Files
ack-tegra/drivers/clk
Alex Frid 7a7ebd4523 clk: soc: tegra: Add DFLL tune high margin voltage
Added DFLL tune high margin voltage entry in CVB table. This allows to
replace current fixed margin defined as number of DFLL voltage steps
with per-table/per-chip margin in millivolts, and convert it to steps
during DFLL initialization.

Bug 1967884

Change-Id: I56268ae2faf9cc633b9f988cacbfd0ea3ba77ff3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576307
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2026-08-24 18:39:45 -05:00
..
2026-02-02 16:42:07 -08:00
2025-07-26 23:49:18 -07:00
2024-10-17 12:02:42 -07:00
2026-08-19 00:26:51 -05:00
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