Merge tag 'phy-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next
Vinod writes:
phy-for-5.20
- New support:
- Samsung FSD ufs phy
- Mediatek MT8365 dsi and tphy support
- Amlogic G12A Analog D-PHY driver
- Mediatek MT8188 tphy support
- Mediatek PCIe phy driver
- Cadence J721e DPHY support
- Qualcomm IPQ8074 PCIe Gen3 PHY support
- Nvidia Tegra PCIe PIPE2UPHY support
- Updates:
- Split of Qualcomm combo qmp phy driver to ufs, usb, pcie phy
drivers and associated cleanup of these drivers
* tag 'phy-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (115 commits)
dt-bindings: phy: mediatek: tphy: add compatible for mt8188
phy: rockchip-inno-usb2: Ignore OTG IRQs in host mode
phy: qcom-qmp-usb: statify qmp_phy_vreg_l
phy: stm32: fix error return in stm32_usbphyc_phy_init
phy: phy-mtk-dp: change mtk_dp_phy_driver to static
phy: freescale: Add i.MX8qm Mixel LVDS PHY support
dt-bindings: phy: Add Freescale i.MX8qm Mixel LVDS PHY binding
dt-bindings: vendor-prefixes: Add prefix for Mixel, Inc.
phy: cadence-torrent: Remove unused `regmap` field from state struct
phy: cadence: Sierra: Remove unused `regmap` field from state struct
phy: samsung-ufs: ufs: change phy on/off control
phy: samsung-ufs: convert phy clk usage to clk_bulk API
phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register
phy: qcom-qmp-usb: replace FLL layout writes for msm8996
phy: qcom-qmp: pcs-pcie-v4: add missing registers
phy: qcom-qmp: pcs-v3: add missing registers
phy: qcom-qmp: qserdes-com-v5: add missing registers
phy: qcom-qmp: qserdes-com-v4: add missing registers
phy: qcom-qmp: qserdes-com-v3: add missing registers
phy: qcom-qmp: qserdes-com: add missing registers
...
This commit is contained in:
Greg Kroah-Hartman
@@ -0,0 +1,35 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Amlogic G12A MIPI analog PHY
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: amlogic,g12a-mipi-dphy-analog
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#phy-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy@0 {
|
||||
compatible = "amlogic,g12a-mipi-dphy-analog";
|
||||
reg = <0x0 0xc>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
@@ -11,8 +11,9 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: cdns,dphy
|
||||
enum:
|
||||
- cdns,dphy
|
||||
- ti,j721e-dphy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mixel LVDS PHY for Freescale i.MX8qm SoC
|
||||
|
||||
maintainers:
|
||||
- Liu Ying <victor.liu@nxp.com>
|
||||
|
||||
description: |
|
||||
The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
|
||||
It converts two groups of four 7/10 bits of CMOS data into two
|
||||
groups of four data lanes of LVDS data streams. A phase-locked
|
||||
transmit clock is transmitted in parallel with each group of
|
||||
data streams over a fifth LVDS link. Every cycle of the transmit
|
||||
clock, 56/80 bits of input data are sampled and transmitted
|
||||
through the two groups of LVDS data streams. Together with the
|
||||
transmit clocks, the two groups of LVDS data streams form two
|
||||
LVDS channels.
|
||||
|
||||
The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
|
||||
by Control and Status Registers(CSR) module in the SoC. The CSR
|
||||
module, as a system controller, contains the PHY's registers.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx8qm-lvds-phy
|
||||
- mixel,28fdsoi-lvds-1250-8ch-tx-pll
|
||||
|
||||
"#phy-cells":
|
||||
const: 1
|
||||
description: |
|
||||
Cell allows setting the LVDS channel index of the PHY.
|
||||
Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#phy-cells"
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/firmware/imx/rsrc.h>
|
||||
phy {
|
||||
compatible = "fsl,imx8qm-lvds-phy";
|
||||
#phy-cells = <1>;
|
||||
clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
|
||||
power-domains = <&pd IMX_SC_R_LVDS_0>;
|
||||
};
|
||||
@@ -24,6 +24,10 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt7623-mipi-tx
|
||||
- const: mediatek,mt2701-mipi-tx
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8365-mipi-tx
|
||||
- const: mediatek,mt8183-mipi-tx
|
||||
- const: mediatek,mt2701-mipi-tx
|
||||
- const: mediatek,mt8173-mipi-tx
|
||||
- const: mediatek,mt8183-mipi-tx
|
||||
|
||||
@@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek PCIe PHY
|
||||
|
||||
maintainers:
|
||||
- Jianjun Wang <jianjun.wang@mediatek.com>
|
||||
|
||||
description: |
|
||||
The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt8195-pcie-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: sif
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
nvmem-cells:
|
||||
maxItems: 7
|
||||
description:
|
||||
Phandles to nvmem cell that contains the efuse data, if unspecified,
|
||||
default value is used.
|
||||
|
||||
nvmem-cell-names:
|
||||
items:
|
||||
- const: glb_intr
|
||||
- const: tx_ln0_pmos
|
||||
- const: tx_ln0_nmos
|
||||
- const: rx_ln0
|
||||
- const: tx_ln1_pmos
|
||||
- const: tx_ln1_nmos
|
||||
- const: rx_ln1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- "#phy-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy@11e80000 {
|
||||
compatible = "mediatek,mt8195-pcie-phy";
|
||||
#phy-cells = <0>;
|
||||
reg = <0x11e80000 0x10000>;
|
||||
reg-names = "sif";
|
||||
nvmem-cells = <&pciephy_glb_intr>,
|
||||
<&pciephy_tx_ln0_pmos>,
|
||||
<&pciephy_tx_ln0_nmos>,
|
||||
<&pciephy_rx_ln0>,
|
||||
<&pciephy_tx_ln1_pmos>,
|
||||
<&pciephy_tx_ln1_nmos>,
|
||||
<&pciephy_rx_ln1>;
|
||||
nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
|
||||
"tx_ln0_nmos", "rx_ln0",
|
||||
"tx_ln1_pmos", "tx_ln1_nmos",
|
||||
"rx_ln1";
|
||||
power-domains = <&spm 2>;
|
||||
};
|
||||
@@ -82,9 +82,11 @@ properties:
|
||||
- mediatek,mt8183-tphy
|
||||
- mediatek,mt8186-tphy
|
||||
- mediatek,mt8192-tphy
|
||||
- mediatek,mt8365-tphy
|
||||
- const: mediatek,generic-tphy-v2
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-tphy
|
||||
- mediatek,mt8195-tphy
|
||||
- const: mediatek,generic-tphy-v3
|
||||
- const: mediatek,mt2701-u3phy
|
||||
|
||||
@@ -8,6 +8,7 @@ Required properties:
|
||||
* "fsl,vf610-usbphy" for Vybrid vf610
|
||||
* "fsl,imx6sx-usbphy" for imx6sx
|
||||
* "fsl,imx7ulp-usbphy" for imx7ulp
|
||||
* "fsl,imx8dxl-usbphy" for imx8dxl
|
||||
"fsl,imx23-usbphy" is still a fallback for other strings
|
||||
- reg: Should contain registers location and length
|
||||
- interrupts: Should contain phy interrupt
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: NVIDIA Tegra194 P2U binding
|
||||
title: NVIDIA Tegra194 & Tegra234 P2U binding
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <treding@nvidia.com>
|
||||
@@ -12,13 +12,17 @@ maintainers:
|
||||
description: >
|
||||
Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
|
||||
Speed) each interfacing with 12 and 8 P2U instances respectively.
|
||||
Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
|
||||
each interfacing with 8, 8 and 8 P2U instances respectively.
|
||||
A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
|
||||
interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
|
||||
lane.
|
||||
interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
|
||||
PCIe lane.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra194-p2u
|
||||
enum:
|
||||
- nvidia,tegra194-p2u
|
||||
- nvidia,tegra234-p2u
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -28,6 +32,11 @@ properties:
|
||||
items:
|
||||
- const: ctl
|
||||
|
||||
nvidia,skip-sz-protect-en:
|
||||
description: Should be present if two PCIe retimers are present between
|
||||
the root port and its immediate downstream device.
|
||||
type: boolean
|
||||
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
|
||||
@@ -41,6 +41,9 @@ properties:
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
vdda-phy-supply: true
|
||||
vdda-pll-supply: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -65,5 +68,8 @@ examples:
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vdda-phy-supply = <&vdd_a_edp_0_1p2>;
|
||||
vdda-pll-supply = <&vdd_a_edp_0_0p9>;
|
||||
};
|
||||
...
|
||||
|
||||
@@ -19,6 +19,7 @@ properties:
|
||||
enum:
|
||||
- qcom,ipq6018-qmp-pcie-phy
|
||||
- qcom,ipq6018-qmp-usb3-phy
|
||||
- qcom,ipq8074-qmp-gen3-pcie-phy
|
||||
- qcom,ipq8074-qmp-pcie-phy
|
||||
- qcom,ipq8074-qmp-usb3-phy
|
||||
- qcom,msm8996-qmp-pcie-phy
|
||||
@@ -312,6 +313,7 @@ allOf:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,ipq6018-qmp-pcie-phy
|
||||
- qcom,ipq8074-qmp-gen3-pcie-phy
|
||||
- qcom,ipq8074-qmp-pcie-phy
|
||||
then:
|
||||
properties:
|
||||
|
||||
@@ -34,7 +34,7 @@ properties:
|
||||
# must not be 0.
|
||||
minItems: 2
|
||||
items:
|
||||
- const: usb3-if # The funcional clock
|
||||
- const: usb3-if # The functional clock
|
||||
- const: usb3s_clk # The usb3's external clock
|
||||
- const: usb_extal # The usb2's external clock
|
||||
|
||||
|
||||
@@ -17,6 +17,7 @@ properties:
|
||||
enum:
|
||||
- samsung,exynos7-ufs-phy
|
||||
- samsung,exynosautov9-ufs-phy
|
||||
- tesla,fsd-ufs-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -40,9 +41,17 @@ properties:
|
||||
- const: tx0_symbol_clk
|
||||
|
||||
samsung,pmu-syscon:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: phandle for PMU system controller interface, used to
|
||||
control pmu registers bits for ufs m-phy
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
maxItems: 1
|
||||
items:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: phandle for PMU system controller interface, used to
|
||||
control pmu registers bits for ufs m-phy
|
||||
- description: offset of the pmu control register
|
||||
description:
|
||||
It can be phandle/offset pair. The second cell which can represent an
|
||||
offset is optional.
|
||||
|
||||
required:
|
||||
- "#phy-cells"
|
||||
|
||||
@@ -795,6 +795,8 @@ patternProperties:
|
||||
description: MiraMEMS Sensing Technology Co., Ltd.
|
||||
"^mitsubishi,.*":
|
||||
description: Mitsubishi Electric Corporation
|
||||
"^mixel,.*":
|
||||
description: Mixel, Inc.
|
||||
"^miyoo,.*":
|
||||
description: Miyoo
|
||||
"^mntre,.*":
|
||||
|
||||
@@ -6794,6 +6794,7 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/display/mediatek/
|
||||
F: drivers/gpu/drm/mediatek/
|
||||
F: drivers/phy/mediatek/phy-mtk-dp.c
|
||||
F: drivers/phy/mediatek/phy-mtk-hdmi*
|
||||
F: drivers/phy/mediatek/phy-mtk-mipi*
|
||||
|
||||
@@ -8420,6 +8421,7 @@ Q: https://patchwork.kernel.org/project/linux-phy/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git
|
||||
F: Documentation/devicetree/bindings/phy/
|
||||
F: drivers/phy/
|
||||
F: include/dt-bindings/phy/
|
||||
F: include/linux/phy/
|
||||
|
||||
GENERIC PINCTRL I2C DEMULTIPLEXER DRIVER
|
||||
|
||||
@@ -22,14 +22,6 @@
|
||||
#define DP_DEFAULT_P0_OFFSET 0x1000
|
||||
#define DP_DEFAULT_P0_SIZE 0x0400
|
||||
|
||||
static const struct dp_regulator_cfg sdm845_dp_reg_cfg = {
|
||||
.num = 2,
|
||||
.regs = {
|
||||
{"vdda-1p2", 21800, 4 }, /* 1.2 V */
|
||||
{"vdda-0p9", 36000, 32 }, /* 0.9 V */
|
||||
},
|
||||
};
|
||||
|
||||
static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len)
|
||||
{
|
||||
struct resource *res;
|
||||
@@ -298,12 +290,6 @@ static int dp_parser_parse(struct dp_parser *parser)
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* Map the corresponding regulator information according to
|
||||
* version. Currently, since we only have one supported platform,
|
||||
* mapping the regulator directly.
|
||||
*/
|
||||
parser->regulator_cfg = &sdm845_dp_reg_cfg;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -92,8 +92,6 @@ struct dp_pinctrl {
|
||||
struct pinctrl_state *state_suspend;
|
||||
};
|
||||
|
||||
#define DP_DEV_REGULATOR_MAX 4
|
||||
|
||||
/* Regulators for DP devices */
|
||||
struct dp_reg_entry {
|
||||
char name[32];
|
||||
@@ -101,11 +99,6 @@ struct dp_reg_entry {
|
||||
int disable_load;
|
||||
};
|
||||
|
||||
struct dp_regulator_cfg {
|
||||
int num;
|
||||
struct dp_reg_entry regs[DP_DEV_REGULATOR_MAX];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dp_parser - DP parser's data exposed to clients
|
||||
*
|
||||
@@ -121,7 +114,6 @@ struct dp_parser {
|
||||
struct dp_pinctrl pinctrl;
|
||||
struct dp_io io;
|
||||
struct dp_display_data disp_data;
|
||||
const struct dp_regulator_cfg *regulator_cfg;
|
||||
u32 max_dp_lanes;
|
||||
struct drm_bridge *next_bridge;
|
||||
|
||||
|
||||
@@ -20,82 +20,10 @@ struct dp_power_private {
|
||||
struct clk *link_clk_src;
|
||||
struct clk *pixel_provider;
|
||||
struct clk *link_provider;
|
||||
struct regulator_bulk_data supplies[DP_DEV_REGULATOR_MAX];
|
||||
|
||||
struct dp_power dp_power;
|
||||
};
|
||||
|
||||
static void dp_power_regulator_disable(struct dp_power_private *power)
|
||||
{
|
||||
struct regulator_bulk_data *s = power->supplies;
|
||||
const struct dp_reg_entry *regs = power->parser->regulator_cfg->regs;
|
||||
int num = power->parser->regulator_cfg->num;
|
||||
int i;
|
||||
|
||||
DBG("");
|
||||
for (i = num - 1; i >= 0; i--)
|
||||
if (regs[i].disable_load >= 0)
|
||||
regulator_set_load(s[i].consumer,
|
||||
regs[i].disable_load);
|
||||
|
||||
regulator_bulk_disable(num, s);
|
||||
}
|
||||
|
||||
static int dp_power_regulator_enable(struct dp_power_private *power)
|
||||
{
|
||||
struct regulator_bulk_data *s = power->supplies;
|
||||
const struct dp_reg_entry *regs = power->parser->regulator_cfg->regs;
|
||||
int num = power->parser->regulator_cfg->num;
|
||||
int ret, i;
|
||||
|
||||
DBG("");
|
||||
for (i = 0; i < num; i++) {
|
||||
if (regs[i].enable_load >= 0) {
|
||||
ret = regulator_set_load(s[i].consumer,
|
||||
regs[i].enable_load);
|
||||
if (ret < 0) {
|
||||
pr_err("regulator %d set op mode failed, %d\n",
|
||||
i, ret);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ret = regulator_bulk_enable(num, s);
|
||||
if (ret < 0) {
|
||||
pr_err("regulator enable failed, %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
for (i--; i >= 0; i--)
|
||||
regulator_set_load(s[i].consumer, regs[i].disable_load);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int dp_power_regulator_init(struct dp_power_private *power)
|
||||
{
|
||||
struct regulator_bulk_data *s = power->supplies;
|
||||
const struct dp_reg_entry *regs = power->parser->regulator_cfg->regs;
|
||||
struct platform_device *pdev = power->pdev;
|
||||
int num = power->parser->regulator_cfg->num;
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < num; i++)
|
||||
s[i].supply = regs[i].name;
|
||||
|
||||
ret = devm_regulator_bulk_get(&pdev->dev, num, s);
|
||||
if (ret < 0) {
|
||||
pr_err("%s: failed to init regulator, ret=%d\n",
|
||||
__func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dp_power_clk_init(struct dp_power_private *power)
|
||||
{
|
||||
int rc = 0;
|
||||
@@ -318,21 +246,10 @@ int dp_power_client_init(struct dp_power *dp_power)
|
||||
|
||||
pm_runtime_enable(&power->pdev->dev);
|
||||
|
||||
rc = dp_power_regulator_init(power);
|
||||
if (rc) {
|
||||
DRM_ERROR("failed to init regulators %d\n", rc);
|
||||
goto error;
|
||||
}
|
||||
|
||||
rc = dp_power_clk_init(power);
|
||||
if (rc) {
|
||||
if (rc)
|
||||
DRM_ERROR("failed to init clocks %d\n", rc);
|
||||
goto error;
|
||||
}
|
||||
return 0;
|
||||
|
||||
error:
|
||||
pm_runtime_disable(&power->pdev->dev);
|
||||
return rc;
|
||||
}
|
||||
|
||||
@@ -365,22 +282,15 @@ int dp_power_init(struct dp_power *dp_power, bool flip)
|
||||
power = container_of(dp_power, struct dp_power_private, dp_power);
|
||||
|
||||
pm_runtime_get_sync(&power->pdev->dev);
|
||||
rc = dp_power_regulator_enable(power);
|
||||
if (rc) {
|
||||
DRM_ERROR("failed to enable regulators, %d\n", rc);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
|
||||
if (rc) {
|
||||
DRM_ERROR("failed to enable DP core clocks, %d\n", rc);
|
||||
goto err_clk;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk:
|
||||
dp_power_regulator_disable(power);
|
||||
exit:
|
||||
pm_runtime_put_sync(&power->pdev->dev);
|
||||
return rc;
|
||||
@@ -393,7 +303,6 @@ int dp_power_deinit(struct dp_power *dp_power)
|
||||
power = container_of(dp_power, struct dp_power_private, dp_power);
|
||||
|
||||
dp_power_clk_enable(dp_power, DP_CORE_PM, false);
|
||||
dp_power_regulator_disable(power);
|
||||
pm_runtime_put_sync(&power->pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -37,6 +37,18 @@ config PHY_MESON_GXL_USB2
|
||||
GXL and GXM SoCs.
|
||||
If unsure, say N.
|
||||
|
||||
config PHY_MESON_G12A_MIPI_DPHY_ANALOG
|
||||
tristate "Meson G12A MIPI Analog DPHY driver"
|
||||
default ARCH_MESON
|
||||
depends on OF && (ARCH_MESON || COMPILE_TEST)
|
||||
select GENERIC_PHY
|
||||
select MFD_SYSCON
|
||||
select GENERIC_PHY_MIPI_DPHY
|
||||
help
|
||||
Enable this to support the Meson MIPI Analog DPHY found in Meson G12A
|
||||
SoCs.
|
||||
If unsure, say N.
|
||||
|
||||
config PHY_MESON_G12A_USB2
|
||||
tristate "Meson G12A USB2 PHY driver"
|
||||
default ARCH_MESON
|
||||
|
||||
@@ -4,6 +4,7 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
|
||||
obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
|
||||
obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o
|
||||
obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o
|
||||
obj-$(CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG) += phy-meson-g12a-mipi-dphy-analog.o
|
||||
obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o
|
||||
obj-$(CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG) += phy-meson-axg-mipi-pcie-analog.o
|
||||
obj-$(CONFIG_PHY_MESON_AXG_MIPI_DPHY) += phy-meson-axg-mipi-dphy.o
|
||||
|
||||
@@ -136,7 +136,7 @@
|
||||
/* TWAKEUP. */
|
||||
#define MIPI_DSI_WAKEUP_TIM 0x20
|
||||
|
||||
/* when in RxULPS check state, after the the logic enable the analog,
|
||||
/* when in RxULPS check state, after the logic enable the analog,
|
||||
* how long we should wait to check the lP state .
|
||||
*/
|
||||
#define MIPI_DSI_LPOK_TIM 0x24
|
||||
|
||||
@@ -0,0 +1,171 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Meson G12A MIPI DSI Analog PHY
|
||||
*
|
||||
* Copyright (C) 2018 Amlogic, Inc. All rights reserved
|
||||
* Copyright (C) 2022 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
#define HHI_MIPI_CNTL0 0x00
|
||||
#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(31, 16)
|
||||
#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
|
||||
|
||||
#define HHI_MIPI_CNTL1 0x04
|
||||
#define HHI_MIPI_CNTL1_BANDGAP BIT(16)
|
||||
#define HHI_MIPI_CNTL2_DIF_REF_CTL2 GENMASK(15, 0)
|
||||
|
||||
#define HHI_MIPI_CNTL2 0x08
|
||||
#define HHI_MIPI_CNTL2_DIF_TX_CTL1 GENMASK(31, 16)
|
||||
#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)
|
||||
#define HHI_MIPI_CNTL2_DIF_TX_CTL0 GENMASK(10, 0)
|
||||
|
||||
#define DSI_LANE_0 BIT(4)
|
||||
#define DSI_LANE_1 BIT(3)
|
||||
#define DSI_LANE_CLK BIT(2)
|
||||
#define DSI_LANE_2 BIT(1)
|
||||
#define DSI_LANE_3 BIT(0)
|
||||
|
||||
struct phy_g12a_mipi_dphy_analog_priv {
|
||||
struct phy *phy;
|
||||
struct regmap *regmap;
|
||||
struct phy_configure_opts_mipi_dphy config;
|
||||
};
|
||||
|
||||
static int phy_g12a_mipi_dphy_analog_configure(struct phy *phy,
|
||||
union phy_configure_opts *opts)
|
||||
{
|
||||
struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
|
||||
ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
memcpy(&priv->config, opts, sizeof(priv->config));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy)
|
||||
{
|
||||
struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
|
||||
unsigned int reg;
|
||||
|
||||
regmap_write(priv->regmap, HHI_MIPI_CNTL0,
|
||||
FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8) |
|
||||
FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0xa487));
|
||||
|
||||
regmap_write(priv->regmap, HHI_MIPI_CNTL1,
|
||||
FIELD_PREP(HHI_MIPI_CNTL2_DIF_REF_CTL2, 0x2e) |
|
||||
HHI_MIPI_CNTL1_BANDGAP);
|
||||
|
||||
regmap_write(priv->regmap, HHI_MIPI_CNTL2,
|
||||
FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x459) |
|
||||
FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL1, 0x2680));
|
||||
|
||||
reg = DSI_LANE_CLK;
|
||||
switch (priv->config.lanes) {
|
||||
case 4:
|
||||
reg |= DSI_LANE_3;
|
||||
fallthrough;
|
||||
case 3:
|
||||
reg |= DSI_LANE_2;
|
||||
fallthrough;
|
||||
case 2:
|
||||
reg |= DSI_LANE_1;
|
||||
fallthrough;
|
||||
case 1:
|
||||
reg |= DSI_LANE_0;
|
||||
break;
|
||||
default:
|
||||
reg = 0;
|
||||
}
|
||||
|
||||
regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2,
|
||||
HHI_MIPI_CNTL2_CH_EN,
|
||||
FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_g12a_mipi_dphy_analog_power_off(struct phy *phy)
|
||||
{
|
||||
struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
|
||||
|
||||
regmap_write(priv->regmap, HHI_MIPI_CNTL0, 0);
|
||||
regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0);
|
||||
regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops phy_g12a_mipi_dphy_analog_ops = {
|
||||
.configure = phy_g12a_mipi_dphy_analog_configure,
|
||||
.power_on = phy_g12a_mipi_dphy_analog_power_on,
|
||||
.power_off = phy_g12a_mipi_dphy_analog_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int phy_g12a_mipi_dphy_analog_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct phy_provider *phy;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct phy_g12a_mipi_dphy_analog_priv *priv;
|
||||
struct device_node *np = dev->of_node, *parent_np;
|
||||
struct regmap *map;
|
||||
|
||||
priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Get the hhi system controller node */
|
||||
parent_np = of_get_parent(np);
|
||||
map = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(map))
|
||||
return dev_err_probe(dev, PTR_ERR(map), "failed to get HHI regmap\n");
|
||||
|
||||
priv->regmap = map;
|
||||
|
||||
priv->phy = devm_phy_create(dev, np, &phy_g12a_mipi_dphy_analog_ops);
|
||||
if (IS_ERR(priv->phy))
|
||||
return dev_err_probe(dev, PTR_ERR(priv->phy), "failed to create PHY\n");
|
||||
|
||||
phy_set_drvdata(priv->phy, priv);
|
||||
dev_set_drvdata(dev, priv);
|
||||
|
||||
phy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
|
||||
return PTR_ERR_OR_ZERO(phy);
|
||||
}
|
||||
|
||||
static const struct of_device_id phy_g12a_mipi_dphy_analog_of_match[] = {
|
||||
{
|
||||
.compatible = "amlogic,g12a-mipi-dphy-analog",
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, phy_g12a_mipi_dphy_analog_of_match);
|
||||
|
||||
static struct platform_driver phy_g12a_mipi_dphy_analog_driver = {
|
||||
.probe = phy_g12a_mipi_dphy_analog_probe,
|
||||
.driver = {
|
||||
.name = "phy-meson-g12a-mipi-dphy-analog",
|
||||
.of_match_table = phy_g12a_mipi_dphy_analog_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(phy_g12a_mipi_dphy_analog_driver);
|
||||
|
||||
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
||||
MODULE_DESCRIPTION("Meson G12A MIPI Analog D-PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@@ -861,7 +861,7 @@ static void usb_init_common(struct brcm_usb_init_params *params)
|
||||
brcmusb_usb2_eye_fix(ctrl);
|
||||
|
||||
/*
|
||||
* Make sure the the second and third memory controller
|
||||
* Make sure the second and third memory controller
|
||||
* interfaces are enabled if they exist.
|
||||
*/
|
||||
if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN))
|
||||
|
||||
@@ -3,9 +3,11 @@
|
||||
* Copyright: 2017-2018 Cadence Design Systems, Inc.
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
@@ -17,6 +19,7 @@
|
||||
|
||||
#define REG_WAKEUP_TIME_NS 800
|
||||
#define DPHY_PLL_RATE_HZ 108000000
|
||||
#define POLL_TIMEOUT_US 1000
|
||||
|
||||
/* DPHY registers */
|
||||
#define DPHY_PMA_CMN(reg) (reg)
|
||||
@@ -45,6 +48,10 @@
|
||||
#define DPHY_CMN_OPDIV_FROM_REG BIT(6)
|
||||
#define DPHY_CMN_OPDIV(x) ((x) << 7)
|
||||
|
||||
#define DPHY_BAND_CFG DPHY_PCS(0x0)
|
||||
#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0)
|
||||
#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5)
|
||||
|
||||
#define DPHY_PSM_CFG DPHY_PCS(0x4)
|
||||
#define DPHY_PSM_CFG_FROM_REG BIT(0)
|
||||
#define DPHY_PSM_CLK_DIV(x) ((x) << 1)
|
||||
@@ -57,6 +64,18 @@
|
||||
#define DSI_NULL_FRAME_OVERHEAD 6
|
||||
#define DSI_EOT_PKT_SIZE 4
|
||||
|
||||
#define DPHY_TX_J721E_WIZ_PLL_CTRL 0xF04
|
||||
#define DPHY_TX_J721E_WIZ_STATUS 0xF08
|
||||
#define DPHY_TX_J721E_WIZ_RST_CTRL 0xF0C
|
||||
#define DPHY_TX_J721E_WIZ_PSM_FREQ 0xF10
|
||||
|
||||
#define DPHY_TX_J721E_WIZ_IPDIV GENMASK(4, 0)
|
||||
#define DPHY_TX_J721E_WIZ_OPDIV GENMASK(13, 8)
|
||||
#define DPHY_TX_J721E_WIZ_FBDIV GENMASK(25, 16)
|
||||
#define DPHY_TX_J721E_WIZ_LANE_RSTB BIT(31)
|
||||
#define DPHY_TX_WIZ_PLL_LOCK BIT(31)
|
||||
#define DPHY_TX_WIZ_O_CMN_READY BIT(31)
|
||||
|
||||
struct cdns_dphy_cfg {
|
||||
u8 pll_ipdiv;
|
||||
u8 pll_opdiv;
|
||||
@@ -92,6 +111,12 @@ struct cdns_dphy {
|
||||
struct phy *phy;
|
||||
};
|
||||
|
||||
/* Order of bands is important since the index is the band number. */
|
||||
static const unsigned int tx_bands[] = {
|
||||
80, 100, 120, 160, 200, 240, 320, 390, 450, 510, 560, 640, 690, 770,
|
||||
870, 950, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2500
|
||||
};
|
||||
|
||||
static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
|
||||
struct cdns_dphy_cfg *cfg,
|
||||
struct phy_configure_opts_mipi_dphy *opts,
|
||||
@@ -199,6 +224,46 @@ static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div)
|
||||
dphy->regs + DPHY_PSM_CFG);
|
||||
}
|
||||
|
||||
static unsigned long cdns_dphy_j721e_get_wakeup_time_ns(struct cdns_dphy *dphy)
|
||||
{
|
||||
/* Minimum wakeup time as per MIPI D-PHY spec v1.2 */
|
||||
return 1000000;
|
||||
}
|
||||
|
||||
static void cdns_dphy_j721e_set_pll_cfg(struct cdns_dphy *dphy,
|
||||
const struct cdns_dphy_cfg *cfg)
|
||||
{
|
||||
u32 status;
|
||||
|
||||
/*
|
||||
* set the PWM and PLL Byteclk divider settings to recommended values
|
||||
* which is same as that of in ref ops
|
||||
*/
|
||||
writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
|
||||
DPHY_CMN_PWM_DIV(0x8),
|
||||
dphy->regs + DPHY_CMN_PWM);
|
||||
|
||||
writel((FIELD_PREP(DPHY_TX_J721E_WIZ_IPDIV, cfg->pll_ipdiv) |
|
||||
FIELD_PREP(DPHY_TX_J721E_WIZ_OPDIV, cfg->pll_opdiv) |
|
||||
FIELD_PREP(DPHY_TX_J721E_WIZ_FBDIV, cfg->pll_fbdiv)),
|
||||
dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL);
|
||||
|
||||
writel(DPHY_TX_J721E_WIZ_LANE_RSTB,
|
||||
dphy->regs + DPHY_TX_J721E_WIZ_RST_CTRL);
|
||||
|
||||
readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL, status,
|
||||
(status & DPHY_TX_WIZ_PLL_LOCK), 0, POLL_TIMEOUT_US);
|
||||
|
||||
readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_STATUS, status,
|
||||
(status & DPHY_TX_WIZ_O_CMN_READY), 0,
|
||||
POLL_TIMEOUT_US);
|
||||
}
|
||||
|
||||
static void cdns_dphy_j721e_set_psm_div(struct cdns_dphy *dphy, u8 div)
|
||||
{
|
||||
writel(div, dphy->regs + DPHY_TX_J721E_WIZ_PSM_FREQ);
|
||||
}
|
||||
|
||||
/*
|
||||
* This is the reference implementation of DPHY hooks. Specific integration of
|
||||
* this IP may have to re-implement some of them depending on how they decided
|
||||
@@ -210,6 +275,12 @@ static const struct cdns_dphy_ops ref_dphy_ops = {
|
||||
.set_psm_div = cdns_dphy_ref_set_psm_div,
|
||||
};
|
||||
|
||||
static const struct cdns_dphy_ops j721e_dphy_ops = {
|
||||
.get_wakeup_time_ns = cdns_dphy_j721e_get_wakeup_time_ns,
|
||||
.set_pll_cfg = cdns_dphy_j721e_set_pll_cfg,
|
||||
.set_psm_div = cdns_dphy_j721e_set_psm_div,
|
||||
};
|
||||
|
||||
static int cdns_dphy_config_from_opts(struct phy *phy,
|
||||
struct phy_configure_opts_mipi_dphy *opts,
|
||||
struct cdns_dphy_cfg *cfg)
|
||||
@@ -232,6 +303,24 @@ static int cdns_dphy_config_from_opts(struct phy *phy,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cdns_dphy_tx_get_band_ctrl(unsigned long hs_clk_rate)
|
||||
{
|
||||
unsigned int rate;
|
||||
int i;
|
||||
|
||||
rate = hs_clk_rate / 1000000UL;
|
||||
|
||||
if (rate < tx_bands[0])
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(tx_bands) - 1; i++) {
|
||||
if (rate >= tx_bands[i] && rate < tx_bands[i + 1])
|
||||
return i;
|
||||
}
|
||||
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
|
||||
union phy_configure_opts *opts)
|
||||
{
|
||||
@@ -247,7 +336,8 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
|
||||
{
|
||||
struct cdns_dphy *dphy = phy_get_drvdata(phy);
|
||||
struct cdns_dphy_cfg cfg = { 0 };
|
||||
int ret;
|
||||
int ret, band_ctrl;
|
||||
unsigned int reg;
|
||||
|
||||
ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
|
||||
if (ret)
|
||||
@@ -276,6 +366,14 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
|
||||
*/
|
||||
cdns_dphy_set_pll_cfg(dphy, &cfg);
|
||||
|
||||
band_ctrl = cdns_dphy_tx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);
|
||||
if (band_ctrl < 0)
|
||||
return band_ctrl;
|
||||
|
||||
reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) |
|
||||
FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl);
|
||||
writel(reg, dphy->regs + DPHY_BAND_CFG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -370,6 +468,7 @@ static int cdns_dphy_remove(struct platform_device *pdev)
|
||||
|
||||
static const struct of_device_id cdns_dphy_of_match[] = {
|
||||
{ .compatible = "cdns,dphy", .data = &ref_dphy_ops },
|
||||
{ .compatible = "ti,j721e-dphy", .data = &j721e_dphy_ops },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, cdns_dphy_of_match);
|
||||
|
||||
@@ -348,7 +348,6 @@ struct cdns_regmap_cdb_context {
|
||||
|
||||
struct cdns_sierra_phy {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
const struct cdns_sierra_data *init_data;
|
||||
struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
|
||||
struct reset_control *phy_rst;
|
||||
|
||||
@@ -331,7 +331,6 @@ struct cdns_torrent_phy {
|
||||
struct cdns_torrent_inst phys[MAX_NUM_LANES];
|
||||
int nsubnodes;
|
||||
const struct cdns_torrent_data *init_data;
|
||||
struct regmap *regmap;
|
||||
struct regmap *regmap_common_cdb;
|
||||
struct regmap *regmap_phy_pcs_common_cdb;
|
||||
struct regmap *regmap_phy_pma_common_cdb;
|
||||
|
||||
@@ -8,6 +8,15 @@ config PHY_FSL_IMX8MQ_USB
|
||||
select GENERIC_PHY
|
||||
default ARCH_MXC && ARM64
|
||||
|
||||
config PHY_MIXEL_LVDS_PHY
|
||||
tristate "Mixel LVDS PHY support"
|
||||
depends on OF
|
||||
select GENERIC_PHY
|
||||
select REGMAP_MMIO
|
||||
help
|
||||
Enable this to add support for the Mixel LVDS PHY as found
|
||||
on NXP's i.MX8qm SoC.
|
||||
|
||||
config PHY_MIXEL_MIPI_DPHY
|
||||
tristate "Mixel MIPI DSI PHY support"
|
||||
depends on OF && HAS_IOMEM
|
||||
|
||||
@@ -1,5 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
|
||||
obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
|
||||
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
|
||||
obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
|
||||
obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
|
||||
|
||||
@@ -0,0 +1,450 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2017-2020,2022 NXP
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/units.h>
|
||||
|
||||
#define REG_SET 0x4
|
||||
#define REG_CLR 0x8
|
||||
|
||||
#define PHY_CTRL 0x0
|
||||
#define M_MASK GENMASK(18, 17)
|
||||
#define M(n) FIELD_PREP(M_MASK, (n))
|
||||
#define CCM_MASK GENMASK(16, 14)
|
||||
#define CCM(n) FIELD_PREP(CCM_MASK, (n))
|
||||
#define CA_MASK GENMASK(13, 11)
|
||||
#define CA(n) FIELD_PREP(CA_MASK, (n))
|
||||
#define TST_MASK GENMASK(10, 5)
|
||||
#define TST(n) FIELD_PREP(TST_MASK, (n))
|
||||
#define CH_EN(id) BIT(3 + (id))
|
||||
#define NB BIT(2)
|
||||
#define RFB BIT(1)
|
||||
#define PD BIT(0)
|
||||
|
||||
/* Power On Reset(POR) value */
|
||||
#define CTRL_RESET_VAL (M(0x0) | CCM(0x4) | CA(0x4) | TST(0x25))
|
||||
|
||||
/* PHY initialization value and mask */
|
||||
#define CTRL_INIT_MASK (M_MASK | CCM_MASK | CA_MASK | TST_MASK | NB | RFB)
|
||||
#define CTRL_INIT_VAL (M(0x0) | CCM(0x5) | CA(0x4) | TST(0x25) | RFB)
|
||||
|
||||
#define PHY_STATUS 0x10
|
||||
#define LOCK BIT(0)
|
||||
|
||||
#define PHY_NUM 2
|
||||
|
||||
#define MIN_CLKIN_FREQ (25 * MEGA)
|
||||
#define MAX_CLKIN_FREQ (165 * MEGA)
|
||||
|
||||
#define PLL_LOCK_SLEEP 10
|
||||
#define PLL_LOCK_TIMEOUT 1000
|
||||
|
||||
struct mixel_lvds_phy {
|
||||
struct phy *phy;
|
||||
struct phy_configure_opts_lvds cfg;
|
||||
unsigned int id;
|
||||
};
|
||||
|
||||
struct mixel_lvds_phy_priv {
|
||||
struct regmap *regmap;
|
||||
struct mutex lock; /* protect remap access and cfg of our own */
|
||||
struct clk *phy_ref_clk;
|
||||
struct mixel_lvds_phy *phys[PHY_NUM];
|
||||
};
|
||||
|
||||
static int mixel_lvds_phy_init(struct phy *phy)
|
||||
{
|
||||
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
|
||||
|
||||
mutex_lock(&priv->lock);
|
||||
regmap_update_bits(priv->regmap,
|
||||
PHY_CTRL, CTRL_INIT_MASK, CTRL_INIT_VAL);
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mixel_lvds_phy_power_on(struct phy *phy)
|
||||
{
|
||||
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
|
||||
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
|
||||
struct mixel_lvds_phy *companion = priv->phys[lvds_phy->id ^ 1];
|
||||
struct phy_configure_opts_lvds *cfg = &lvds_phy->cfg;
|
||||
u32 val = 0;
|
||||
u32 locked;
|
||||
int ret;
|
||||
|
||||
/* The master PHY would power on the slave PHY. */
|
||||
if (cfg->is_slave)
|
||||
return 0;
|
||||
|
||||
ret = clk_prepare_enable(priv->phy_ref_clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&phy->dev,
|
||||
"failed to enable PHY reference clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
mutex_lock(&priv->lock);
|
||||
if (cfg->bits_per_lane_and_dclk_cycle == 7) {
|
||||
if (cfg->differential_clk_rate < 44000000)
|
||||
val |= M(0x2);
|
||||
else if (cfg->differential_clk_rate < 90000000)
|
||||
val |= M(0x1);
|
||||
else
|
||||
val |= M(0x0);
|
||||
} else {
|
||||
val = NB;
|
||||
|
||||
if (cfg->differential_clk_rate < 32000000)
|
||||
val |= M(0x2);
|
||||
else if (cfg->differential_clk_rate < 63000000)
|
||||
val |= M(0x1);
|
||||
else
|
||||
val |= M(0x0);
|
||||
}
|
||||
regmap_update_bits(priv->regmap, PHY_CTRL, M_MASK | NB, val);
|
||||
|
||||
/*
|
||||
* Enable two channels synchronously,
|
||||
* if the companion PHY is a slave PHY.
|
||||
*/
|
||||
if (companion->cfg.is_slave)
|
||||
val = CH_EN(0) | CH_EN(1);
|
||||
else
|
||||
val = CH_EN(lvds_phy->id);
|
||||
regmap_write(priv->regmap, PHY_CTRL + REG_SET, val);
|
||||
|
||||
ret = regmap_read_poll_timeout(priv->regmap, PHY_STATUS, locked,
|
||||
locked, PLL_LOCK_SLEEP,
|
||||
PLL_LOCK_TIMEOUT);
|
||||
if (ret < 0) {
|
||||
dev_err(&phy->dev, "failed to get PHY lock: %d\n", ret);
|
||||
clk_disable_unprepare(priv->phy_ref_clk);
|
||||
}
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mixel_lvds_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
|
||||
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
|
||||
struct mixel_lvds_phy *companion = priv->phys[lvds_phy->id ^ 1];
|
||||
struct phy_configure_opts_lvds *cfg = &lvds_phy->cfg;
|
||||
|
||||
/* The master PHY would power off the slave PHY. */
|
||||
if (cfg->is_slave)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&priv->lock);
|
||||
if (companion->cfg.is_slave)
|
||||
regmap_write(priv->regmap, PHY_CTRL + REG_CLR,
|
||||
CH_EN(0) | CH_EN(1));
|
||||
else
|
||||
regmap_write(priv->regmap, PHY_CTRL + REG_CLR,
|
||||
CH_EN(lvds_phy->id));
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
clk_disable_unprepare(priv->phy_ref_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mixel_lvds_phy_configure(struct phy *phy,
|
||||
union phy_configure_opts *opts)
|
||||
{
|
||||
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
|
||||
struct phy_configure_opts_lvds *cfg = &opts->lvds;
|
||||
int ret;
|
||||
|
||||
ret = clk_set_rate(priv->phy_ref_clk, cfg->differential_clk_rate);
|
||||
if (ret)
|
||||
dev_err(&phy->dev, "failed to set PHY reference clock rate(%lu): %d\n",
|
||||
cfg->differential_clk_rate, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Assume the master PHY's configuration set is cached first. */
|
||||
static int mixel_lvds_phy_check_slave(struct phy *slave_phy)
|
||||
{
|
||||
struct device *dev = &slave_phy->dev;
|
||||
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev->parent);
|
||||
struct mixel_lvds_phy *slv = phy_get_drvdata(slave_phy);
|
||||
struct mixel_lvds_phy *mst = priv->phys[slv->id ^ 1];
|
||||
struct phy_configure_opts_lvds *mst_cfg = &mst->cfg;
|
||||
struct phy_configure_opts_lvds *slv_cfg = &slv->cfg;
|
||||
|
||||
if (mst_cfg->bits_per_lane_and_dclk_cycle !=
|
||||
slv_cfg->bits_per_lane_and_dclk_cycle) {
|
||||
dev_err(dev, "number bits mismatch(mst: %u vs slv: %u)\n",
|
||||
mst_cfg->bits_per_lane_and_dclk_cycle,
|
||||
slv_cfg->bits_per_lane_and_dclk_cycle);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (mst_cfg->differential_clk_rate !=
|
||||
slv_cfg->differential_clk_rate) {
|
||||
dev_err(dev, "dclk rate mismatch(mst: %lu vs slv: %lu)\n",
|
||||
mst_cfg->differential_clk_rate,
|
||||
slv_cfg->differential_clk_rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (mst_cfg->lanes != slv_cfg->lanes) {
|
||||
dev_err(dev, "lanes mismatch(mst: %u vs slv: %u)\n",
|
||||
mst_cfg->lanes, slv_cfg->lanes);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (mst_cfg->is_slave == slv_cfg->is_slave) {
|
||||
dev_err(dev, "master PHY is not found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mixel_lvds_phy_validate(struct phy *phy, enum phy_mode mode,
|
||||
int submode, union phy_configure_opts *opts)
|
||||
{
|
||||
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
|
||||
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
|
||||
struct phy_configure_opts_lvds *cfg = &opts->lvds;
|
||||
int ret = 0;
|
||||
|
||||
if (mode != PHY_MODE_LVDS) {
|
||||
dev_err(&phy->dev, "invalid PHY mode(%d)\n", mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (cfg->bits_per_lane_and_dclk_cycle != 7 &&
|
||||
cfg->bits_per_lane_and_dclk_cycle != 10) {
|
||||
dev_err(&phy->dev, "invalid bits per data lane(%u)\n",
|
||||
cfg->bits_per_lane_and_dclk_cycle);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (cfg->lanes != 4 && cfg->lanes != 3) {
|
||||
dev_err(&phy->dev, "invalid data lanes(%u)\n", cfg->lanes);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (cfg->differential_clk_rate < MIN_CLKIN_FREQ ||
|
||||
cfg->differential_clk_rate > MAX_CLKIN_FREQ) {
|
||||
dev_err(&phy->dev, "invalid differential clock rate(%lu)\n",
|
||||
cfg->differential_clk_rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mutex_lock(&priv->lock);
|
||||
/* cache configuration set of our own for check */
|
||||
memcpy(&lvds_phy->cfg, cfg, sizeof(*cfg));
|
||||
|
||||
if (cfg->is_slave) {
|
||||
ret = mixel_lvds_phy_check_slave(phy);
|
||||
if (ret)
|
||||
dev_err(&phy->dev, "failed to check slave PHY: %d\n", ret);
|
||||
}
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct phy_ops mixel_lvds_phy_ops = {
|
||||
.init = mixel_lvds_phy_init,
|
||||
.power_on = mixel_lvds_phy_power_on,
|
||||
.power_off = mixel_lvds_phy_power_off,
|
||||
.configure = mixel_lvds_phy_configure,
|
||||
.validate = mixel_lvds_phy_validate,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int mixel_lvds_phy_reset(struct device *dev)
|
||||
{
|
||||
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(dev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to get PM runtime: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
regmap_write(priv->regmap, PHY_CTRL, CTRL_RESET_VAL);
|
||||
|
||||
ret = pm_runtime_put(dev);
|
||||
if (ret < 0)
|
||||
dev_err(dev, "failed to put PM runtime: %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct phy *mixel_lvds_phy_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev);
|
||||
unsigned int phy_id;
|
||||
|
||||
if (args->args_count != 1) {
|
||||
dev_err(dev,
|
||||
"invalid argument number(%d) for 'phys' property\n",
|
||||
args->args_count);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
phy_id = args->args[0];
|
||||
|
||||
if (phy_id >= PHY_NUM) {
|
||||
dev_err(dev, "invalid PHY index(%d)\n", phy_id);
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
return priv->phys[phy_id]->phy;
|
||||
}
|
||||
|
||||
static int mixel_lvds_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct phy_provider *phy_provider;
|
||||
struct mixel_lvds_phy_priv *priv;
|
||||
struct mixel_lvds_phy *lvds_phy;
|
||||
struct phy *phy;
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
if (!dev->of_node)
|
||||
return -ENODEV;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->regmap = syscon_node_to_regmap(dev->of_node->parent);
|
||||
if (IS_ERR(priv->regmap))
|
||||
return dev_err_probe(dev, PTR_ERR(priv->regmap),
|
||||
"failed to get regmap\n");
|
||||
|
||||
priv->phy_ref_clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(priv->phy_ref_clk))
|
||||
return dev_err_probe(dev, PTR_ERR(priv->phy_ref_clk),
|
||||
"failed to get PHY reference clock\n");
|
||||
|
||||
mutex_init(&priv->lock);
|
||||
|
||||
dev_set_drvdata(dev, priv);
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
ret = mixel_lvds_phy_reset(dev);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to do POR reset: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < PHY_NUM; i++) {
|
||||
lvds_phy = devm_kzalloc(dev, sizeof(*lvds_phy), GFP_KERNEL);
|
||||
if (!lvds_phy) {
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
phy = devm_phy_create(dev, NULL, &mixel_lvds_phy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
ret = PTR_ERR(phy);
|
||||
dev_err(dev, "failed to create PHY for channel%d: %d\n",
|
||||
i, ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
lvds_phy->phy = phy;
|
||||
lvds_phy->id = i;
|
||||
priv->phys[i] = lvds_phy;
|
||||
|
||||
phy_set_drvdata(phy, lvds_phy);
|
||||
}
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, mixel_lvds_phy_xlate);
|
||||
if (IS_ERR(phy_provider)) {
|
||||
ret = PTR_ERR(phy_provider);
|
||||
dev_err(dev, "failed to register PHY provider: %d\n", ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
err:
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mixel_lvds_phy_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused mixel_lvds_phy_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
/* power down */
|
||||
mutex_lock(&priv->lock);
|
||||
regmap_write(priv->regmap, PHY_CTRL + REG_SET, PD);
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused mixel_lvds_phy_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
/* power up + control initialization */
|
||||
mutex_lock(&priv->lock);
|
||||
regmap_update_bits(priv->regmap, PHY_CTRL,
|
||||
CTRL_INIT_MASK | PD, CTRL_INIT_VAL);
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops mixel_lvds_phy_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(mixel_lvds_phy_runtime_suspend,
|
||||
mixel_lvds_phy_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
static const struct of_device_id mixel_lvds_phy_of_match[] = {
|
||||
{ .compatible = "fsl,imx8qm-lvds-phy" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mixel_lvds_phy_of_match);
|
||||
|
||||
static struct platform_driver mixel_lvds_phy_driver = {
|
||||
.probe = mixel_lvds_phy_probe,
|
||||
.remove = mixel_lvds_phy_remove,
|
||||
.driver = {
|
||||
.pm = &mixel_lvds_phy_pm_ops,
|
||||
.name = "mixel-lvds-phy",
|
||||
.of_match_table = mixel_lvds_phy_of_match,
|
||||
}
|
||||
};
|
||||
module_platform_driver(mixel_lvds_phy_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Mixel LVDS PHY driver");
|
||||
MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
@@ -2,6 +2,17 @@
|
||||
#
|
||||
# Phy drivers for Mediatek devices
|
||||
#
|
||||
config PHY_MTK_PCIE
|
||||
tristate "MediaTek PCIe-PHY Driver"
|
||||
depends on ARCH_MEDIATEK || COMPILE_TEST
|
||||
depends on OF
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Say 'Y' here to add support for MediaTek PCIe PHY driver.
|
||||
This driver create the basic PHY instance and provides initialize
|
||||
callback for PCIe GEN3 port, it supports software efuse
|
||||
initialization.
|
||||
|
||||
config PHY_MTK_TPHY
|
||||
tristate "MediaTek T-PHY Driver"
|
||||
depends on ARCH_MEDIATEK || COMPILE_TEST
|
||||
@@ -55,3 +66,11 @@ config PHY_MTK_MIPI_DSI
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Support MIPI DSI for Mediatek SoCs.
|
||||
|
||||
config PHY_MTK_DP
|
||||
tristate "MediaTek DP-PHY Driver"
|
||||
depends on ARCH_MEDIATEK || COMPILE_TEST
|
||||
depends on OF
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Support DisplayPort PHY for MediaTek SoCs.
|
||||
|
||||
@@ -3,6 +3,8 @@
|
||||
# Makefile for the phy drivers.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_PHY_MTK_DP) += phy-mtk-dp.o
|
||||
obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
|
||||
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
|
||||
obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
|
||||
obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
|
||||
|
||||
@@ -0,0 +1,202 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* MediaTek DisplayPort PHY driver
|
||||
*
|
||||
* Copyright (c) 2022, BayLibre Inc.
|
||||
* Copyright (c) 2022, MediaTek Inc.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#define PHY_OFFSET 0x1000
|
||||
|
||||
#define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x14)
|
||||
#define TPLL_SSC_EN BIT(3)
|
||||
|
||||
#define MTK_DP_PHY_DIG_BIT_RATE (PHY_OFFSET + 0x3C)
|
||||
#define BIT_RATE_RBR 0
|
||||
#define BIT_RATE_HBR 1
|
||||
#define BIT_RATE_HBR2 2
|
||||
#define BIT_RATE_HBR3 3
|
||||
|
||||
#define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38)
|
||||
#define DP_GLB_SW_RST_PHYD BIT(0)
|
||||
|
||||
#define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138)
|
||||
#define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238)
|
||||
#define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338)
|
||||
#define MTK_DP_LANE3_DRIVING_PARAM_3 (PHY_OFFSET + 0x438)
|
||||
#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4)
|
||||
#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12))
|
||||
#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19)
|
||||
#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29)
|
||||
#define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
|
||||
XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
|
||||
XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
|
||||
XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
|
||||
|
||||
#define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT GENMASK(4, 3)
|
||||
#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT GENMASK(12, 9)
|
||||
#define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (BIT(18) | BIT(21))
|
||||
#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29)
|
||||
#define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
|
||||
XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \
|
||||
XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \
|
||||
XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT)
|
||||
|
||||
#define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT (BIT(3) | BIT(5))
|
||||
#define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT GENMASK(13, 12)
|
||||
#define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
|
||||
XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT)
|
||||
|
||||
#define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0
|
||||
#define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT GENMASK(10, 10)
|
||||
#define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT GENMASK(19, 19)
|
||||
#define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT GENMASK(28, 28)
|
||||
#define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
|
||||
XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \
|
||||
XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \
|
||||
XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT)
|
||||
|
||||
#define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0
|
||||
#define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT GENMASK(10, 9)
|
||||
#define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT GENMASK(19, 18)
|
||||
#define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT 0
|
||||
#define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
|
||||
XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \
|
||||
XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \
|
||||
XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT)
|
||||
|
||||
#define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT GENMASK(3, 3)
|
||||
#define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT 0
|
||||
#define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
|
||||
XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
|
||||
|
||||
struct mtk_dp_phy {
|
||||
struct regmap *regs;
|
||||
};
|
||||
|
||||
static int mtk_dp_phy_init(struct phy *phy)
|
||||
{
|
||||
struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
|
||||
u32 driving_params[] = {
|
||||
DRIVING_PARAM_3_DEFAULT,
|
||||
DRIVING_PARAM_4_DEFAULT,
|
||||
DRIVING_PARAM_5_DEFAULT,
|
||||
DRIVING_PARAM_6_DEFAULT,
|
||||
DRIVING_PARAM_7_DEFAULT,
|
||||
DRIVING_PARAM_8_DEFAULT
|
||||
};
|
||||
|
||||
regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3,
|
||||
driving_params, ARRAY_SIZE(driving_params));
|
||||
regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3,
|
||||
driving_params, ARRAY_SIZE(driving_params));
|
||||
regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3,
|
||||
driving_params, ARRAY_SIZE(driving_params));
|
||||
regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3,
|
||||
driving_params, ARRAY_SIZE(driving_params));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
|
||||
{
|
||||
struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
|
||||
u32 val;
|
||||
|
||||
if (opts->dp.set_rate) {
|
||||
switch (opts->dp.link_rate) {
|
||||
default:
|
||||
dev_err(&phy->dev,
|
||||
"Implementation error, unknown linkrate %x\n",
|
||||
opts->dp.link_rate);
|
||||
return -EINVAL;
|
||||
case 1620:
|
||||
val = BIT_RATE_RBR;
|
||||
break;
|
||||
case 2700:
|
||||
val = BIT_RATE_HBR;
|
||||
break;
|
||||
case 5400:
|
||||
val = BIT_RATE_HBR2;
|
||||
break;
|
||||
case 8100:
|
||||
val = BIT_RATE_HBR3;
|
||||
break;
|
||||
}
|
||||
regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val);
|
||||
}
|
||||
|
||||
regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1,
|
||||
TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_dp_phy_reset(struct phy *phy)
|
||||
{
|
||||
struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
|
||||
|
||||
regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST,
|
||||
DP_GLB_SW_RST_PHYD, 0);
|
||||
usleep_range(50, 200);
|
||||
regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST,
|
||||
DP_GLB_SW_RST_PHYD, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops mtk_dp_phy_dev_ops = {
|
||||
.init = mtk_dp_phy_init,
|
||||
.configure = mtk_dp_phy_configure,
|
||||
.reset = mtk_dp_phy_reset,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int mtk_dp_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mtk_dp_phy *dp_phy;
|
||||
struct phy *phy;
|
||||
struct regmap *regs;
|
||||
|
||||
regs = *(struct regmap **)dev->platform_data;
|
||||
if (!regs)
|
||||
return dev_err_probe(dev, EINVAL,
|
||||
"No data passed, requires struct regmap**\n");
|
||||
|
||||
dp_phy = devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL);
|
||||
if (!dp_phy)
|
||||
return -ENOMEM;
|
||||
|
||||
dp_phy->regs = regs;
|
||||
phy = devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops);
|
||||
if (IS_ERR(phy))
|
||||
return dev_err_probe(dev, PTR_ERR(phy),
|
||||
"Failed to create DP PHY\n");
|
||||
|
||||
phy_set_drvdata(phy, dp_phy);
|
||||
if (!dev->of_node)
|
||||
phy_create_lookup(phy, "dp", dev_name(dev));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver mtk_dp_phy_driver = {
|
||||
.probe = mtk_dp_phy_probe,
|
||||
.driver = {
|
||||
.name = "mediatek-dp-phy",
|
||||
},
|
||||
};
|
||||
module_platform_driver(mtk_dp_phy_driver);
|
||||
|
||||
MODULE_AUTHOR("Markus Schneider-Pargmann <msp@baylibre.com>");
|
||||
MODULE_DESCRIPTION("MediaTek DP PHY Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@@ -0,0 +1,267 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
* Author: Jianjun Wang <jianjun.wang@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/nvmem-consumer.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "phy-mtk-io.h"
|
||||
|
||||
#define PEXTP_ANA_GLB_00_REG 0x9000
|
||||
/* Internal Resistor Selection of TX Bias Current */
|
||||
#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
|
||||
|
||||
#define PEXTP_ANA_LN0_TRX_REG 0xa000
|
||||
|
||||
#define PEXTP_ANA_TX_REG 0x04
|
||||
/* TX PMOS impedance selection */
|
||||
#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
|
||||
/* TX NMOS impedance selection */
|
||||
#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
|
||||
|
||||
#define PEXTP_ANA_RX_REG 0x3c
|
||||
/* RX impedance selection */
|
||||
#define EFUSE_LN_RX_SEL GENMASK(3, 0)
|
||||
|
||||
#define PEXTP_ANA_LANE_OFFSET 0x100
|
||||
|
||||
/**
|
||||
* struct mtk_pcie_lane_efuse - eFuse data for each lane
|
||||
* @tx_pmos: TX PMOS impedance selection data
|
||||
* @tx_nmos: TX NMOS impedance selection data
|
||||
* @rx_data: RX impedance selection data
|
||||
* @lane_efuse_supported: software eFuse data is supported for this lane
|
||||
*/
|
||||
struct mtk_pcie_lane_efuse {
|
||||
u32 tx_pmos;
|
||||
u32 tx_nmos;
|
||||
u32 rx_data;
|
||||
bool lane_efuse_supported;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mtk_pcie_phy_data - phy data for each SoC
|
||||
* @num_lanes: supported lane numbers
|
||||
* @sw_efuse_supported: support software to load eFuse data
|
||||
*/
|
||||
struct mtk_pcie_phy_data {
|
||||
int num_lanes;
|
||||
bool sw_efuse_supported;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mtk_pcie_phy - PCIe phy driver main structure
|
||||
* @dev: pointer to device
|
||||
* @phy: pointer to generic phy
|
||||
* @sif_base: IO mapped register base address of system interface
|
||||
* @data: pointer to SoC dependent data
|
||||
* @sw_efuse_en: software eFuse enable status
|
||||
* @efuse_glb_intr: internal resistor selection of TX bias current data
|
||||
* @efuse: pointer to eFuse data for each lane
|
||||
*/
|
||||
struct mtk_pcie_phy {
|
||||
struct device *dev;
|
||||
struct phy *phy;
|
||||
void __iomem *sif_base;
|
||||
const struct mtk_pcie_phy_data *data;
|
||||
|
||||
bool sw_efuse_en;
|
||||
u32 efuse_glb_intr;
|
||||
struct mtk_pcie_lane_efuse *efuse;
|
||||
};
|
||||
|
||||
static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
|
||||
unsigned int lane)
|
||||
{
|
||||
struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
|
||||
void __iomem *addr;
|
||||
|
||||
if (!data->lane_efuse_supported)
|
||||
return;
|
||||
|
||||
addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
|
||||
lane * PEXTP_ANA_LANE_OFFSET;
|
||||
|
||||
mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL,
|
||||
FIELD_PREP(EFUSE_LN_TX_PMOS_SEL, data->tx_pmos));
|
||||
|
||||
mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL,
|
||||
FIELD_PREP(EFUSE_LN_TX_NMOS_SEL, data->tx_nmos));
|
||||
|
||||
mtk_phy_update_bits(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL,
|
||||
FIELD_PREP(EFUSE_LN_RX_SEL, data->rx_data));
|
||||
}
|
||||
|
||||
/**
|
||||
* mtk_pcie_phy_init() - Initialize the phy
|
||||
* @phy: the phy to be initialized
|
||||
*
|
||||
* Initialize the phy by setting the efuse data.
|
||||
* The hardware settings will be reset during suspend, it should be
|
||||
* reinitialized when the consumer calls phy_init() again on resume.
|
||||
*/
|
||||
static int mtk_pcie_phy_init(struct phy *phy)
|
||||
{
|
||||
struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
|
||||
int i;
|
||||
|
||||
if (!pcie_phy->sw_efuse_en)
|
||||
return 0;
|
||||
|
||||
/* Set global data */
|
||||
mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
|
||||
EFUSE_GLB_INTR_SEL,
|
||||
FIELD_PREP(EFUSE_GLB_INTR_SEL, pcie_phy->efuse_glb_intr));
|
||||
|
||||
for (i = 0; i < pcie_phy->data->num_lanes; i++)
|
||||
mtk_pcie_efuse_set_lane(pcie_phy, i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops mtk_pcie_phy_ops = {
|
||||
.init = mtk_pcie_phy_init,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy,
|
||||
unsigned int lane)
|
||||
{
|
||||
struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
|
||||
struct device *dev = pcie_phy->dev;
|
||||
char efuse_id[16];
|
||||
int ret;
|
||||
|
||||
snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
|
||||
ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
|
||||
|
||||
snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
|
||||
ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
|
||||
|
||||
snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
|
||||
ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
|
||||
|
||||
if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
|
||||
return dev_err_probe(dev, -EINVAL,
|
||||
"No eFuse data found for lane%d, but dts enable it\n",
|
||||
lane);
|
||||
|
||||
efuse->lane_efuse_supported = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
|
||||
{
|
||||
struct device *dev = pcie_phy->dev;
|
||||
bool nvmem_enabled;
|
||||
int ret, i;
|
||||
|
||||
/* nvmem data is optional */
|
||||
nvmem_enabled = device_property_present(dev, "nvmem-cells");
|
||||
if (!nvmem_enabled)
|
||||
return 0;
|
||||
|
||||
ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
|
||||
&pcie_phy->efuse_glb_intr);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to read glb_intr\n");
|
||||
|
||||
pcie_phy->sw_efuse_en = true;
|
||||
|
||||
pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
|
||||
sizeof(*pcie_phy->efuse), GFP_KERNEL);
|
||||
if (!pcie_phy->efuse)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < pcie_phy->data->num_lanes; i++) {
|
||||
ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_pcie_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct phy_provider *provider;
|
||||
struct mtk_pcie_phy *pcie_phy;
|
||||
int ret;
|
||||
|
||||
pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
|
||||
if (!pcie_phy)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif");
|
||||
if (IS_ERR(pcie_phy->sif_base))
|
||||
return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
|
||||
"Failed to map phy-sif base\n");
|
||||
|
||||
pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops);
|
||||
if (IS_ERR(pcie_phy->phy))
|
||||
return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
|
||||
"Failed to create PCIe phy\n");
|
||||
|
||||
pcie_phy->dev = dev;
|
||||
pcie_phy->data = of_device_get_match_data(dev);
|
||||
if (!pcie_phy->data)
|
||||
return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n");
|
||||
|
||||
if (pcie_phy->data->sw_efuse_supported) {
|
||||
/*
|
||||
* Failed to read the efuse data is not a fatal problem,
|
||||
* ignore the failure and keep going.
|
||||
*/
|
||||
ret = mtk_pcie_read_efuse(pcie_phy);
|
||||
if (ret == -EPROBE_DEFER || ret == -ENOMEM)
|
||||
return ret;
|
||||
}
|
||||
|
||||
phy_set_drvdata(pcie_phy->phy, pcie_phy);
|
||||
|
||||
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
if (IS_ERR(provider))
|
||||
return dev_err_probe(dev, PTR_ERR(provider),
|
||||
"PCIe phy probe failed\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mtk_pcie_phy_data mt8195_data = {
|
||||
.num_lanes = 2,
|
||||
.sw_efuse_supported = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id mtk_pcie_phy_of_match[] = {
|
||||
{ .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
|
||||
|
||||
static struct platform_driver mtk_pcie_phy_driver = {
|
||||
.probe = mtk_pcie_phy_probe,
|
||||
.driver = {
|
||||
.name = "mtk-pcie-phy",
|
||||
.of_match_table = mtk_pcie_phy_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(mtk_pcie_phy_driver);
|
||||
|
||||
MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
|
||||
MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
@@ -5,7 +5,13 @@ obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
|
||||
obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
|
||||
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
|
||||
obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
|
||||
obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
|
||||
obj-$(CONFIG_PHY_QCOM_QMP) += \
|
||||
phy-qcom-qmp-combo.o \
|
||||
phy-qcom-qmp-pcie.o \
|
||||
phy-qcom-qmp-pcie-msm8996.o \
|
||||
phy-qcom-qmp-ufs.o \
|
||||
phy-qcom-qmp-usb.o
|
||||
|
||||
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
|
||||
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
|
||||
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
|
||||
|
||||
@@ -639,6 +639,18 @@ static int qcom_edp_phy_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to set load at %s\n", edp->supplies[0].supply);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to set load at %s\n", edp->supplies[1].supply);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = qcom_edp_clks_register(edp, pdev->dev.of_node);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,123 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCIE_QHP_H_
|
||||
#define QCOM_PHY_QMP_PCIE_QHP_H_
|
||||
|
||||
/* PCIE GEN3 COM registers */
|
||||
#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
|
||||
#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
|
||||
#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
|
||||
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
|
||||
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
|
||||
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
|
||||
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
|
||||
#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
|
||||
#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
|
||||
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
|
||||
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
|
||||
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
|
||||
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
|
||||
#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
|
||||
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
|
||||
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
|
||||
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
|
||||
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
|
||||
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
|
||||
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
|
||||
#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
|
||||
#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
|
||||
#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
|
||||
#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
|
||||
#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
|
||||
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
|
||||
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
|
||||
#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
|
||||
#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
|
||||
#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
|
||||
#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
|
||||
#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
|
||||
#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
|
||||
#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
|
||||
#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
|
||||
#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
|
||||
#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
|
||||
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
|
||||
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
|
||||
|
||||
/* PCIE GEN3 QHP Lane registers */
|
||||
#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
|
||||
#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
|
||||
#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
|
||||
#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
|
||||
#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
|
||||
#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
|
||||
#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
|
||||
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
|
||||
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
|
||||
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
|
||||
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
|
||||
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
|
||||
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
|
||||
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
|
||||
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
|
||||
#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
|
||||
#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
|
||||
#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
|
||||
#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
|
||||
#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
|
||||
#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
|
||||
#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
|
||||
#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
|
||||
#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
|
||||
#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
|
||||
#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
|
||||
#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
|
||||
#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
|
||||
#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
|
||||
#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
|
||||
#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
|
||||
#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
|
||||
#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
|
||||
#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
|
||||
#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
|
||||
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
|
||||
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
|
||||
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
|
||||
#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
|
||||
#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
|
||||
#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
|
||||
#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
|
||||
#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
|
||||
#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
|
||||
#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
|
||||
#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
|
||||
#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
|
||||
#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
|
||||
#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
|
||||
|
||||
/* PCIE GEN3 PCS registers */
|
||||
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
|
||||
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
|
||||
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
|
||||
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
|
||||
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
|
||||
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
|
||||
#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_MISC_V3_H_
|
||||
#define QCOM_PHY_QMP_PCS_MISC_V3_H_
|
||||
|
||||
/* Only for QMP V3 PHY - PCS_MISC registers */
|
||||
#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
|
||||
#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
|
||||
#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
|
||||
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
|
||||
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
|
||||
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,72 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V4_H_
|
||||
|
||||
/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
|
||||
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0x00
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0x04
|
||||
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0x08
|
||||
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
|
||||
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0x10
|
||||
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14
|
||||
#define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0x18
|
||||
#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c
|
||||
#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x20
|
||||
#define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x24
|
||||
#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x28
|
||||
#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x2c
|
||||
#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x30
|
||||
#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x34
|
||||
#define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0x38
|
||||
#define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x3c
|
||||
#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40
|
||||
#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x44
|
||||
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
|
||||
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x4c
|
||||
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
|
||||
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x54
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0x58
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0x5c
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0x60
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0x64
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0x68
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0x6c
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0x70
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x74
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x78
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x7c
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x80
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x84
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x88
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x8c
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
|
||||
#define QPHY_V4_PCS_PCIE_LOCAL_FS 0x94
|
||||
#define QPHY_V4_PCS_PCIE_LOCAL_LF 0x98
|
||||
#define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0x9c
|
||||
#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
|
||||
#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0xa8
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0xac
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0xb0
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0xb8
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc0
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc4
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xc8
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0xcc
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0xd0
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0xd4
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0xd8
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0xdc
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe4
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0xe8
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0xec
|
||||
#define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0xf0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
|
||||
|
||||
#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
|
||||
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
|
||||
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
|
||||
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
|
||||
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
|
||||
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
|
||||
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,16 @@
|
||||
/* Only for QMP V5 PHY - PCS_PCIE registers */
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V5_H_
|
||||
|
||||
/* Only for QMP V5 PHY - PCS_PCIE registers */
|
||||
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
|
||||
#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
|
||||
#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
|
||||
#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
|
||||
|
||||
/* Only for QMP V5_20 PHY - PCIe PCS registers */
|
||||
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
|
||||
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
|
||||
#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
|
||||
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
|
||||
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
|
||||
#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_
|
||||
#define QCOM_PHY_QMP_PCS_UFS_V3_H_
|
||||
|
||||
#define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
|
||||
#define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
|
||||
#define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
|
||||
#define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
|
||||
#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
|
||||
#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
|
||||
#define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
|
||||
#define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_UFS_V4_H_
|
||||
#define QCOM_PHY_QMP_PCS_UFS_V4_H_
|
||||
|
||||
/* Only for QMP V4 PHY - UFS PCS registers */
|
||||
#define QPHY_V4_PCS_UFS_PHY_START 0x000
|
||||
#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
|
||||
#define QPHY_V4_PCS_UFS_SW_RESET 0x008
|
||||
#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
|
||||
#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
|
||||
#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
|
||||
#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
|
||||
#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
|
||||
#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
|
||||
#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
|
||||
#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
|
||||
#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
|
||||
#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
|
||||
#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
|
||||
#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
|
||||
#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
|
||||
#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
|
||||
#define QPHY_V4_PCS_UFS_READY_STATUS 0x180
|
||||
#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
|
||||
#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,27 @@
|
||||
/* Only for QMP V5 PHY - UFS PCS registers */
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_
|
||||
#define QCOM_PHY_QMP_PCS_UFS_V5_H_
|
||||
|
||||
/* Only for QMP V5 PHY - UFS PCS registers */
|
||||
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
|
||||
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
|
||||
#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
|
||||
#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
|
||||
#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
|
||||
#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
|
||||
#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
|
||||
#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
|
||||
#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
|
||||
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
|
||||
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
|
||||
#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
|
||||
#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
|
||||
#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
|
||||
#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,34 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_USB_V4_H_
|
||||
#define QCOM_PHY_QMP_PCS_USB_V4_H_
|
||||
|
||||
/* Only for QMP V4 PHY - USB3 PCS registers */
|
||||
#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
|
||||
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
|
||||
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
|
||||
#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
|
||||
#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
|
||||
#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
|
||||
#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
|
||||
#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
|
||||
#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
|
||||
#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
|
||||
#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028
|
||||
#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c
|
||||
#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030
|
||||
#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034
|
||||
#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038
|
||||
#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c
|
||||
#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040
|
||||
#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044
|
||||
#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048
|
||||
#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c
|
||||
#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050
|
||||
#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054
|
||||
#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,36 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_USB_V5_H_
|
||||
#define QCOM_PHY_QMP_PCS_USB_V5_H_
|
||||
|
||||
/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
|
||||
#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
|
||||
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
|
||||
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
|
||||
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
|
||||
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
|
||||
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
|
||||
#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
|
||||
#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
|
||||
#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
|
||||
#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
|
||||
#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
|
||||
#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
|
||||
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
|
||||
#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
|
||||
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
|
||||
#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
|
||||
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
|
||||
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
|
||||
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
|
||||
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
|
||||
#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
|
||||
#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
|
||||
#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
|
||||
#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
|
||||
#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,46 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_V2_H_
|
||||
#define QCOM_PHY_QMP_PCS_V2_H_
|
||||
|
||||
/* Only for QMP V2 PHY - PCS registers */
|
||||
#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
|
||||
#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
|
||||
#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
|
||||
#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
|
||||
#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038
|
||||
#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c
|
||||
#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040
|
||||
#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
|
||||
#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
|
||||
#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
|
||||
#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064
|
||||
#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c
|
||||
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080
|
||||
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084
|
||||
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088
|
||||
#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
|
||||
#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
|
||||
#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
|
||||
#define QPHY_V2_PCS_FLL_CNTRL1 0x0c0
|
||||
#define QPHY_V2_PCS_FLL_CNTRL2 0x0c4
|
||||
#define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8
|
||||
#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc
|
||||
#define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0
|
||||
|
||||
/* UFS only ? */
|
||||
#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
|
||||
#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
|
||||
#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
|
||||
#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
|
||||
#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
|
||||
#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
|
||||
#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
|
||||
#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
|
||||
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
|
||||
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,145 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_V3_H_
|
||||
#define QCOM_PHY_QMP_PCS_V3_H_
|
||||
|
||||
/* Only for QMP V3 PHY - PCS registers */
|
||||
#define QPHY_V3_PCS_SW_RESET 0x000
|
||||
#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
|
||||
#define QPHY_V3_PCS_START_CONTROL 0x008
|
||||
#define QPHY_V3_PCS_TXMGN_V0 0x00c
|
||||
#define QPHY_V3_PCS_TXMGN_V1 0x010
|
||||
#define QPHY_V3_PCS_TXMGN_V2 0x014
|
||||
#define QPHY_V3_PCS_TXMGN_V3 0x018
|
||||
#define QPHY_V3_PCS_TXMGN_V4 0x01c
|
||||
#define QPHY_V3_PCS_TXMGN_LS 0x020
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
|
||||
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
|
||||
#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
|
||||
#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
|
||||
#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
|
||||
#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
|
||||
#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
|
||||
#define QPHY_V3_PCS_POWER_STATE_CONFIG3 0x068
|
||||
#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
|
||||
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
|
||||
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
|
||||
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
|
||||
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
|
||||
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
|
||||
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
|
||||
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
|
||||
#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
|
||||
#define QPHY_V3_PCS_SIGDET_LOW_2_IDLE_TIME 0x090
|
||||
#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_L 0x094
|
||||
#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_H 0x098
|
||||
#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_SYSCLK 0x09c
|
||||
#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
|
||||
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
|
||||
#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
|
||||
#define QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL 0x0ac
|
||||
#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
|
||||
#define QPHY_V3_PCS_LFPS_TX_END_CNT_P2U3_START 0x0b4
|
||||
#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
|
||||
#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
|
||||
#define QPHY_V3_PCS_TXONESZEROS_RUN_LENGTH 0x0c0
|
||||
#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
|
||||
#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
|
||||
#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
|
||||
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
|
||||
#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
|
||||
#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL 0x0d8
|
||||
#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0dc
|
||||
#define QPHY_V3_PCS_ARCVR_DTCT_EN_PERIOD 0x0e0
|
||||
#define QPHY_V3_PCS_ARCVR_DTCT_CM_DLY 0x0e4
|
||||
#define QPHY_V3_PCS_ALFPS_DEGLITCH_VAL 0x0e8
|
||||
#define QPHY_V3_PCS_INSIG_SW_CTRL1 0x0ec
|
||||
#define QPHY_V3_PCS_INSIG_SW_CTRL2 0x0f0
|
||||
#define QPHY_V3_PCS_INSIG_SW_CTRL3 0x0f4
|
||||
#define QPHY_V3_PCS_INSIG_MX_CTRL1 0x0f8
|
||||
#define QPHY_V3_PCS_INSIG_MX_CTRL2 0x0fc
|
||||
#define QPHY_V3_PCS_INSIG_MX_CTRL3 0x100
|
||||
#define QPHY_V3_PCS_OUTSIG_SW_CTRL1 0x104
|
||||
#define QPHY_V3_PCS_OUTSIG_MX_CTRL1 0x108
|
||||
#define QPHY_V3_PCS_CLK_DEBUG_BYPASS_CTRL 0x10c
|
||||
#define QPHY_V3_PCS_TEST_CONTROL 0x110
|
||||
#define QPHY_V3_PCS_TEST_CONTROL2 0x114
|
||||
#define QPHY_V3_PCS_TEST_CONTROL3 0x118
|
||||
#define QPHY_V3_PCS_TEST_CONTROL4 0x11c
|
||||
#define QPHY_V3_PCS_TEST_CONTROL5 0x120
|
||||
#define QPHY_V3_PCS_TEST_CONTROL6 0x124
|
||||
#define QPHY_V3_PCS_TEST_CONTROL7 0x128
|
||||
#define QPHY_V3_PCS_COM_RESET_CONTROL 0x12c
|
||||
#define QPHY_V3_PCS_BIST_CTRL 0x130
|
||||
#define QPHY_V3_PCS_PRBS_POLY0 0x134
|
||||
#define QPHY_V3_PCS_PRBS_POLY1 0x138
|
||||
#define QPHY_V3_PCS_PRBS_SEED0 0x13c
|
||||
#define QPHY_V3_PCS_PRBS_SEED1 0x140
|
||||
#define QPHY_V3_PCS_FIXED_PAT_CTRL 0x144
|
||||
#define QPHY_V3_PCS_FIXED_PAT0 0x148
|
||||
#define QPHY_V3_PCS_FIXED_PAT1 0x14c
|
||||
#define QPHY_V3_PCS_FIXED_PAT2 0x150
|
||||
#define QPHY_V3_PCS_FIXED_PAT3 0x154
|
||||
#define QPHY_V3_PCS_COM_CLK_SWITCH_CTRL 0x158
|
||||
#define QPHY_V3_PCS_ELECIDLE_DLY_SEL 0x15c
|
||||
#define QPHY_V3_PCS_SPARE1 0x160
|
||||
#define QPHY_V3_PCS_BIST_CHK_ERR_CNT_L_STATUS 0x164
|
||||
#define QPHY_V3_PCS_BIST_CHK_ERR_CNT_H_STATUS 0x168
|
||||
#define QPHY_V3_PCS_BIST_CHK_STATUS 0x16c
|
||||
#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x170
|
||||
#define QPHY_V3_PCS_PCS_STATUS 0x174
|
||||
#define QPHY_V3_PCS_PCS_STATUS2 0x178
|
||||
#define QPHY_V3_PCS_PCS_STATUS3 0x17c
|
||||
#define QPHY_V3_PCS_COM_RESET_STATUS 0x180
|
||||
#define QPHY_V3_PCS_OSC_DTCT_STATUS 0x184
|
||||
#define QPHY_V3_PCS_REVISION_ID0 0x188
|
||||
#define QPHY_V3_PCS_REVISION_ID1 0x18c
|
||||
#define QPHY_V3_PCS_REVISION_ID2 0x190
|
||||
#define QPHY_V3_PCS_REVISION_ID3 0x194
|
||||
#define QPHY_V3_PCS_DEBUG_BUS_0_STATUS 0x198
|
||||
#define QPHY_V3_PCS_DEBUG_BUS_1_STATUS 0x19c
|
||||
#define QPHY_V3_PCS_DEBUG_BUS_2_STATUS 0x1a0
|
||||
#define QPHY_V3_PCS_DEBUG_BUS_3_STATUS 0x1a4
|
||||
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
|
||||
#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
|
||||
#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
|
||||
#define QPHY_V3_PCS_IDAC_CAL_CNTRL 0x1b4
|
||||
#define QPHY_V3_PCS_CMN_ACK_OUT_SEL 0x1b8
|
||||
#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME_SYSCLK 0x1bc
|
||||
#define QPHY_V3_PCS_AUTONOMOUS_MODE_STATUS 0x1c0
|
||||
#define QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL 0x1c4
|
||||
#define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_SYSCLK 0x1c8
|
||||
#define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x1cc
|
||||
#define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_L 0x1d0
|
||||
#define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_H 0x1d4
|
||||
#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
|
||||
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
|
||||
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
|
||||
#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL2 0x1e4
|
||||
#define QPHY_V3_PCS_RXTERMINATION_DLY_SEL 0x1e8
|
||||
#define QPHY_V3_PCS_LFPS_PER_TIMER_VAL 0x1ec
|
||||
#define QPHY_V3_PCS_SIGDET_STARTUP_TIMER_VAL 0x1f0
|
||||
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG4 0x1f4
|
||||
#define QPHY_V3_PCS_RX_SIGDET_DTCT_CNTRL 0x1f8
|
||||
#define QPHY_V3_PCS_PCS_STATUS4 0x1fc
|
||||
#define QPHY_V3_PCS_PCS_STATUS4_CLEAR 0x200
|
||||
#define QPHY_V3_PCS_DEC_ERROR_COUNT_STATUS 0x204
|
||||
#define QPHY_V3_PCS_COMMA_POS_STATUS 0x208
|
||||
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
|
||||
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
|
||||
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG3 0x214
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,135 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_V4_H_
|
||||
#define QCOM_PHY_QMP_PCS_V4_H_
|
||||
|
||||
/* Only for QMP V4 PHY - USB/PCIe PCS registers */
|
||||
#define QPHY_V4_PCS_SW_RESET 0x000
|
||||
#define QPHY_V4_PCS_REVISION_ID0 0x004
|
||||
#define QPHY_V4_PCS_REVISION_ID1 0x008
|
||||
#define QPHY_V4_PCS_REVISION_ID2 0x00c
|
||||
#define QPHY_V4_PCS_REVISION_ID3 0x010
|
||||
#define QPHY_V4_PCS_PCS_STATUS1 0x014
|
||||
#define QPHY_V4_PCS_PCS_STATUS2 0x018
|
||||
#define QPHY_V4_PCS_PCS_STATUS3 0x01c
|
||||
#define QPHY_V4_PCS_PCS_STATUS4 0x020
|
||||
#define QPHY_V4_PCS_PCS_STATUS5 0x024
|
||||
#define QPHY_V4_PCS_PCS_STATUS6 0x028
|
||||
#define QPHY_V4_PCS_PCS_STATUS7 0x02c
|
||||
#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030
|
||||
#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034
|
||||
#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038
|
||||
#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c
|
||||
#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040
|
||||
#define QPHY_V4_PCS_START_CONTROL 0x044
|
||||
#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048
|
||||
#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c
|
||||
#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050
|
||||
#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054
|
||||
#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058
|
||||
#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c
|
||||
#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060
|
||||
#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064
|
||||
#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068
|
||||
#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c
|
||||
#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070
|
||||
#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074
|
||||
#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078
|
||||
#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c
|
||||
#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080
|
||||
#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084
|
||||
#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088
|
||||
#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c
|
||||
#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090
|
||||
#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094
|
||||
#define QPHY_V4_PCS_FLL_CNTRL1 0x098
|
||||
#define QPHY_V4_PCS_FLL_CNTRL2 0x09c
|
||||
#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0
|
||||
#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4
|
||||
#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8
|
||||
#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac
|
||||
#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0
|
||||
#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4
|
||||
#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8
|
||||
#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc
|
||||
#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0
|
||||
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4
|
||||
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8
|
||||
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc
|
||||
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0
|
||||
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4
|
||||
#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8
|
||||
#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc
|
||||
#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0
|
||||
#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4
|
||||
#define QPHY_V4_PCS_BIST_CTRL 0x0e8
|
||||
#define QPHY_V4_PCS_PRBS_POLY0 0x0ec
|
||||
#define QPHY_V4_PCS_PRBS_POLY1 0x0f0
|
||||
#define QPHY_V4_PCS_FIXED_PAT0 0x0f4
|
||||
#define QPHY_V4_PCS_FIXED_PAT1 0x0f8
|
||||
#define QPHY_V4_PCS_FIXED_PAT2 0x0fc
|
||||
#define QPHY_V4_PCS_FIXED_PAT3 0x100
|
||||
#define QPHY_V4_PCS_FIXED_PAT4 0x104
|
||||
#define QPHY_V4_PCS_FIXED_PAT5 0x108
|
||||
#define QPHY_V4_PCS_FIXED_PAT6 0x10c
|
||||
#define QPHY_V4_PCS_FIXED_PAT7 0x110
|
||||
#define QPHY_V4_PCS_FIXED_PAT8 0x114
|
||||
#define QPHY_V4_PCS_FIXED_PAT9 0x118
|
||||
#define QPHY_V4_PCS_FIXED_PAT10 0x11c
|
||||
#define QPHY_V4_PCS_FIXED_PAT11 0x120
|
||||
#define QPHY_V4_PCS_FIXED_PAT12 0x124
|
||||
#define QPHY_V4_PCS_FIXED_PAT13 0x128
|
||||
#define QPHY_V4_PCS_FIXED_PAT14 0x12c
|
||||
#define QPHY_V4_PCS_FIXED_PAT15 0x130
|
||||
#define QPHY_V4_PCS_TXMGN_CONFIG 0x134
|
||||
#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138
|
||||
#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c
|
||||
#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140
|
||||
#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144
|
||||
#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148
|
||||
#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c
|
||||
#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150
|
||||
#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154
|
||||
#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158
|
||||
#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c
|
||||
#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160
|
||||
#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164
|
||||
#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168
|
||||
#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
|
||||
#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170
|
||||
#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174
|
||||
#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178
|
||||
#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c
|
||||
#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180
|
||||
#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
|
||||
#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188
|
||||
#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
|
||||
#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
|
||||
#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
|
||||
#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198
|
||||
#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c
|
||||
#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
|
||||
#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
|
||||
#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
|
||||
#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac
|
||||
#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0
|
||||
#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4
|
||||
#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8
|
||||
#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc
|
||||
#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
|
||||
#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
|
||||
#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8
|
||||
#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc
|
||||
#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0
|
||||
#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
|
||||
#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8
|
||||
#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc
|
||||
#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0
|
||||
#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
|
||||
#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
|
||||
#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_V4_20_H_
|
||||
#define QCOM_PHY_QMP_PCS_V4_20_H_
|
||||
|
||||
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
|
||||
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
|
||||
#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
|
||||
#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
|
||||
#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_V5_H_
|
||||
#define QCOM_PHY_QMP_PCS_V5_H_
|
||||
|
||||
/* Only for QMP V5 PHY - USB/PCIe PCS registers */
|
||||
#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
|
||||
#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
|
||||
#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
|
||||
#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
|
||||
#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
|
||||
#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,111 @@
|
||||
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_COM_V3_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_COM_V3_H_
|
||||
|
||||
/* Only for QMP V3 PHY - QSERDES COM registers */
|
||||
#define QSERDES_V3_COM_ATB_SEL1 0x000
|
||||
#define QSERDES_V3_COM_ATB_SEL2 0x004
|
||||
#define QSERDES_V3_COM_FREQ_UPDATE 0x008
|
||||
#define QSERDES_V3_COM_BG_TIMER 0x00c
|
||||
#define QSERDES_V3_COM_SSC_EN_CENTER 0x010
|
||||
#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
|
||||
#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
|
||||
#define QSERDES_V3_COM_SSC_PER1 0x01c
|
||||
#define QSERDES_V3_COM_SSC_PER2 0x020
|
||||
#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
|
||||
#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
|
||||
#define QSERDES_V3_COM_POST_DIV 0x02c
|
||||
#define QSERDES_V3_COM_POST_DIV_MUX 0x030
|
||||
#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
|
||||
#define QSERDES_V3_COM_CLK_ENABLE1 0x038
|
||||
#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
|
||||
#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
|
||||
#define QSERDES_V3_COM_PLL_EN 0x044
|
||||
#define QSERDES_V3_COM_PLL_IVCO 0x048
|
||||
#define QSERDES_V3_COM_CMN_IETRIM 0x04c
|
||||
#define QSERDES_V3_COM_CMN_IPTRIM 0x050
|
||||
#define QSERDES_V3_COM_EP_CLOCK_DETECT_CTR 0x054
|
||||
#define QSERDES_V3_COM_SYSCLK_DET_COMP_STATUS 0x058
|
||||
#define QSERDES_V3_COM_CLK_EP_DIV 0x05c
|
||||
#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
|
||||
#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
|
||||
#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068
|
||||
#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
|
||||
#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
|
||||
#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
|
||||
#define QSERDES_V3_COM_PLL_CNTRL 0x078
|
||||
#define QSERDES_V3_COM_BIAS_EN_CTRL_BY_PSM 0x07c
|
||||
#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
|
||||
#define QSERDES_V3_COM_CML_SYSCLK_SEL 0x084
|
||||
#define QSERDES_V3_COM_RESETSM_CNTRL 0x088
|
||||
#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
|
||||
#define QSERDES_V3_COM_LOCK_CMP_EN 0x090
|
||||
#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094
|
||||
#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
|
||||
#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
|
||||
#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0
|
||||
#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4
|
||||
#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8
|
||||
#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac
|
||||
#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0
|
||||
#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4
|
||||
#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8
|
||||
#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc
|
||||
#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0
|
||||
#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
|
||||
#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
|
||||
#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
|
||||
#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
|
||||
#define QSERDES_V3_COM_INTEGLOOP_EN 0x0d4
|
||||
#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
|
||||
#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
|
||||
#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
|
||||
#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
|
||||
#define QSERDES_V3_COM_VCOCAL_DEADMAN_CTRL 0x0e8
|
||||
#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
|
||||
#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
|
||||
#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
|
||||
#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
|
||||
#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
|
||||
#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
|
||||
#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
|
||||
#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
|
||||
#define QSERDES_V3_COM_VCO_TUNE_MINVAL1 0x10c
|
||||
#define QSERDES_V3_COM_VCO_TUNE_MINVAL2 0x110
|
||||
#define QSERDES_V3_COM_VCO_TUNE_MAXVAL1 0x114
|
||||
#define QSERDES_V3_COM_VCO_TUNE_MAXVAL2 0x118
|
||||
#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
|
||||
#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
|
||||
#define QSERDES_V3_COM_CMN_STATUS 0x124
|
||||
#define QSERDES_V3_COM_RESET_SM_STATUS 0x128
|
||||
#define QSERDES_V3_COM_RESTRIM_CODE_STATUS 0x12c
|
||||
#define QSERDES_V3_COM_PLLCAL_CODE1_STATUS 0x130
|
||||
#define QSERDES_V3_COM_PLLCAL_CODE2_STATUS 0x134
|
||||
#define QSERDES_V3_COM_CLK_SELECT 0x138
|
||||
#define QSERDES_V3_COM_HSCLK_SEL 0x13c
|
||||
#define QSERDES_V3_COM_INTEGLOOP_BINCODE_STATUS 0x140
|
||||
#define QSERDES_V3_COM_PLL_ANALOG 0x144
|
||||
#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
|
||||
#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
|
||||
#define QSERDES_V3_COM_SW_RESET 0x150
|
||||
#define QSERDES_V3_COM_CORE_CLK_EN 0x154
|
||||
#define QSERDES_V3_COM_C_READY_STATUS 0x158
|
||||
#define QSERDES_V3_COM_CMN_CONFIG 0x15c
|
||||
#define QSERDES_V3_COM_CMN_RATE_OVERRIDE 0x160
|
||||
#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
|
||||
#define QSERDES_V3_COM_DEBUG_BUS0 0x168
|
||||
#define QSERDES_V3_COM_DEBUG_BUS1 0x16c
|
||||
#define QSERDES_V3_COM_DEBUG_BUS2 0x170
|
||||
#define QSERDES_V3_COM_DEBUG_BUS3 0x174
|
||||
#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
|
||||
#define QSERDES_V3_COM_CMN_MISC1 0x17c
|
||||
#define QSERDES_V3_COM_CMN_MISC2 0x180
|
||||
#define QSERDES_V3_COM_CMN_MODE 0x184
|
||||
#define QSERDES_V3_COM_CMN_VREG_SEL 0x188
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,123 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_COM_V4_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_COM_V4_H_
|
||||
|
||||
/* Only for QMP V4 PHY - QSERDES COM registers */
|
||||
#define QSERDES_V4_COM_ATB_SEL1 0x000
|
||||
#define QSERDES_V4_COM_ATB_SEL2 0x004
|
||||
#define QSERDES_V4_COM_FREQ_UPDATE 0x008
|
||||
#define QSERDES_V4_COM_BG_TIMER 0x00c
|
||||
#define QSERDES_V4_COM_SSC_EN_CENTER 0x010
|
||||
#define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
|
||||
#define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
|
||||
#define QSERDES_V4_COM_SSC_PER1 0x01c
|
||||
#define QSERDES_V4_COM_SSC_PER2 0x020
|
||||
#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
|
||||
#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028
|
||||
#define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE0 0x02c
|
||||
#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030
|
||||
#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034
|
||||
#define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE1 0x038
|
||||
#define QSERDES_V4_COM_POST_DIV 0x03c
|
||||
#define QSERDES_V4_COM_POST_DIV_MUX 0x040
|
||||
#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044
|
||||
#define QSERDES_V4_COM_CLK_ENABLE1 0x048
|
||||
#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c
|
||||
#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050
|
||||
#define QSERDES_V4_COM_PLL_EN 0x054
|
||||
#define QSERDES_V4_COM_PLL_IVCO 0x058
|
||||
#define QSERDES_V4_COM_CMN_IETRIM 0x05c
|
||||
#define QSERDES_V4_COM_CMN_IPTRIM 0x060
|
||||
#define QSERDES_V4_COM_EP_CLOCK_DETECT_CTRL 0x064
|
||||
#define QSERDES_V4_COM_SYSCLK_DET_COMP_STATUS 0x068
|
||||
#define QSERDES_V4_COM_CLK_EP_DIV_MODE0 0x06c
|
||||
#define QSERDES_V4_COM_CLK_EP_DIV_MODE1 0x070
|
||||
#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
|
||||
#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
|
||||
#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
|
||||
#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
|
||||
#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
|
||||
#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
|
||||
#define QSERDES_V4_COM_PLL_CNTRL 0x08c
|
||||
#define QSERDES_V4_COM_BIAS_EN_CTRL_BY_PSM 0x090
|
||||
#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
|
||||
#define QSERDES_V4_COM_CML_SYSCLK_SEL 0x098
|
||||
#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c
|
||||
#define QSERDES_V4_COM_RESETSM_CNTRL2 0x0a0
|
||||
#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
|
||||
#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8
|
||||
#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
|
||||
#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0
|
||||
#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
|
||||
#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
|
||||
#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
|
||||
#define QSERDES_V4_COM_DEC_START_MSB_MODE0 0x0c0
|
||||
#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
|
||||
#define QSERDES_V4_COM_DEC_START_MSB_MODE1 0x0c8
|
||||
#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc
|
||||
#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0
|
||||
#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4
|
||||
#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8
|
||||
#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc
|
||||
#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0
|
||||
#define QSERDES_V4_COM_INTEGLOOP_INITVAL 0x0e4
|
||||
#define QSERDES_V4_COM_INTEGLOOP_EN 0x0e8
|
||||
#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
|
||||
#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
|
||||
#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
|
||||
#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
|
||||
#define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc
|
||||
#define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN1 0x100
|
||||
#define QSERDES_V4_COM_VCOCAL_DEADMAN_CTRL 0x104
|
||||
#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108
|
||||
#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
|
||||
#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110
|
||||
#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114
|
||||
#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118
|
||||
#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c
|
||||
#define QSERDES_V4_COM_VCO_TUNE_INITVAL1 0x120
|
||||
#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
|
||||
#define QSERDES_V4_COM_VCO_TUNE_MINVAL1 0x128
|
||||
#define QSERDES_V4_COM_VCO_TUNE_MINVAL2 0x12c
|
||||
#define QSERDES_V4_COM_VCO_TUNE_MAXVAL1 0x130
|
||||
#define QSERDES_V4_COM_VCO_TUNE_MAXVAL2 0x134
|
||||
#define QSERDES_V4_COM_VCO_TUNE_TIMER1 0x138
|
||||
#define QSERDES_V4_COM_VCO_TUNE_TIMER2 0x13c
|
||||
#define QSERDES_V4_COM_CMN_STATUS 0x140
|
||||
#define QSERDES_V4_COM_RESET_SM_STATUS 0x144
|
||||
#define QSERDES_V4_COM_RESTRIM_CODE_STATUS 0x148
|
||||
#define QSERDES_V4_COM_PLLCAL_CODE1_STATUS 0x14c
|
||||
#define QSERDES_V4_COM_PLLCAL_CODE2_STATUS 0x150
|
||||
#define QSERDES_V4_COM_CLK_SELECT 0x154
|
||||
#define QSERDES_V4_COM_HSCLK_SEL 0x158
|
||||
#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
|
||||
#define QSERDES_V4_COM_INTEGLOOP_BINCODE_STATUS 0x160
|
||||
#define QSERDES_V4_COM_PLL_ANALOG 0x164
|
||||
#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168
|
||||
#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c
|
||||
#define QSERDES_V4_COM_SW_RESET 0x170
|
||||
#define QSERDES_V4_COM_CORE_CLK_EN 0x174
|
||||
#define QSERDES_V4_COM_C_READY_STATUS 0x178
|
||||
#define QSERDES_V4_COM_CMN_CONFIG 0x17c
|
||||
#define QSERDES_V4_COM_CMN_RATE_OVERRIDE 0x180
|
||||
#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184
|
||||
#define QSERDES_V4_COM_DEBUG_BUS0 0x188
|
||||
#define QSERDES_V4_COM_DEBUG_BUS1 0x18c
|
||||
#define QSERDES_V4_COM_DEBUG_BUS2 0x190
|
||||
#define QSERDES_V4_COM_DEBUG_BUS3 0x194
|
||||
#define QSERDES_V4_COM_DEBUG_BUS_SEL 0x198
|
||||
#define QSERDES_V4_COM_CMN_MISC1 0x19c
|
||||
#define QSERDES_V4_COM_CMN_MISC2 0x1a0
|
||||
#define QSERDES_V4_COM_CMN_MODE 0x1a4
|
||||
#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8
|
||||
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
|
||||
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
|
||||
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
|
||||
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
|
||||
#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,124 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_COM_V5_H_
|
||||
|
||||
/* Only for QMP V5 PHY - QSERDES COM registers */
|
||||
#define QSERDES_V5_COM_ATB_SEL1 0x000
|
||||
#define QSERDES_V5_COM_ATB_SEL2 0x004
|
||||
#define QSERDES_V5_COM_FREQ_UPDATE 0x008
|
||||
#define QSERDES_V5_COM_BG_TIMER 0x00c
|
||||
#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
|
||||
#define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
|
||||
#define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
|
||||
#define QSERDES_V5_COM_SSC_PER1 0x01c
|
||||
#define QSERDES_V5_COM_SSC_PER2 0x020
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE0 0x02c
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE1 0x038
|
||||
#define QSERDES_V5_COM_POST_DIV 0x03c
|
||||
#define QSERDES_V5_COM_POST_DIV_MUX 0x040
|
||||
#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044
|
||||
#define QSERDES_V5_COM_CLK_ENABLE1 0x048
|
||||
#define QSERDES_V5_COM_SYS_CLK_CTRL 0x04c
|
||||
#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
|
||||
#define QSERDES_V5_COM_PLL_EN 0x054
|
||||
#define QSERDES_V5_COM_PLL_IVCO 0x058
|
||||
#define QSERDES_V5_COM_CMN_IETRIM 0x05c
|
||||
#define QSERDES_V5_COM_CMN_IPTRIM 0x060
|
||||
#define QSERDES_V5_COM_EP_CLOCK_DETECT_CTRL 0x064
|
||||
#define QSERDES_V5_COM_SYSCLK_DET_COMP_STATUS 0x068
|
||||
#define QSERDES_V5_COM_CLK_EP_DIV_MODE0 0x06c
|
||||
#define QSERDES_V5_COM_CLK_EP_DIV_MODE1 0x070
|
||||
#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
|
||||
#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
|
||||
#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c
|
||||
#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080
|
||||
#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084
|
||||
#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088
|
||||
#define QSERDES_V5_COM_PLL_CNTRL 0x08c
|
||||
#define QSERDES_V5_COM_BIAS_EN_CTRL_BY_PSM 0x090
|
||||
#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094
|
||||
#define QSERDES_V5_COM_CML_SYSCLK_SEL 0x098
|
||||
#define QSERDES_V5_COM_RESETSM_CNTRL 0x09c
|
||||
#define QSERDES_V5_COM_RESETSM_CNTRL2 0x0a0
|
||||
#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4
|
||||
#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8
|
||||
#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
|
||||
#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0
|
||||
#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
|
||||
#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
|
||||
#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
|
||||
#define QSERDES_V5_COM_DEC_START_MSB_MODE0 0x0c0
|
||||
#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
|
||||
#define QSERDES_V5_COM_DEC_START_MSB_MODE1 0x0c8
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
|
||||
#define QSERDES_V5_COM_INTEGLOOP_INITVAL 0x0e4
|
||||
#define QSERDES_V5_COM_INTEGLOOP_EN 0x0e8
|
||||
#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
|
||||
#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
|
||||
#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
|
||||
#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
|
||||
#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc
|
||||
#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN1 0x100
|
||||
#define QSERDES_V5_COM_VCOCAL_DEADMAN_CTRL 0x104
|
||||
#define QSERDES_V5_COM_VCO_TUNE_CTRL 0x108
|
||||
#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
|
||||
#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
|
||||
#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
|
||||
#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
|
||||
#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
|
||||
#define QSERDES_V5_COM_VCO_TUNE_INITVAL1 0x120
|
||||
#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
|
||||
#define QSERDES_V5_COM_VCO_TUNE_MINVAL1 0x128
|
||||
#define QSERDES_V5_COM_VCO_TUNE_MINVAL2 0x12c
|
||||
#define QSERDES_V5_COM_VCO_TUNE_MAXVAL1 0x130
|
||||
#define QSERDES_V5_COM_VCO_TUNE_MAXVAL2 0x134
|
||||
#define QSERDES_V5_COM_VCO_TUNE_TIMER1 0x138
|
||||
#define QSERDES_V5_COM_VCO_TUNE_TIMER2 0x13c
|
||||
#define QSERDES_V5_COM_CMN_STATUS 0x140
|
||||
#define QSERDES_V5_COM_RESET_SM_STATUS 0x144
|
||||
#define QSERDES_V5_COM_RESTRIM_CODE_STATUS 0x148
|
||||
#define QSERDES_V5_COM_PLLCAL_CODE1_STATUS 0x14c
|
||||
#define QSERDES_V5_COM_PLLCAL_CODE2_STATUS 0x150
|
||||
#define QSERDES_V5_COM_CLK_SELECT 0x154
|
||||
#define QSERDES_V5_COM_HSCLK_SEL 0x158
|
||||
#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
|
||||
#define QSERDES_V5_COM_INTEGLOOP_BINCODE_STATUS 0x160
|
||||
#define QSERDES_V5_COM_PLL_ANALOG 0x164
|
||||
#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168
|
||||
#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
|
||||
#define QSERDES_V5_COM_SW_RESET 0x170
|
||||
#define QSERDES_V5_COM_CORE_CLK_EN 0x174
|
||||
#define QSERDES_V5_COM_C_READY_STATUS 0x178
|
||||
#define QSERDES_V5_COM_CMN_CONFIG 0x17c
|
||||
#define QSERDES_V5_COM_CMN_RATE_OVERRIDE 0x180
|
||||
#define QSERDES_V5_COM_SVS_MODE_CLK_SEL 0x184
|
||||
#define QSERDES_V5_COM_DEBUG_BUS0 0x188
|
||||
#define QSERDES_V5_COM_DEBUG_BUS1 0x18c
|
||||
#define QSERDES_V5_COM_DEBUG_BUS2 0x190
|
||||
#define QSERDES_V5_COM_DEBUG_BUS3 0x194
|
||||
#define QSERDES_V5_COM_DEBUG_BUS_SEL 0x198
|
||||
#define QSERDES_V5_COM_CMN_MISC1 0x19c
|
||||
#define QSERDES_V5_COM_CMN_MODE 0x1a0
|
||||
#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
|
||||
#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8
|
||||
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
|
||||
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
|
||||
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
|
||||
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
|
||||
#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
|
||||
#define QSERDES_V5_COM_RESERVED_1 0x1c0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,140 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_COM_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_COM_H_
|
||||
|
||||
/* Only for QMP V2 PHY - QSERDES COM registers */
|
||||
#define QSERDES_COM_ATB_SEL1 0x000
|
||||
#define QSERDES_COM_ATB_SEL2 0x004
|
||||
#define QSERDES_COM_FREQ_UPDATE 0x008
|
||||
#define QSERDES_COM_BG_TIMER 0x00c
|
||||
#define QSERDES_COM_SSC_EN_CENTER 0x010
|
||||
#define QSERDES_COM_SSC_ADJ_PER1 0x014
|
||||
#define QSERDES_COM_SSC_ADJ_PER2 0x018
|
||||
#define QSERDES_COM_SSC_PER1 0x01c
|
||||
#define QSERDES_COM_SSC_PER2 0x020
|
||||
#define QSERDES_COM_SSC_STEP_SIZE1 0x024
|
||||
#define QSERDES_COM_SSC_STEP_SIZE2 0x028
|
||||
#define QSERDES_COM_POST_DIV 0x02c
|
||||
#define QSERDES_COM_POST_DIV_MUX 0x030
|
||||
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
|
||||
#define QSERDES_COM_CLK_ENABLE1 0x038
|
||||
#define QSERDES_COM_SYS_CLK_CTRL 0x03c
|
||||
#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
|
||||
#define QSERDES_COM_PLL_EN 0x044
|
||||
#define QSERDES_COM_PLL_IVCO 0x048
|
||||
#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
|
||||
#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
|
||||
#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
|
||||
#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
|
||||
#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
|
||||
#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
|
||||
#define QSERDES_COM_LOCK_CMP1_MODE2 0x064
|
||||
#define QSERDES_COM_CMN_RSVD0 0x064
|
||||
#define QSERDES_COM_LOCK_CMP2_MODE2 0x068
|
||||
#define QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x068
|
||||
#define QSERDES_COM_LOCK_CMP3_MODE2 0x06c
|
||||
#define QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x06c
|
||||
#define QSERDES_COM_BG_TRIM 0x070
|
||||
#define QSERDES_COM_CLK_EP_DIV 0x074
|
||||
#define QSERDES_COM_CP_CTRL_MODE0 0x078
|
||||
#define QSERDES_COM_CP_CTRL_MODE1 0x07c
|
||||
#define QSERDES_COM_CP_CTRL_MODE2 0x080
|
||||
#define QSERDES_COM_CMN_RSVD1 0x080
|
||||
#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
|
||||
#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
|
||||
#define QSERDES_COM_PLL_RCTRL_MODE2 0x08c
|
||||
#define QSERDES_COM_CMN_RSVD2 0x08c
|
||||
#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
|
||||
#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
|
||||
#define QSERDES_COM_PLL_CCTRL_MODE2 0x098
|
||||
#define QSERDES_COM_CMN_RSVD3 0x098
|
||||
#define QSERDES_COM_PLL_CNTRL 0x09c
|
||||
#define QSERDES_COM_PHASE_SEL_CTRL 0x0a0
|
||||
#define QSERDES_COM_PHASE_SEL_DC 0x0a4
|
||||
#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x0a8
|
||||
#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
|
||||
#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
|
||||
#define QSERDES_COM_CML_SYSCLK_SEL 0x0b0
|
||||
#define QSERDES_COM_RESETSM_CNTRL 0x0b4
|
||||
#define QSERDES_COM_RESETSM_CNTRL2 0x0b8
|
||||
#define QSERDES_COM_RESTRIM_CTRL 0x0bc
|
||||
#define QSERDES_COM_RESTRIM_CTRL2 0x0c0
|
||||
#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
|
||||
#define QSERDES_COM_LOCK_CMP_EN 0x0c8
|
||||
#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
|
||||
#define QSERDES_COM_DEC_START_MODE0 0x0d0
|
||||
#define QSERDES_COM_DEC_START_MODE1 0x0d4
|
||||
#define QSERDES_COM_DEC_START_MODE2 0x0d8
|
||||
#define QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x0d8
|
||||
#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
|
||||
#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
|
||||
#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
|
||||
#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
|
||||
#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
|
||||
#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
|
||||
#define QSERDES_COM_DIV_FRAC_START1_MODE2 0x0f4
|
||||
#define QSERDES_COM_VCO_TUNE_MINVAL1 0x0f4
|
||||
#define QSERDES_COM_DIV_FRAC_START2_MODE2 0x0f8
|
||||
#define QSERDES_COM_VCO_TUNE_MINVAL2 0x0f8
|
||||
#define QSERDES_COM_DIV_FRAC_START3_MODE2 0x0fc
|
||||
#define QSERDES_COM_CMN_RSVD4 0x0fc
|
||||
#define QSERDES_COM_INTEGLOOP_INITVAL 0x100
|
||||
#define QSERDES_COM_INTEGLOOP_EN 0x104
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x118
|
||||
#define QSERDES_COM_VCO_TUNE_MAXVAL1 0x118
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x11c
|
||||
#define QSERDES_COM_VCO_TUNE_MAXVAL2 0x11c
|
||||
#define QSERDES_COM_RES_TRIM_CONTROL2 0x120
|
||||
#define QSERDES_COM_VCO_TUNE_CTRL 0x124
|
||||
#define QSERDES_COM_VCO_TUNE_MAP 0x128
|
||||
#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
|
||||
#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
|
||||
#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
|
||||
#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
|
||||
#define QSERDES_COM_VCO_TUNE1_MODE2 0x13c
|
||||
#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c
|
||||
#define QSERDES_COM_VCO_TUNE2_MODE2 0x140
|
||||
#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140
|
||||
#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
|
||||
#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
|
||||
#define QSERDES_COM_SAR 0x14c
|
||||
#define QSERDES_COM_SAR_CLK 0x150
|
||||
#define QSERDES_COM_SAR_CODE_OUT_STATUS 0x154
|
||||
#define QSERDES_COM_SAR_CODE_READY_STATUS 0x158
|
||||
#define QSERDES_COM_CMN_STATUS 0x15c
|
||||
#define QSERDES_COM_RESET_SM_STATUS 0x160
|
||||
#define QSERDES_COM_RESTRIM_CODE_STATUS 0x164
|
||||
#define QSERDES_COM_PLLCAL_CODE1_STATUS 0x168
|
||||
#define QSERDES_COM_PLLCAL_CODE2_STATUS 0x16c
|
||||
#define QSERDES_COM_BG_CTRL 0x170
|
||||
#define QSERDES_COM_CLK_SELECT 0x174
|
||||
#define QSERDES_COM_HSCLK_SEL 0x178
|
||||
#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x17c
|
||||
#define QSERDES_COM_PLL_ANALOG 0x180
|
||||
#define QSERDES_COM_CORECLK_DIV 0x184
|
||||
#define QSERDES_COM_SW_RESET 0x188
|
||||
#define QSERDES_COM_CORE_CLK_EN 0x18c
|
||||
#define QSERDES_COM_C_READY_STATUS 0x190
|
||||
#define QSERDES_COM_CMN_CONFIG 0x194
|
||||
#define QSERDES_COM_CMN_RATE_OVERRIDE 0x198
|
||||
#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
|
||||
#define QSERDES_COM_DEBUG_BUS0 0x1a0
|
||||
#define QSERDES_COM_DEBUG_BUS1 0x1a4
|
||||
#define QSERDES_COM_DEBUG_BUS2 0x1a8
|
||||
#define QSERDES_COM_DEBUG_BUS3 0x1ac
|
||||
#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
|
||||
#define QSERDES_COM_CMN_MISC1 0x1b4
|
||||
#define QSERDES_COM_CMN_MISC2 0x1b8
|
||||
#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
|
||||
#define QSERDES_COM_CORECLK_DIV_MODE2 0x1c0
|
||||
#define QSERDES_COM_CMN_RSVD5 0x1c0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,66 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_PLL_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_PLL_H_
|
||||
|
||||
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
|
||||
#define QSERDES_PLL_BG_TIMER 0x00c
|
||||
#define QSERDES_PLL_SSC_PER1 0x01c
|
||||
#define QSERDES_PLL_SSC_PER2 0x020
|
||||
#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
|
||||
#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
|
||||
#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
|
||||
#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
|
||||
#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
|
||||
#define QSERDES_PLL_CLK_ENABLE1 0x040
|
||||
#define QSERDES_PLL_SYS_CLK_CTRL 0x044
|
||||
#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048
|
||||
#define QSERDES_PLL_PLL_IVCO 0x050
|
||||
#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054
|
||||
#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058
|
||||
#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060
|
||||
#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064
|
||||
#define QSERDES_PLL_BG_TRIM 0x074
|
||||
#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078
|
||||
#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c
|
||||
#define QSERDES_PLL_CP_CTRL_MODE0 0x080
|
||||
#define QSERDES_PLL_CP_CTRL_MODE1 0x084
|
||||
#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088
|
||||
#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c
|
||||
#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090
|
||||
#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094
|
||||
#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4
|
||||
#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8
|
||||
#define QSERDES_PLL_RESETSM_CNTRL 0x0b0
|
||||
#define QSERDES_PLL_LOCK_CMP_EN 0x0c4
|
||||
#define QSERDES_PLL_DEC_START_MODE0 0x0cc
|
||||
#define QSERDES_PLL_DEC_START_MODE1 0x0d0
|
||||
#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8
|
||||
#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc
|
||||
#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0
|
||||
#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4
|
||||
#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8
|
||||
#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec
|
||||
#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100
|
||||
#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104
|
||||
#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108
|
||||
#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c
|
||||
#define QSERDES_PLL_VCO_TUNE_MAP 0x120
|
||||
#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124
|
||||
#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128
|
||||
#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c
|
||||
#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130
|
||||
#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c
|
||||
#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140
|
||||
#define QSERDES_PLL_CLK_SELECT 0x16c
|
||||
#define QSERDES_PLL_HSCLK_SEL 0x170
|
||||
#define QSERDES_PLL_CORECLK_DIV 0x17c
|
||||
#define QSERDES_PLL_CORE_CLK_EN 0x184
|
||||
#define QSERDES_PLL_CMN_CONFIG 0x18c
|
||||
#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
|
||||
#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,68 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V3_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_TXRX_V3_H_
|
||||
|
||||
/* Only for QMP V3 PHY - TX registers */
|
||||
#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
|
||||
#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
|
||||
#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
|
||||
#define QSERDES_V3_TX_TX_DRV_LVL 0x01c
|
||||
#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
|
||||
#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
|
||||
#define QSERDES_V3_TX_TX_BAND 0x02c
|
||||
#define QSERDES_V3_TX_SLEW_CNTL 0x030
|
||||
#define QSERDES_V3_TX_INTERFACE_SELECT 0x034
|
||||
#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
|
||||
#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040
|
||||
#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
|
||||
#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048
|
||||
#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058
|
||||
#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c
|
||||
#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060
|
||||
#define QSERDES_V3_TX_TX_POL_INV 0x064
|
||||
#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068
|
||||
#define QSERDES_V3_TX_LANE_MODE_1 0x08c
|
||||
#define QSERDES_V3_TX_LANE_MODE_2 0x090
|
||||
#define QSERDES_V3_TX_LANE_MODE_3 0x094
|
||||
#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
|
||||
#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0
|
||||
#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4
|
||||
#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0
|
||||
|
||||
/* Only for QMP V3 PHY - RX registers */
|
||||
#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008
|
||||
#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
|
||||
#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
|
||||
#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
|
||||
#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
|
||||
#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c
|
||||
#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
|
||||
#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
|
||||
#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
|
||||
#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
|
||||
#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
|
||||
#define QSERDES_V3_RX_RX_TERM_BW 0x07c
|
||||
#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
|
||||
#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
|
||||
#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
|
||||
#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
|
||||
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d0
|
||||
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
|
||||
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
|
||||
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
|
||||
#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8
|
||||
#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc
|
||||
#define QSERDES_V3_RX_SIGDET_ENABLES 0x100
|
||||
#define QSERDES_V3_RX_SIGDET_CNTRL 0x104
|
||||
#define QSERDES_V3_RX_SIGDET_LVL 0x108
|
||||
#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
|
||||
#define QSERDES_V3_RX_RX_BAND 0x110
|
||||
#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
|
||||
#define QSERDES_V3_RX_RX_MODE_00 0x164
|
||||
#define QSERDES_V3_RX_RX_MODE_01 0x168
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,233 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_
|
||||
|
||||
/* Only for QMP V4 PHY - TX registers */
|
||||
#define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
|
||||
#define QSERDES_V4_TX_BIST_INVERT 0x004
|
||||
#define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
|
||||
#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
|
||||
#define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
|
||||
#define QSERDES_V4_TX_TX_DRV_LVL 0x014
|
||||
#define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
|
||||
#define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
|
||||
#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
|
||||
#define QSERDES_V4_TX_TX_BAND 0x024
|
||||
#define QSERDES_V4_TX_SLEW_CNTL 0x028
|
||||
#define QSERDES_V4_TX_INTERFACE_SELECT 0x02c
|
||||
#define QSERDES_V4_TX_LPB_EN 0x030
|
||||
#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x034
|
||||
#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x038
|
||||
#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x03c
|
||||
#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x040
|
||||
#define QSERDES_V4_TX_PERL_LENGTH1 0x044
|
||||
#define QSERDES_V4_TX_PERL_LENGTH2 0x048
|
||||
#define QSERDES_V4_TX_SERDES_BYP_EN_OUT 0x04c
|
||||
#define QSERDES_V4_TX_DEBUG_BUS_SEL 0x050
|
||||
#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x054
|
||||
#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x058
|
||||
#define QSERDES_V4_TX_TX_POL_INV 0x05c
|
||||
#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
|
||||
#define QSERDES_V4_TX_BIST_PATTERN1 0x064
|
||||
#define QSERDES_V4_TX_BIST_PATTERN2 0x068
|
||||
#define QSERDES_V4_TX_BIST_PATTERN3 0x06c
|
||||
#define QSERDES_V4_TX_BIST_PATTERN4 0x070
|
||||
#define QSERDES_V4_TX_BIST_PATTERN5 0x074
|
||||
#define QSERDES_V4_TX_BIST_PATTERN6 0x078
|
||||
#define QSERDES_V4_TX_BIST_PATTERN7 0x07c
|
||||
#define QSERDES_V4_TX_BIST_PATTERN8 0x080
|
||||
#define QSERDES_V4_TX_LANE_MODE_1 0x084
|
||||
#define QSERDES_V4_TX_LANE_MODE_2 0x088
|
||||
#define QSERDES_V4_TX_LANE_MODE_3 0x08c
|
||||
#define QSERDES_V4_TX_ATB_SEL1 0x090
|
||||
#define QSERDES_V4_TX_ATB_SEL2 0x094
|
||||
#define QSERDES_V4_TX_RCV_DETECT_LVL 0x098
|
||||
#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x09c
|
||||
#define QSERDES_V4_TX_PRBS_SEED1 0x0a0
|
||||
#define QSERDES_V4_TX_PRBS_SEED2 0x0a4
|
||||
#define QSERDES_V4_TX_PRBS_SEED3 0x0a8
|
||||
#define QSERDES_V4_TX_PRBS_SEED4 0x0ac
|
||||
#define QSERDES_V4_TX_RESET_GEN 0x0b0
|
||||
#define QSERDES_V4_TX_RESET_GEN_MUXES 0x0b4
|
||||
#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0x0b8
|
||||
#define QSERDES_V4_TX_TX_INTERFACE_MODE 0x0bc
|
||||
#define QSERDES_V4_TX_PWM_CTRL 0x0c0
|
||||
#define QSERDES_V4_TX_PWM_ENCODED_OR_DATA 0x0c4
|
||||
#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0c8
|
||||
#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0cc
|
||||
#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0d0
|
||||
#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0d4
|
||||
#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0d8
|
||||
#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0dc
|
||||
#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0e0
|
||||
#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0e4
|
||||
#define QSERDES_V4_TX_VMODE_CTRL1 0x0e8
|
||||
#define QSERDES_V4_TX_ALOG_OBSV_BUS_CTRL_1 0x0ec
|
||||
#define QSERDES_V4_TX_BIST_STATUS 0x0f0
|
||||
#define QSERDES_V4_TX_BIST_ERROR_COUNT1 0x0f4
|
||||
#define QSERDES_V4_TX_BIST_ERROR_COUNT2 0x0f8
|
||||
#define QSERDES_V4_TX_ALOG_OBSV_BUS_STATUS_1 0x0fc
|
||||
#define QSERDES_V4_TX_LANE_DIG_CONFIG 0x100
|
||||
#define QSERDES_V4_TX_PI_QEC_CTRL 0x104
|
||||
#define QSERDES_V4_TX_PRE_EMPH 0x108
|
||||
#define QSERDES_V4_TX_SW_RESET 0x10c
|
||||
#define QSERDES_V4_TX_DCC_OFFSET 0x110
|
||||
#define QSERDES_V4_TX_DIG_BKUP_CTRL 0x114
|
||||
#define QSERDES_V4_TX_DEBUG_BUS0 0x118
|
||||
#define QSERDES_V4_TX_DEBUG_BUS1 0x11c
|
||||
#define QSERDES_V4_TX_DEBUG_BUS2 0x120
|
||||
#define QSERDES_V4_TX_DEBUG_BUS3 0x124
|
||||
#define QSERDES_V4_TX_READ_EQCODE 0x128
|
||||
#define QSERDES_V4_TX_READ_OFFSETCODE 0x12c
|
||||
#define QSERDES_V4_TX_IA_ERROR_COUNTER_LOW 0x130
|
||||
#define QSERDES_V4_TX_IA_ERROR_COUNTER_HIGH 0x134
|
||||
#define QSERDES_V4_TX_VGA_READ_CODE 0x138
|
||||
#define QSERDES_V4_TX_VTH_READ_CODE 0x13c
|
||||
#define QSERDES_V4_TX_DFE_TAP1_READ_CODE 0x140
|
||||
#define QSERDES_V4_TX_DFE_TAP2_READ_CODE 0x144
|
||||
#define QSERDES_V4_TX_IDAC_STATUS_I 0x148
|
||||
#define QSERDES_V4_TX_IDAC_STATUS_IBAR 0x14c
|
||||
#define QSERDES_V4_TX_IDAC_STATUS_Q 0x150
|
||||
#define QSERDES_V4_TX_IDAC_STATUS_QBAR 0x154
|
||||
#define QSERDES_V4_TX_IDAC_STATUS_A 0x158
|
||||
#define QSERDES_V4_TX_IDAC_STATUS_ABAR 0x15c
|
||||
#define QSERDES_V4_TX_IDAC_STATUS_SM_ON 0x160
|
||||
#define QSERDES_V4_TX_IDAC_STATUS_CAL_DONE 0x164
|
||||
#define QSERDES_V4_TX_IDAC_STATUS_SIGNERROR 0x168
|
||||
#define QSERDES_V4_TX_DCC_CAL_STATUS 0x16c
|
||||
|
||||
/* Only for QMP V4 PHY - RX registers */
|
||||
#define QSERDES_V4_RX_UCDR_FO_GAIN_HALF 0x000
|
||||
#define QSERDES_V4_RX_UCDR_FO_GAIN_QUARTER 0x004
|
||||
#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
|
||||
#define QSERDES_V4_RX_UCDR_SO_GAIN_HALF 0x00c
|
||||
#define QSERDES_V4_RX_UCDR_SO_GAIN_QUARTER 0x010
|
||||
#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
|
||||
#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_HALF 0x018
|
||||
#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c
|
||||
#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN 0x020
|
||||
#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_HALF 0x024
|
||||
#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
|
||||
#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN 0x02c
|
||||
#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
|
||||
#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
|
||||
#define QSERDES_V4_RX_UCDR_FO_TO_SO_DELAY 0x038
|
||||
#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
|
||||
#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
|
||||
#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
|
||||
#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048
|
||||
#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c
|
||||
#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050
|
||||
#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054
|
||||
#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058
|
||||
#define QSERDES_V4_RX_AUX_CONTROL 0x05c
|
||||
#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060
|
||||
#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064
|
||||
#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
|
||||
#define QSERDES_V4_RX_AC_JTAG_INITP 0x06c
|
||||
#define QSERDES_V4_RX_AC_JTAG_INITN 0x070
|
||||
#define QSERDES_V4_RX_AC_JTAG_LVL 0x074
|
||||
#define QSERDES_V4_RX_AC_JTAG_MODE 0x078
|
||||
#define QSERDES_V4_RX_AC_JTAG_RESET 0x07c
|
||||
#define QSERDES_V4_RX_RX_TERM_BW 0x080
|
||||
#define QSERDES_V4_RX_RX_RCVR_IQ_EN 0x084
|
||||
#define QSERDES_V4_RX_RX_IDAC_I_DC_OFFSETS 0x088
|
||||
#define QSERDES_V4_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c
|
||||
#define QSERDES_V4_RX_RX_IDAC_Q_DC_OFFSETS 0x090
|
||||
#define QSERDES_V4_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094
|
||||
#define QSERDES_V4_RX_RX_IDAC_A_DC_OFFSETS 0x098
|
||||
#define QSERDES_V4_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c
|
||||
#define QSERDES_V4_RX_RX_IDAC_EN 0x0a0
|
||||
#define QSERDES_V4_RX_RX_IDAC_ENABLES 0x0a4
|
||||
#define QSERDES_V4_RX_RX_IDAC_SIGN 0x0a8
|
||||
#define QSERDES_V4_RX_RX_HIGHZ_HIGHRATE 0x0ac
|
||||
#define QSERDES_V4_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0
|
||||
#define QSERDES_V4_RX_DFE_1 0x0b4
|
||||
#define QSERDES_V4_RX_DFE_2 0x0b8
|
||||
#define QSERDES_V4_RX_DFE_3 0x0bc
|
||||
#define QSERDES_V4_RX_DFE_4 0x0c0
|
||||
#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1 0x0c4
|
||||
#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2 0x0c8
|
||||
#define QSERDES_V4_RX_TX_ADAPT_POST_THRESH 0x0cc
|
||||
#define QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH 0x0d0
|
||||
#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4
|
||||
#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8
|
||||
#define QSERDES_V4_RX_GM_CAL 0x0dc
|
||||
#define QSERDES_V4_RX_RX_VGA_GAIN2_LSB 0x0e0
|
||||
#define QSERDES_V4_RX_RX_VGA_GAIN2_MSB 0x0e4
|
||||
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
|
||||
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
|
||||
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
|
||||
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
|
||||
#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
|
||||
#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
|
||||
#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
|
||||
#define QSERDES_V4_RX_RX_IDAC_ACCUMULATOR 0x104
|
||||
#define QSERDES_V4_RX_RX_EQ_OFFSET_LSB 0x108
|
||||
#define QSERDES_V4_RX_RX_EQ_OFFSET_MSB 0x10c
|
||||
#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
|
||||
#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
|
||||
#define QSERDES_V4_RX_SIGDET_ENABLES 0x118
|
||||
#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c
|
||||
#define QSERDES_V4_RX_SIGDET_LVL 0x120
|
||||
#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
|
||||
#define QSERDES_V4_RX_RX_BAND 0x128
|
||||
#define QSERDES_V4_RX_CDR_FREEZE_UP_DN 0x12c
|
||||
#define QSERDES_V4_RX_CDR_RESET_OVERRIDE 0x130
|
||||
#define QSERDES_V4_RX_RX_INTERFACE_MODE 0x134
|
||||
#define QSERDES_V4_RX_JITTER_GEN_MODE 0x138
|
||||
#define QSERDES_V4_RX_SJ_AMP1 0x13c
|
||||
#define QSERDES_V4_RX_SJ_AMP2 0x140
|
||||
#define QSERDES_V4_RX_SJ_PER1 0x144
|
||||
#define QSERDES_V4_RX_SJ_PER2 0x148
|
||||
#define QSERDES_V4_RX_PPM_OFFSET1 0x14c
|
||||
#define QSERDES_V4_RX_PPM_OFFSET2 0x150
|
||||
#define QSERDES_V4_RX_SIGN_PPM_PERIOD1 0x154
|
||||
#define QSERDES_V4_RX_SIGN_PPM_PERIOD2 0x158
|
||||
#define QSERDES_V4_RX_RX_PWM_ENABLE_AND_DATA 0x15c
|
||||
#define QSERDES_V4_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x160
|
||||
#define QSERDES_V4_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x164
|
||||
#define QSERDES_V4_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x168
|
||||
#define QSERDES_V4_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x16c
|
||||
#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
|
||||
#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
|
||||
#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
|
||||
#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c
|
||||
#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180
|
||||
#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184
|
||||
#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188
|
||||
#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c
|
||||
#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190
|
||||
#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194
|
||||
#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198
|
||||
#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c
|
||||
#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
|
||||
#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
|
||||
#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
|
||||
#define QSERDES_V4_RX_PHPRE_CTRL 0x1ac
|
||||
#define QSERDES_V4_RX_PHPRE_INITVAL 0x1b0
|
||||
#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4
|
||||
#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8
|
||||
#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
|
||||
#define QSERDES_V4_RX_DCC_CTRL2 0x1c0
|
||||
#define QSERDES_V4_RX_VTH_CODE 0x1c4
|
||||
#define QSERDES_V4_RX_VTH_MIN_THRESH 0x1c8
|
||||
#define QSERDES_V4_RX_VTH_MAX_THRESH 0x1cc
|
||||
#define QSERDES_V4_RX_ALOG_OBSV_BUS_CTRL_1 0x1d0
|
||||
#define QSERDES_V4_RX_PI_CTRL1 0x1d4
|
||||
#define QSERDES_V4_RX_PI_CTRL2 0x1d8
|
||||
#define QSERDES_V4_RX_PI_QUAD 0x1dc
|
||||
#define QSERDES_V4_RX_IDATA1 0x1e0
|
||||
#define QSERDES_V4_RX_IDATA2 0x1e4
|
||||
#define QSERDES_V4_RX_AUX_DATA1 0x1e8
|
||||
#define QSERDES_V4_RX_AUX_DATA2 0x1ec
|
||||
#define QSERDES_V4_RX_AC_JTAG_OUTP 0x1f0
|
||||
#define QSERDES_V4_RX_AC_JTAG_OUTN 0x1f4
|
||||
#define QSERDES_V4_RX_RX_SIGDET 0x1f8
|
||||
#define QSERDES_V4_RX_ALOG_OBSV_BUS_STATUS_1 0x1fc
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,43 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_
|
||||
|
||||
/* Only for QMP V4_20 PHY - TX registers */
|
||||
#define QSERDES_V4_20_TX_LANE_MODE_1 0x88
|
||||
#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
|
||||
#define QSERDES_V4_20_TX_LANE_MODE_3 0x90
|
||||
#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
|
||||
#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
|
||||
|
||||
/* Only for QMP V4_20 PHY - RX registers */
|
||||
#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
|
||||
#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
|
||||
#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
|
||||
#define QSERDES_V4_20_RX_DFE_3 0x110
|
||||
#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
|
||||
#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138
|
||||
#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150
|
||||
#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8
|
||||
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc
|
||||
#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200
|
||||
#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
|
||||
#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,231 @@
|
||||
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_
|
||||
|
||||
/* Only for QMP V5 PHY - TX registers */
|
||||
#define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
|
||||
#define QSERDES_V5_TX_BIST_INVERT 0x004
|
||||
#define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
|
||||
#define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
|
||||
#define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
|
||||
#define QSERDES_V5_TX_TX_DRV_LVL 0x014
|
||||
#define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
|
||||
#define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
|
||||
#define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
|
||||
#define QSERDES_V5_TX_TX_BAND 0x024
|
||||
#define QSERDES_V5_TX_SLEW_CNTL 0x028
|
||||
#define QSERDES_V5_TX_INTERFACE_SELECT 0x02c
|
||||
#define QSERDES_V5_TX_LPB_EN 0x030
|
||||
#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034
|
||||
#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038
|
||||
#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c
|
||||
#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040
|
||||
#define QSERDES_V5_TX_PERL_LENGTH1 0x044
|
||||
#define QSERDES_V5_TX_PERL_LENGTH2 0x048
|
||||
#define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c
|
||||
#define QSERDES_V5_TX_DEBUG_BUS_SEL 0x050
|
||||
#define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x054
|
||||
#define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x058
|
||||
#define QSERDES_V5_TX_TX_POL_INV 0x05c
|
||||
#define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
|
||||
#define QSERDES_V5_TX_BIST_PATTERN1 0x064
|
||||
#define QSERDES_V5_TX_BIST_PATTERN2 0x068
|
||||
#define QSERDES_V5_TX_BIST_PATTERN3 0x06c
|
||||
#define QSERDES_V5_TX_BIST_PATTERN4 0x070
|
||||
#define QSERDES_V5_TX_BIST_PATTERN5 0x074
|
||||
#define QSERDES_V5_TX_BIST_PATTERN6 0x078
|
||||
#define QSERDES_V5_TX_BIST_PATTERN7 0x07c
|
||||
#define QSERDES_V5_TX_BIST_PATTERN8 0x080
|
||||
#define QSERDES_V5_TX_LANE_MODE_1 0x084
|
||||
#define QSERDES_V5_TX_LANE_MODE_2 0x088
|
||||
#define QSERDES_V5_TX_LANE_MODE_3 0x08c
|
||||
#define QSERDES_V5_TX_LANE_MODE_4 0x090
|
||||
#define QSERDES_V5_TX_LANE_MODE_5 0x094
|
||||
#define QSERDES_V5_TX_ATB_SEL1 0x098
|
||||
#define QSERDES_V5_TX_ATB_SEL2 0x09c
|
||||
#define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a0
|
||||
#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4
|
||||
#define QSERDES_V5_TX_PRBS_SEED1 0x0a8
|
||||
#define QSERDES_V5_TX_PRBS_SEED2 0x0ac
|
||||
#define QSERDES_V5_TX_PRBS_SEED3 0x0b0
|
||||
#define QSERDES_V5_TX_PRBS_SEED4 0x0b4
|
||||
#define QSERDES_V5_TX_RESET_GEN 0x0b8
|
||||
#define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc
|
||||
#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0
|
||||
#define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c4
|
||||
#define QSERDES_V5_TX_VMODE_CTRL1 0x0c8
|
||||
#define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc
|
||||
#define QSERDES_V5_TX_BIST_STATUS 0x0d0
|
||||
#define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d4
|
||||
#define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d8
|
||||
#define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc
|
||||
#define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e0
|
||||
#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4
|
||||
#define QSERDES_V5_TX_PRE_EMPH 0x0e8
|
||||
#define QSERDES_V5_TX_SW_RESET 0x0ec
|
||||
#define QSERDES_V5_TX_DCC_OFFSET 0x0f0
|
||||
#define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4
|
||||
#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f8
|
||||
#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc
|
||||
#define QSERDES_V5_TX_DIG_BKUP_CTRL 0x100
|
||||
#define QSERDES_V5_TX_DEBUG_BUS0 0x104
|
||||
#define QSERDES_V5_TX_DEBUG_BUS1 0x108
|
||||
#define QSERDES_V5_TX_DEBUG_BUS2 0x10c
|
||||
#define QSERDES_V5_TX_DEBUG_BUS3 0x110
|
||||
#define QSERDES_V5_TX_READ_EQCODE 0x114
|
||||
#define QSERDES_V5_TX_READ_OFFSETCODE 0x118
|
||||
#define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c
|
||||
#define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x120
|
||||
#define QSERDES_V5_TX_VGA_READ_CODE 0x124
|
||||
#define QSERDES_V5_TX_VTH_READ_CODE 0x128
|
||||
#define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c
|
||||
#define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x130
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_I 0x134
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x138
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x140
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_A 0x144
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x148
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x150
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x154
|
||||
#define QSERDES_V5_TX_DCC_CAL_STATUS 0x158
|
||||
#define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c
|
||||
|
||||
/* Only for QMP V5 PHY - RX registers */
|
||||
#define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000
|
||||
#define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004
|
||||
#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008
|
||||
#define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c
|
||||
#define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010
|
||||
#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014
|
||||
#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018
|
||||
#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c
|
||||
#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020
|
||||
#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024
|
||||
#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
|
||||
#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c
|
||||
#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030
|
||||
#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
|
||||
#define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038
|
||||
#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
|
||||
#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
|
||||
#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044
|
||||
#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048
|
||||
#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c
|
||||
#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050
|
||||
#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054
|
||||
#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058
|
||||
#define QSERDES_V5_RX_AUX_CONTROL 0x05c
|
||||
#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060
|
||||
#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064
|
||||
#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
|
||||
#define QSERDES_V5_RX_AC_JTAG_INITP 0x06c
|
||||
#define QSERDES_V5_RX_AC_JTAG_INITN 0x070
|
||||
#define QSERDES_V5_RX_AC_JTAG_LVL 0x074
|
||||
#define QSERDES_V5_RX_AC_JTAG_MODE 0x078
|
||||
#define QSERDES_V5_RX_AC_JTAG_RESET 0x07c
|
||||
#define QSERDES_V5_RX_RX_TERM_BW 0x080
|
||||
#define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084
|
||||
#define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088
|
||||
#define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c
|
||||
#define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090
|
||||
#define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094
|
||||
#define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098
|
||||
#define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c
|
||||
#define QSERDES_V5_RX_RX_IDAC_EN 0x0a0
|
||||
#define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4
|
||||
#define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8
|
||||
#define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac
|
||||
#define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0
|
||||
#define QSERDES_V5_RX_DFE_1 0x0b4
|
||||
#define QSERDES_V5_RX_DFE_2 0x0b8
|
||||
#define QSERDES_V5_RX_DFE_3 0x0bc
|
||||
#define QSERDES_V5_RX_DFE_4 0x0c0
|
||||
#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4
|
||||
#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8
|
||||
#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
|
||||
#define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0
|
||||
#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
|
||||
#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
|
||||
#define QSERDES_V5_RX_GM_CAL 0x0dc
|
||||
#define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0
|
||||
#define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4
|
||||
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
|
||||
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
|
||||
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
|
||||
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
|
||||
#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8
|
||||
#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
|
||||
#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100
|
||||
#define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104
|
||||
#define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108
|
||||
#define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c
|
||||
#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
|
||||
#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
|
||||
#define QSERDES_V5_RX_SIGDET_ENABLES 0x118
|
||||
#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c
|
||||
#define QSERDES_V5_RX_SIGDET_LVL 0x120
|
||||
#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124
|
||||
#define QSERDES_V5_RX_RX_BAND 0x128
|
||||
#define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c
|
||||
#define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130
|
||||
#define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134
|
||||
#define QSERDES_V5_RX_JITTER_GEN_MODE 0x138
|
||||
#define QSERDES_V5_RX_SJ_AMP1 0x13c
|
||||
#define QSERDES_V5_RX_SJ_AMP2 0x140
|
||||
#define QSERDES_V5_RX_SJ_PER1 0x144
|
||||
#define QSERDES_V5_RX_SJ_PER2 0x148
|
||||
#define QSERDES_V5_RX_PPM_OFFSET1 0x14c
|
||||
#define QSERDES_V5_RX_PPM_OFFSET2 0x150
|
||||
#define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154
|
||||
#define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158
|
||||
#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c
|
||||
#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160
|
||||
#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164
|
||||
#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168
|
||||
#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c
|
||||
#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170
|
||||
#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174
|
||||
#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178
|
||||
#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c
|
||||
#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180
|
||||
#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184
|
||||
#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188
|
||||
#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c
|
||||
#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190
|
||||
#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194
|
||||
#define QSERDES_V5_RX_PHPRE_CTRL 0x198
|
||||
#define QSERDES_V5_RX_PHPRE_INITVAL 0x19c
|
||||
#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0
|
||||
#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
|
||||
#define QSERDES_V5_RX_DCC_CTRL1 0x1a8
|
||||
#define QSERDES_V5_RX_DCC_CTRL2 0x1ac
|
||||
#define QSERDES_V5_RX_VTH_CODE 0x1b0
|
||||
#define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4
|
||||
#define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8
|
||||
#define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc
|
||||
#define QSERDES_V5_RX_PI_CTRL1 0x1c0
|
||||
#define QSERDES_V5_RX_PI_CTRL2 0x1c4
|
||||
#define QSERDES_V5_RX_PI_QUAD 0x1c8
|
||||
#define QSERDES_V5_RX_IDATA1 0x1cc
|
||||
#define QSERDES_V5_RX_IDATA2 0x1d0
|
||||
#define QSERDES_V5_RX_AUX_DATA1 0x1d4
|
||||
#define QSERDES_V5_RX_AUX_DATA2 0x1d8
|
||||
#define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc
|
||||
#define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0
|
||||
#define QSERDES_V5_RX_RX_SIGDET 0x1e4
|
||||
#define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8
|
||||
|
||||
/* Only for QMP V5 UFS ? */
|
||||
#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
|
||||
#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
|
||||
#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
|
||||
#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,60 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
|
||||
|
||||
/* Only for QMP V5_20 PHY - TX registers */
|
||||
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
|
||||
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
|
||||
#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
|
||||
#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
|
||||
|
||||
/* Only for QMP V5_20 PHY - RX registers */
|
||||
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
|
||||
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
|
||||
#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
|
||||
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
|
||||
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
|
||||
#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
|
||||
#define QSERDES_V5_20_RX_DFE_3 0x090
|
||||
#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4
|
||||
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4
|
||||
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8
|
||||
#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc
|
||||
#define QSERDES_V5_20_RX_GM_CAL 0x0ec
|
||||
#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac
|
||||
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0
|
||||
#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4
|
||||
#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0
|
||||
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
|
||||
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8
|
||||
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
|
||||
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200
|
||||
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
|
||||
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208
|
||||
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210
|
||||
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
|
||||
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,205 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_TXRX_H_
|
||||
|
||||
/* Only for QMP V2 PHY - TX registers */
|
||||
#define QSERDES_TX_BIST_MODE_LANENO 0x000
|
||||
#define QSERDES_TX_BIST_INVERT 0x004
|
||||
#define QSERDES_TX_CLKBUF_ENABLE 0x008
|
||||
#define QSERDES_TX_CMN_CONTROL_ONE 0x00c
|
||||
#define QSERDES_TX_CMN_CONTROL_TWO 0x010
|
||||
#define QSERDES_TX_CMN_CONTROL_THREE 0x014
|
||||
#define QSERDES_TX_TX_EMP_POST1_LVL 0x018
|
||||
#define QSERDES_TX_TX_POST2_EMPH 0x01c
|
||||
#define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
|
||||
#define QSERDES_TX_HP_PD_ENABLES 0x024
|
||||
#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x028
|
||||
#define QSERDES_TX_TX_DRV_LVL 0x02c
|
||||
#define QSERDES_TX_TX_DRV_LVL_OFFSET 0x030
|
||||
#define QSERDES_TX_RESET_TSYNC_EN 0x034
|
||||
#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x038
|
||||
#define QSERDES_TX_TX_BAND 0x03c
|
||||
#define QSERDES_TX_SLEW_CNTL 0x040
|
||||
#define QSERDES_TX_INTERFACE_SELECT 0x044
|
||||
#define QSERDES_TX_LPB_EN 0x048
|
||||
#define QSERDES_TX_RES_CODE_LANE_TX 0x04c
|
||||
#define QSERDES_TX_RES_CODE_LANE_RX 0x050
|
||||
#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
|
||||
#define QSERDES_TX_PERL_LENGTH1 0x058
|
||||
#define QSERDES_TX_PERL_LENGTH2 0x05c
|
||||
#define QSERDES_TX_SERDES_BYP_EN_OUT 0x060
|
||||
#define QSERDES_TX_DEBUG_BUS_SEL 0x064
|
||||
#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
|
||||
#define QSERDES_TX_TX_POL_INV 0x06c
|
||||
#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x070
|
||||
#define QSERDES_TX_BIST_PATTERN1 0x074
|
||||
#define QSERDES_TX_BIST_PATTERN2 0x078
|
||||
#define QSERDES_TX_BIST_PATTERN3 0x07c
|
||||
#define QSERDES_TX_BIST_PATTERN4 0x080
|
||||
#define QSERDES_TX_BIST_PATTERN5 0x084
|
||||
#define QSERDES_TX_BIST_PATTERN6 0x088
|
||||
#define QSERDES_TX_BIST_PATTERN7 0x08c
|
||||
#define QSERDES_TX_BIST_PATTERN8 0x090
|
||||
#define QSERDES_TX_LANE_MODE 0x094
|
||||
#define QSERDES_TX_IDAC_CAL_LANE_MODE 0x098
|
||||
#define QSERDES_TX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x09c
|
||||
#define QSERDES_TX_ATB_SEL1 0x0a0
|
||||
#define QSERDES_TX_ATB_SEL2 0x0a4
|
||||
#define QSERDES_TX_RCV_DETECT_LVL 0x0a8
|
||||
#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
|
||||
#define QSERDES_TX_PRBS_SEED1 0x0b0
|
||||
#define QSERDES_TX_PRBS_SEED2 0x0b4
|
||||
#define QSERDES_TX_PRBS_SEED3 0x0b8
|
||||
#define QSERDES_TX_PRBS_SEED4 0x0bc
|
||||
#define QSERDES_TX_RESET_GEN 0x0c0
|
||||
#define QSERDES_TX_RESET_GEN_MUXES 0x0c4
|
||||
#define QSERDES_TX_TRAN_DRVR_EMP_EN 0x0c8
|
||||
#define QSERDES_TX_TX_INTERFACE_MODE 0x0cc
|
||||
#define QSERDES_TX_PWM_CTRL 0x0d0
|
||||
#define QSERDES_TX_PWM_ENCODED_OR_DATA 0x0d4
|
||||
#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0d8
|
||||
#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0dc
|
||||
#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0e0
|
||||
#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0e4
|
||||
#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0e8
|
||||
#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0ec
|
||||
#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0f0
|
||||
#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0f4
|
||||
#define QSERDES_TX_VMODE_CTRL1 0x0f8
|
||||
#define QSERDES_TX_VMODE_CTRL2 0x0fc
|
||||
#define QSERDES_TX_TX_ALOG_INTF_OBSV_CNTL 0x100
|
||||
#define QSERDES_TX_BIST_STATUS 0x104
|
||||
#define QSERDES_TX_BIST_ERROR_COUNT1 0x108
|
||||
#define QSERDES_TX_BIST_ERROR_COUNT2 0x10c
|
||||
#define QSERDES_TX_TX_ALOG_INTF_OBSV 0x110
|
||||
|
||||
/* Only for QMP V2 PHY - RX registers */
|
||||
#define QSERDES_RX_UCDR_FO_GAIN_HALF 0x000
|
||||
#define QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x004
|
||||
#define QSERDES_RX_UCDR_FO_GAIN_EIGHTH 0x008
|
||||
#define QSERDES_RX_UCDR_FO_GAIN 0x00c
|
||||
#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
|
||||
#define QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x014
|
||||
#define QSERDES_RX_UCDR_SO_GAIN_EIGHTH 0x018
|
||||
#define QSERDES_RX_UCDR_SO_GAIN 0x01c
|
||||
#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x020
|
||||
#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x024
|
||||
#define QSERDES_RX_UCDR_SVS_FO_GAIN_EIGHTH 0x028
|
||||
#define QSERDES_RX_UCDR_SVS_FO_GAIN 0x02c
|
||||
#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030
|
||||
#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034
|
||||
#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038
|
||||
#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c
|
||||
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
|
||||
#define QSERDES_RX_UCDR_FD_GAIN 0x044
|
||||
#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
|
||||
#define QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x04c
|
||||
#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x050
|
||||
#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x054
|
||||
#define QSERDES_RX_UCDR_MODULATE 0x058
|
||||
#define QSERDES_RX_UCDR_PI_CONTROLS 0x05c
|
||||
#define QSERDES_RX_RBIST_CONTROL 0x060
|
||||
#define QSERDES_RX_AUX_CONTROL 0x064
|
||||
#define QSERDES_RX_AUX_DATA_TCOARSE 0x068
|
||||
#define QSERDES_RX_AUX_DATA_TFINE_LSB 0x06c
|
||||
#define QSERDES_RX_AUX_DATA_TFINE_MSB 0x070
|
||||
#define QSERDES_RX_RCLK_AUXDATA_SEL 0x074
|
||||
#define QSERDES_RX_AC_JTAG_ENABLE 0x078
|
||||
#define QSERDES_RX_AC_JTAG_INITP 0x07c
|
||||
#define QSERDES_RX_AC_JTAG_INITN 0x080
|
||||
#define QSERDES_RX_AC_JTAG_LVL 0x084
|
||||
#define QSERDES_RX_AC_JTAG_MODE 0x088
|
||||
#define QSERDES_RX_AC_JTAG_RESET 0x08c
|
||||
#define QSERDES_RX_RX_TERM_BW 0x090
|
||||
#define QSERDES_RX_RX_RCVR_IQ_EN 0x094
|
||||
#define QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x098
|
||||
#define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x09c
|
||||
#define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x0a0
|
||||
#define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x0a4
|
||||
#define QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x0a8
|
||||
#define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x0ac
|
||||
#define QSERDES_RX_RX_IDAC_EN 0x0b0
|
||||
#define QSERDES_RX_RX_IDAC_ENABLES 0x0b4
|
||||
#define QSERDES_RX_RX_IDAC_SIGN 0x0b8
|
||||
#define QSERDES_RX_RX_HIGHZ_HIGHRATE 0x0bc
|
||||
#define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0c0
|
||||
#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
|
||||
#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
|
||||
#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
|
||||
#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
|
||||
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d4
|
||||
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
|
||||
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
|
||||
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
|
||||
#define QSERDES_RX_RX_IDAC_CAL_CONFIGURATION 0x0e4
|
||||
#define QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x0e8
|
||||
#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x0ec
|
||||
#define QSERDES_RX_RX_IDAC_ENDSAMP_LOW 0x0f0
|
||||
#define QSERDES_RX_RX_IDAC_ENDSAMP_HIGH 0x0f4
|
||||
#define QSERDES_RX_RX_IDAC_MIDPOINT_LOW 0x0f8
|
||||
#define QSERDES_RX_RX_IDAC_MIDPOINT_HIGH 0x0fc
|
||||
#define QSERDES_RX_RX_EQ_OFFSET_LSB 0x100
|
||||
#define QSERDES_RX_RX_EQ_OFFSET_MSB 0x104
|
||||
#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
|
||||
#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
|
||||
#define QSERDES_RX_SIGDET_ENABLES 0x110
|
||||
#define QSERDES_RX_SIGDET_CNTRL 0x114
|
||||
#define QSERDES_RX_SIGDET_LVL 0x118
|
||||
#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
|
||||
#define QSERDES_RX_RX_BAND 0x120
|
||||
#define QSERDES_RX_CDR_FREEZE_UP_DN 0x124
|
||||
#define QSERDES_RX_CDR_RESET_OVERRIDE 0x128
|
||||
#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
|
||||
#define QSERDES_RX_JITTER_GEN_MODE 0x130
|
||||
#define QSERDES_RX_BUJ_AMP 0x134
|
||||
#define QSERDES_RX_SJ_AMP1 0x138
|
||||
#define QSERDES_RX_SJ_AMP2 0x13c
|
||||
#define QSERDES_RX_SJ_PER1 0x140
|
||||
#define QSERDES_RX_SJ_PER2 0x144
|
||||
#define QSERDES_RX_BUJ_STEP_FREQ1 0x148
|
||||
#define QSERDES_RX_BUJ_STEP_FREQ2 0x14c
|
||||
#define QSERDES_RX_PPM_OFFSET1 0x150
|
||||
#define QSERDES_RX_PPM_OFFSET2 0x154
|
||||
#define QSERDES_RX_SIGN_PPM_PERIOD1 0x158
|
||||
#define QSERDES_RX_SIGN_PPM_PERIOD2 0x15c
|
||||
#define QSERDES_RX_SSC_CTRL 0x160
|
||||
#define QSERDES_RX_SSC_COUNT1 0x164
|
||||
#define QSERDES_RX_SSC_COUNT2 0x168
|
||||
#define QSERDES_RX_RX_ALOG_INTF_OBSV_CNTL 0x16c
|
||||
#define QSERDES_RX_RX_PWM_ENABLE_AND_DATA 0x170
|
||||
#define QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x174
|
||||
#define QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x178
|
||||
#define QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x17c
|
||||
#define QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x180
|
||||
#define QSERDES_RX_PI_CTRL1 0x184
|
||||
#define QSERDES_RX_PI_CTRL2 0x188
|
||||
#define QSERDES_RX_PI_QUAD 0x18c
|
||||
#define QSERDES_RX_IDATA1 0x190
|
||||
#define QSERDES_RX_IDATA2 0x194
|
||||
#define QSERDES_RX_AUX_DATA1 0x198
|
||||
#define QSERDES_RX_AUX_DATA2 0x19c
|
||||
#define QSERDES_RX_AC_JTAG_OUTP 0x1a0
|
||||
#define QSERDES_RX_AC_JTAG_OUTN 0x1a4
|
||||
#define QSERDES_RX_RX_SIGDET 0x1a8
|
||||
#define QSERDES_RX_RX_VDCOFF 0x1ac
|
||||
#define QSERDES_RX_IDAC_CAL_ON 0x1b0
|
||||
#define QSERDES_RX_IDAC_STATUS_I 0x1b4
|
||||
#define QSERDES_RX_IDAC_STATUS_IBAR 0x1b8
|
||||
#define QSERDES_RX_IDAC_STATUS_Q 0x1bc
|
||||
#define QSERDES_RX_IDAC_STATUS_QBAR 0x1c0
|
||||
#define QSERDES_RX_IDAC_STATUS_A 0x1c4
|
||||
#define QSERDES_RX_IDAC_STATUS_ABAR 0x1c8
|
||||
#define QSERDES_RX_CALST_STATUS_I 0x1cc
|
||||
#define QSERDES_RX_CALST_STATUS_Q 0x1d0
|
||||
#define QSERDES_RX_CALST_STATUS_A 0x1d4
|
||||
#define QSERDES_RX_RX_ALOG_INTF_OBSV 0x1d8
|
||||
#define QSERDES_RX_READ_EQCODE 0x1dc
|
||||
#define QSERDES_RX_READ_OFFSETCODE 0x1e0
|
||||
#define QSERDES_RX_IA_ERROR_COUNTER_LOW 0x1e4
|
||||
#define QSERDES_RX_IA_ERROR_COUNTER_HIGH 0x1e8
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+29
-1213
File diff suppressed because it is too large
Load Diff
@@ -978,7 +978,9 @@ static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
|
||||
|
||||
switch (rport->port_id) {
|
||||
case USB2PHY_PORT_OTG:
|
||||
ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
|
||||
if (rport->mode != USB_DR_MODE_HOST &&
|
||||
rport->mode != USB_DR_MODE_UNKNOWN)
|
||||
ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
|
||||
break;
|
||||
case USB2PHY_PORT_HOST:
|
||||
ret |= rockchip_usb2phy_linestate_irq(irq, rport);
|
||||
@@ -1162,6 +1164,12 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
|
||||
EXTCON_USB_HOST, &rport->event_nb);
|
||||
if (ret)
|
||||
dev_err(rphy->dev, "register USB HOST notifier failed\n");
|
||||
|
||||
if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
|
||||
/* do initial sync of usb state */
|
||||
ret = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
|
||||
extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !ret);
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
@@ -1283,7 +1291,7 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
|
||||
|
||||
phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "failed to create phy\n");
|
||||
dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n");
|
||||
ret = PTR_ERR(phy);
|
||||
goto put_child;
|
||||
}
|
||||
|
||||
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o
|
||||
phy-exynos-ufs-y += phy-samsung-ufs.o
|
||||
phy-exynos-ufs-y += phy-exynos7-ufs.o
|
||||
phy-exynos-ufs-y += phy-exynosautov9-ufs.o
|
||||
phy-exynos-ufs-y += phy-fsd-ufs.o
|
||||
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
|
||||
phy-exynos-usb2-y += phy-samsung-usb2.o
|
||||
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
|
||||
|
||||
@@ -11,6 +11,8 @@
|
||||
#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
|
||||
#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
|
||||
|
||||
#define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
|
||||
|
||||
/* Calibration for phy initialization */
|
||||
static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
|
||||
PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
|
||||
@@ -66,12 +68,18 @@ static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
|
||||
[CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
|
||||
};
|
||||
|
||||
static const char * const exynos7_ufs_phy_clks[] = {
|
||||
"tx0_symbol_clk", "rx0_symbol_clk", "rx1_symbol_clk", "ref_clk",
|
||||
};
|
||||
|
||||
const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
|
||||
.cfg = exynos7_ufs_phy_cfgs,
|
||||
.cfgs = exynos7_ufs_phy_cfgs,
|
||||
.isol = {
|
||||
.offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
|
||||
.mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
|
||||
.en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
|
||||
},
|
||||
.has_symbol_clk = 1,
|
||||
.clk_list = exynos7_ufs_phy_clks,
|
||||
.num_clks = ARRAY_SIZE(exynos7_ufs_phy_clks),
|
||||
.cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
|
||||
};
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728
|
||||
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
|
||||
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
|
||||
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
|
||||
|
||||
#define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
|
||||
PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
|
||||
@@ -31,22 +32,22 @@ static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = {
|
||||
PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
|
||||
PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),
|
||||
|
||||
PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),
|
||||
|
||||
END_UFS_PHY_CFG,
|
||||
};
|
||||
|
||||
/* Calibration for HS mode series A/B */
|
||||
static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {
|
||||
PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY),
|
||||
PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY),
|
||||
PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY),
|
||||
PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),
|
||||
PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),
|
||||
PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),
|
||||
|
||||
PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
|
||||
PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
|
||||
PWR_MODE_HS_G3_SER_B),
|
||||
PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
|
||||
PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
|
||||
PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
|
||||
PWR_MODE_HS_G3_SER_B),
|
||||
PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
|
||||
|
||||
END_UFS_PHY_CFG,
|
||||
};
|
||||
@@ -56,12 +57,18 @@ static const struct samsung_ufs_phy_cfg *exynosautov9_ufs_phy_cfgs[CFG_TAG_MAX]
|
||||
[CFG_PRE_PWR_HS] = exynosautov9_pre_pwr_hs_cfg,
|
||||
};
|
||||
|
||||
static const char * const exynosautov9_ufs_phy_clks[] = {
|
||||
"ref_clk",
|
||||
};
|
||||
|
||||
const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
|
||||
.cfg = exynosautov9_ufs_phy_cfgs,
|
||||
.cfgs = exynosautov9_ufs_phy_cfgs,
|
||||
.isol = {
|
||||
.offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL,
|
||||
.mask = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK,
|
||||
.en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
|
||||
},
|
||||
.has_symbol_clk = 0,
|
||||
.clk_list = exynosautov9_ufs_phy_clks,
|
||||
.num_clks = ARRAY_SIZE(exynosautov9_ufs_phy_clks),
|
||||
.cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
|
||||
};
|
||||
|
||||
@@ -0,0 +1,63 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* UFS PHY driver data for FSD SoC
|
||||
*
|
||||
* Copyright (C) 2022 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
#include "phy-samsung-ufs.h"
|
||||
|
||||
#define FSD_EMBEDDED_COMBO_PHY_CTRL 0x724
|
||||
#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
|
||||
#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
|
||||
#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x6e
|
||||
|
||||
static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = {
|
||||
PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
|
||||
PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
|
||||
PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
|
||||
PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
|
||||
PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
|
||||
END_UFS_PHY_CFG
|
||||
};
|
||||
|
||||
/* Calibration for HS mode series A/B */
|
||||
static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = {
|
||||
END_UFS_PHY_CFG
|
||||
};
|
||||
|
||||
/* Calibration for HS mode series A/B atfer PMC */
|
||||
static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = {
|
||||
END_UFS_PHY_CFG
|
||||
};
|
||||
|
||||
static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = {
|
||||
[CFG_PRE_INIT] = fsd_pre_init_cfg,
|
||||
[CFG_PRE_PWR_HS] = fsd_pre_pwr_hs_cfg,
|
||||
[CFG_POST_PWR_HS] = fsd_post_pwr_hs_cfg,
|
||||
};
|
||||
|
||||
static const char * const fsd_ufs_phy_clks[] = {
|
||||
"ref_clk",
|
||||
};
|
||||
|
||||
const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
|
||||
.cfgs = fsd_ufs_phy_cfgs,
|
||||
.isol = {
|
||||
.offset = FSD_EMBEDDED_COMBO_PHY_CTRL,
|
||||
.mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK,
|
||||
.en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN,
|
||||
},
|
||||
.clk_list = fsd_ufs_phy_clks,
|
||||
.num_clks = ARRAY_SIZE(fsd_ufs_phy_clks),
|
||||
.cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
|
||||
};
|
||||
@@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
|
||||
}
|
||||
|
||||
err = readl_poll_timeout(
|
||||
ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
|
||||
ufs_phy->reg_pma +
|
||||
PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
|
||||
val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
|
||||
if (err)
|
||||
dev_err(ufs_phy->dev,
|
||||
@@ -75,7 +76,7 @@ out:
|
||||
static int samsung_ufs_phy_calibrate(struct phy *phy)
|
||||
{
|
||||
struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
|
||||
struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
|
||||
const struct samsung_ufs_phy_cfg * const *cfgs = ufs_phy->cfgs;
|
||||
const struct samsung_ufs_phy_cfg *cfg;
|
||||
int err = 0;
|
||||
int i;
|
||||
@@ -130,113 +131,63 @@ out:
|
||||
return err;
|
||||
}
|
||||
|
||||
static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy *phy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
|
||||
if (IS_ERR(phy->tx0_symbol_clk)) {
|
||||
dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
|
||||
return PTR_ERR(phy->tx0_symbol_clk);
|
||||
}
|
||||
|
||||
phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
|
||||
if (IS_ERR(phy->rx0_symbol_clk)) {
|
||||
dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
|
||||
return PTR_ERR(phy->rx0_symbol_clk);
|
||||
}
|
||||
|
||||
phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
|
||||
if (IS_ERR(phy->rx1_symbol_clk)) {
|
||||
dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
|
||||
return PTR_ERR(phy->rx1_symbol_clk);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(phy->tx0_symbol_clk);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n", __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(phy->rx0_symbol_clk);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n", __func__, ret);
|
||||
goto out_disable_tx0_clk;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(phy->rx1_symbol_clk);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n", __func__, ret);
|
||||
goto out_disable_rx0_clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
out_disable_rx0_clk:
|
||||
clk_disable_unprepare(phy->rx0_symbol_clk);
|
||||
out_disable_tx0_clk:
|
||||
clk_disable_unprepare(phy->tx0_symbol_clk);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
const struct samsung_ufs_phy_drvdata *drvdata = phy->drvdata;
|
||||
int num_clks = drvdata->num_clks;
|
||||
|
||||
phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
|
||||
if (IS_ERR(phy->ref_clk))
|
||||
dev_err(phy->dev, "failed to get ref_clk clock\n");
|
||||
phy->clks = devm_kcalloc(phy->dev, num_clks, sizeof(*phy->clks),
|
||||
GFP_KERNEL);
|
||||
if (!phy->clks)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = clk_prepare_enable(phy->ref_clk);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: ref_clk enable failed %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
for (i = 0; i < num_clks; i++)
|
||||
phy->clks[i].id = drvdata->clk_list[i];
|
||||
|
||||
dev_dbg(phy->dev, "UFS MPHY ref_clk_rate = %ld\n", clk_get_rate(phy->ref_clk));
|
||||
|
||||
return 0;
|
||||
return devm_clk_bulk_get(phy->dev, num_clks, phy->clks);
|
||||
}
|
||||
|
||||
static int samsung_ufs_phy_init(struct phy *phy)
|
||||
{
|
||||
struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
|
||||
int ret;
|
||||
|
||||
ss_phy->lane_cnt = phy->attrs.bus_width;
|
||||
ss_phy->ufs_phy_state = CFG_PRE_INIT;
|
||||
|
||||
if (ss_phy->drvdata->has_symbol_clk) {
|
||||
ret = samsung_ufs_phy_symbol_clk_init(ss_phy);
|
||||
if (ret)
|
||||
dev_err(ss_phy->dev, "failed to set ufs phy symbol clocks\n");
|
||||
}
|
||||
|
||||
ret = samsung_ufs_phy_clks_init(ss_phy);
|
||||
if (ret)
|
||||
dev_err(ss_phy->dev, "failed to set ufs phy clocks\n");
|
||||
|
||||
ret = samsung_ufs_phy_calibrate(phy);
|
||||
if (ret)
|
||||
dev_err(ss_phy->dev, "ufs phy calibration failed\n");
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int samsung_ufs_phy_power_on(struct phy *phy)
|
||||
{
|
||||
struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
|
||||
int ret;
|
||||
|
||||
samsung_ufs_phy_ctrl_isol(ss_phy, false);
|
||||
return 0;
|
||||
|
||||
ret = clk_bulk_prepare_enable(ss_phy->drvdata->num_clks, ss_phy->clks);
|
||||
if (ret) {
|
||||
dev_err(ss_phy->dev, "failed to enable ufs phy clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ss_phy->ufs_phy_state == CFG_PRE_INIT) {
|
||||
ret = samsung_ufs_phy_calibrate(phy);
|
||||
if (ret)
|
||||
dev_err(ss_phy->dev, "ufs phy calibration failed\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int samsung_ufs_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
|
||||
|
||||
clk_bulk_disable_unprepare(ss_phy->drvdata->num_clks, ss_phy->clks);
|
||||
|
||||
samsung_ufs_phy_ctrl_isol(ss_phy, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -257,13 +208,7 @@ static int samsung_ufs_phy_exit(struct phy *phy)
|
||||
{
|
||||
struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
|
||||
|
||||
clk_disable_unprepare(ss_phy->ref_clk);
|
||||
|
||||
if (ss_phy->drvdata->has_symbol_clk) {
|
||||
clk_disable_unprepare(ss_phy->tx0_symbol_clk);
|
||||
clk_disable_unprepare(ss_phy->rx0_symbol_clk);
|
||||
clk_disable_unprepare(ss_phy->rx1_symbol_clk);
|
||||
}
|
||||
ss_phy->ufs_phy_state = CFG_TAG_MAX;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -288,6 +233,7 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)
|
||||
struct phy *gen_phy;
|
||||
struct phy_provider *phy_provider;
|
||||
const struct samsung_ufs_phy_drvdata *drvdata;
|
||||
u32 isol_offset;
|
||||
int err = 0;
|
||||
|
||||
match = of_match_node(samsung_ufs_phy_match, dev->of_node);
|
||||
@@ -327,10 +273,21 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)
|
||||
drvdata = match->data;
|
||||
phy->dev = dev;
|
||||
phy->drvdata = drvdata;
|
||||
phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg;
|
||||
phy->isol = &drvdata->isol;
|
||||
phy->cfgs = drvdata->cfgs;
|
||||
memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol));
|
||||
|
||||
if (!of_property_read_u32_index(dev->of_node, "samsung,pmu-syscon", 1,
|
||||
&isol_offset))
|
||||
phy->isol.offset = isol_offset;
|
||||
|
||||
phy->lane_cnt = PHY_DEF_LANE_CNT;
|
||||
|
||||
err = samsung_ufs_phy_clks_init(phy);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to get phy clocks\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
phy_set_drvdata(gen_phy, phy);
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
@@ -350,6 +307,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = {
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-ufs-phy",
|
||||
.data = &exynosautov9_ufs_phy,
|
||||
}, {
|
||||
.compatible = "tesla,fsd-ufs-phy",
|
||||
.data = &fsd_ufs_phy,
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
@@ -40,7 +40,6 @@
|
||||
|
||||
/* UFS PHY registers */
|
||||
#define PHY_PLL_LOCK_STATUS 0x1e
|
||||
#define PHY_CDR_LOCK_STATUS 0x5e
|
||||
|
||||
#define PHY_PLL_LOCK_BIT BIT(5)
|
||||
#define PHY_CDR_LOCK_BIT BIT(4)
|
||||
@@ -101,28 +100,28 @@ struct samsung_ufs_phy_cfg {
|
||||
u8 id;
|
||||
};
|
||||
|
||||
struct samsung_ufs_phy_pmu_isol {
|
||||
u32 offset;
|
||||
u32 mask;
|
||||
u32 en;
|
||||
};
|
||||
|
||||
struct samsung_ufs_phy_drvdata {
|
||||
const struct samsung_ufs_phy_cfg **cfg;
|
||||
struct pmu_isol {
|
||||
u32 offset;
|
||||
u32 mask;
|
||||
u32 en;
|
||||
} isol;
|
||||
bool has_symbol_clk;
|
||||
const struct samsung_ufs_phy_cfg **cfgs;
|
||||
struct samsung_ufs_phy_pmu_isol isol;
|
||||
const char * const *clk_list;
|
||||
int num_clks;
|
||||
u32 cdr_lock_status_offset;
|
||||
};
|
||||
|
||||
struct samsung_ufs_phy {
|
||||
struct device *dev;
|
||||
void __iomem *reg_pma;
|
||||
struct regmap *reg_pmu;
|
||||
struct clk *ref_clk;
|
||||
struct clk *ref_clk_parent;
|
||||
struct clk *tx0_symbol_clk;
|
||||
struct clk *rx0_symbol_clk;
|
||||
struct clk *rx1_symbol_clk;
|
||||
struct clk_bulk_data *clks;
|
||||
const struct samsung_ufs_phy_drvdata *drvdata;
|
||||
struct samsung_ufs_phy_cfg **cfg;
|
||||
const struct pmu_isol *isol;
|
||||
const struct samsung_ufs_phy_cfg * const *cfgs;
|
||||
struct samsung_ufs_phy_pmu_isol isol;
|
||||
u8 lane_cnt;
|
||||
int ufs_phy_state;
|
||||
enum phy_mode mode;
|
||||
@@ -136,11 +135,12 @@ static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)
|
||||
static inline void samsung_ufs_phy_ctrl_isol(
|
||||
struct samsung_ufs_phy *phy, u32 isol)
|
||||
{
|
||||
regmap_update_bits(phy->reg_pmu, phy->isol->offset,
|
||||
phy->isol->mask, isol ? 0 : phy->isol->en);
|
||||
regmap_update_bits(phy->reg_pmu, phy->isol.offset,
|
||||
phy->isol.mask, isol ? 0 : phy->isol.en);
|
||||
}
|
||||
|
||||
extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
|
||||
extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
|
||||
extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
|
||||
|
||||
#endif /* _PHY_SAMSUNG_UFS_ */
|
||||
|
||||
@@ -358,7 +358,9 @@ static int stm32_usbphyc_phy_init(struct phy *phy)
|
||||
return 0;
|
||||
|
||||
pll_disable:
|
||||
return stm32_usbphyc_pll_disable(usbphyc);
|
||||
stm32_usbphyc_pll_disable(usbphyc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_usbphyc_phy_exit(struct phy *phy)
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* P2U (PIPE to UPHY) driver for Tegra T194 SoC
|
||||
*
|
||||
* Copyright (C) 2019 NVIDIA Corporation.
|
||||
* Copyright (C) 2019-2022 NVIDIA Corporation.
|
||||
*
|
||||
* Author: Vidya Sagar <vidyas@nvidia.com>
|
||||
*/
|
||||
@@ -14,6 +14,9 @@
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy/phy.h>
|
||||
|
||||
#define P2U_CONTROL_CMN 0x74
|
||||
#define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20)
|
||||
|
||||
#define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0
|
||||
#define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)
|
||||
#define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1)
|
||||
@@ -24,8 +27,17 @@
|
||||
#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xffff
|
||||
#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 160
|
||||
|
||||
#define P2U_DIR_SEARCH_CTRL 0xd4
|
||||
#define P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE BIT(18)
|
||||
|
||||
struct tegra_p2u_of_data {
|
||||
bool one_dir_search;
|
||||
};
|
||||
|
||||
struct tegra_p2u {
|
||||
void __iomem *base;
|
||||
bool skip_sz_protection_en; /* Needed to support two retimers */
|
||||
struct tegra_p2u_of_data *of_data;
|
||||
};
|
||||
|
||||
static inline void p2u_writel(struct tegra_p2u *phy, const u32 value,
|
||||
@@ -44,6 +56,12 @@ static int tegra_p2u_power_on(struct phy *x)
|
||||
struct tegra_p2u *phy = phy_get_drvdata(x);
|
||||
u32 val;
|
||||
|
||||
if (phy->skip_sz_protection_en) {
|
||||
val = p2u_readl(phy, P2U_CONTROL_CMN);
|
||||
val |= P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN;
|
||||
p2u_writel(phy, val, P2U_CONTROL_CMN);
|
||||
}
|
||||
|
||||
val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3);
|
||||
val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
|
||||
val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
|
||||
@@ -58,6 +76,12 @@ static int tegra_p2u_power_on(struct phy *x)
|
||||
val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;
|
||||
p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME);
|
||||
|
||||
if (phy->of_data->one_dir_search) {
|
||||
val = p2u_readl(phy, P2U_DIR_SEARCH_CTRL);
|
||||
val &= ~P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE;
|
||||
p2u_writel(phy, val, P2U_DIR_SEARCH_CTRL);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -77,10 +101,19 @@ static int tegra_p2u_probe(struct platform_device *pdev)
|
||||
if (!phy)
|
||||
return -ENOMEM;
|
||||
|
||||
phy->of_data =
|
||||
(struct tegra_p2u_of_data *)of_device_get_match_data(dev);
|
||||
if (!phy->of_data)
|
||||
return -EINVAL;
|
||||
|
||||
phy->base = devm_platform_ioremap_resource_byname(pdev, "ctl");
|
||||
if (IS_ERR(phy->base))
|
||||
return PTR_ERR(phy->base);
|
||||
|
||||
phy->skip_sz_protection_en =
|
||||
of_property_read_bool(dev->of_node,
|
||||
"nvidia,skip-sz-protect-en");
|
||||
|
||||
platform_set_drvdata(pdev, phy);
|
||||
|
||||
generic_phy = devm_phy_create(dev, NULL, &ops);
|
||||
@@ -96,9 +129,22 @@ static int tegra_p2u_probe(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct tegra_p2u_of_data tegra194_p2u_of_data = {
|
||||
.one_dir_search = false,
|
||||
};
|
||||
|
||||
static const struct tegra_p2u_of_data tegra234_p2u_of_data = {
|
||||
.one_dir_search = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_p2u_id_table[] = {
|
||||
{
|
||||
.compatible = "nvidia,tegra194-p2u",
|
||||
.data = &tegra194_p2u_of_data,
|
||||
},
|
||||
{
|
||||
.compatible = "nvidia,tegra234-p2u",
|
||||
.data = &tegra234_p2u_of_data,
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
@@ -253,6 +253,14 @@ enum wiz_type {
|
||||
AM64_WIZ_10G,
|
||||
};
|
||||
|
||||
struct wiz_data {
|
||||
enum wiz_type type;
|
||||
const struct reg_field *refclk_dig_sel;
|
||||
const struct reg_field *pma_cmn_refclk1_dig_div;
|
||||
const struct wiz_clk_mux_sel *clk_mux_sel;
|
||||
unsigned int clk_div_sel_num;
|
||||
};
|
||||
|
||||
#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
|
||||
#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
|
||||
|
||||
@@ -290,6 +298,7 @@ struct wiz {
|
||||
struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
|
||||
struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
|
||||
struct clk_onecell_data clk_data;
|
||||
const struct wiz_data *data;
|
||||
};
|
||||
|
||||
static int wiz_reset(struct wiz *wiz)
|
||||
@@ -409,6 +418,7 @@ static int wiz_regfield_init(struct wiz *wiz)
|
||||
struct regmap *regmap = wiz->regmap;
|
||||
int num_lanes = wiz->num_lanes;
|
||||
struct device *dev = wiz->dev;
|
||||
const struct wiz_data *data = wiz->data;
|
||||
int i;
|
||||
|
||||
wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
|
||||
@@ -445,10 +455,10 @@ static int wiz_regfield_init(struct wiz *wiz)
|
||||
return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]);
|
||||
}
|
||||
|
||||
if (wiz->type == J721E_WIZ_16G) {
|
||||
if (data->pma_cmn_refclk1_dig_div) {
|
||||
wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =
|
||||
devm_regmap_field_alloc(dev, regmap,
|
||||
pma_cmn_refclk1_dig_div);
|
||||
*data->pma_cmn_refclk1_dig_div);
|
||||
if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {
|
||||
dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
|
||||
return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);
|
||||
@@ -469,15 +479,8 @@ static int wiz_regfield_init(struct wiz *wiz)
|
||||
return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
|
||||
}
|
||||
|
||||
if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
|
||||
wiz->mux_sel_field[REFCLK_DIG] =
|
||||
devm_regmap_field_alloc(dev, regmap,
|
||||
refclk_dig_sel_10g);
|
||||
else
|
||||
wiz->mux_sel_field[REFCLK_DIG] =
|
||||
devm_regmap_field_alloc(dev, regmap,
|
||||
refclk_dig_sel_16g);
|
||||
|
||||
wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, regmap,
|
||||
*data->refclk_dig_sel);
|
||||
if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
|
||||
dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
|
||||
return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
|
||||
@@ -1078,15 +1081,37 @@ static const struct regmap_config wiz_regmap_config = {
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct wiz_data j721e_16g_data = {
|
||||
.type = J721E_WIZ_16G,
|
||||
.refclk_dig_sel = &refclk_dig_sel_16g,
|
||||
.pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
|
||||
.clk_mux_sel = clk_mux_sel_16g,
|
||||
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
|
||||
};
|
||||
|
||||
static struct wiz_data j721e_10g_data = {
|
||||
.type = J721E_WIZ_10G,
|
||||
.refclk_dig_sel = &refclk_dig_sel_10g,
|
||||
.clk_mux_sel = clk_mux_sel_10g,
|
||||
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
|
||||
};
|
||||
|
||||
static struct wiz_data am64_10g_data = {
|
||||
.type = AM64_WIZ_10G,
|
||||
.refclk_dig_sel = &refclk_dig_sel_10g,
|
||||
.clk_mux_sel = clk_mux_sel_10g,
|
||||
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
|
||||
};
|
||||
|
||||
static const struct of_device_id wiz_id_table[] = {
|
||||
{
|
||||
.compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
|
||||
.compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
|
||||
},
|
||||
{
|
||||
.compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
|
||||
.compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data,
|
||||
},
|
||||
{
|
||||
.compatible = "ti,am64-wiz-10g", .data = (void *)AM64_WIZ_10G
|
||||
.compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
|
||||
},
|
||||
{}
|
||||
};
|
||||
@@ -1145,12 +1170,20 @@ static int wiz_probe(struct platform_device *pdev)
|
||||
struct wiz *wiz;
|
||||
int ret, val, i;
|
||||
u32 num_lanes;
|
||||
const struct wiz_data *data;
|
||||
|
||||
wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
|
||||
if (!wiz)
|
||||
return -ENOMEM;
|
||||
|
||||
wiz->type = (enum wiz_type)of_device_get_match_data(dev);
|
||||
data = of_device_get_match_data(dev);
|
||||
if (!data) {
|
||||
dev_err(dev, "NULL device data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
wiz->data = data;
|
||||
wiz->type = data->type;
|
||||
|
||||
child_node = of_get_child_by_name(node, "serdes");
|
||||
if (!child_node) {
|
||||
@@ -1226,17 +1259,9 @@ static int wiz_probe(struct platform_device *pdev)
|
||||
wiz->dev = dev;
|
||||
wiz->regmap = regmap;
|
||||
wiz->num_lanes = num_lanes;
|
||||
if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
|
||||
wiz->clk_mux_sel = clk_mux_sel_10g;
|
||||
else
|
||||
wiz->clk_mux_sel = clk_mux_sel_16g;
|
||||
|
||||
wiz->clk_mux_sel = data->clk_mux_sel;
|
||||
wiz->clk_div_sel = clk_div_sel;
|
||||
|
||||
if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
|
||||
wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
|
||||
else
|
||||
wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
|
||||
wiz->clk_div_sel_num = data->clk_div_sel_num;
|
||||
|
||||
platform_set_drvdata(pdev, wiz);
|
||||
|
||||
|
||||
@@ -105,8 +105,9 @@ static int tusb1210_power_on(struct phy *phy)
|
||||
msleep(TUSB1210_RESET_TIME_MS);
|
||||
|
||||
/* Restore the optional eye diagram optimization value */
|
||||
return tusb1210_ulpi_write(tusb, TUSB1210_VENDOR_SPECIFIC2,
|
||||
tusb->vendor_specific2);
|
||||
tusb1210_ulpi_write(tusb, TUSB1210_VENDOR_SPECIFIC2, tusb->vendor_specific2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tusb1210_power_off(struct phy *phy)
|
||||
|
||||
Reference in New Issue
Block a user