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Revert "drm/amdgpu/gfx9: put queue resets behind a debug option"

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[ Upstream commit 32f00289698189b813942f37626218fd473e7302 ]

This reverts commit 7c1a2d8aba.

Extended validation has completed successfully, so enable
these features by default.

Acked-by: Jiadong Zhu <Jiadong.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Jonathan Kim <jonathan.kim@amd.com>
Cc: Jiadong Zhu <Jiadong.Zhu@amd.com>
Stable-dep-of: 86bde64cb795 ("drm/amdgpu: fix gpu recovery disable with per queue reset")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Alex Deucher
2024-10-15 15:55:10 -04:00
committed by Greg Kroah-Hartman
parent 495497c6e7
commit fd3ea4d549
3 changed files with 0 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
-4
View File
@@ -1133,10 +1133,6 @@ uint64_t kgd_gfx_v9_hqd_get_pq_addr(struct amdgpu_device *adev,
uint32_t low, high;
uint64_t queue_addr = 0;
if (!adev->debug_exp_resets &&
!adev->gfx.num_gfx_rings)
return 0;
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
amdgpu_gfx_rlc_enter_safe_mode(adev, inst);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
-4
View File
@@ -7251,10 +7251,6 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring,
unsigned long flags;
int i, r;
if (!adev->debug_exp_resets &&
!adev->gfx.num_gfx_rings)
return -EINVAL;
if (amdgpu_sriov_vf(adev))
return -EINVAL;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
-6
View File
@@ -3062,9 +3062,6 @@ static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring,
struct amdgpu_device *adev = ring->adev;
uint32_t value = 0;
if (!adev->debug_exp_resets)
return;
value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
@@ -3580,9 +3577,6 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
unsigned long flags;
int r;
if (!adev->debug_exp_resets)
return -EINVAL;
if (amdgpu_sriov_vf(adev))
return -EINVAL;