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clk: renesas: rcar-gen4: Remove unused fixed PLL clock types

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All users of the fixed default PLL2/3/4/6 clock types have been
converted to fixed or variable fractional PLL clock types.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/c0229eb3518444f61173c6fb83bdcedb058dd079.1721648548.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven
2024-07-22 13:50:34 +02:00
parent ccdf745bd1
commit f7444f0fde
2 changed files with 0 additions and 24 deletions
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drivers/clk/renesas/rcar-gen4-cpg.c
-20
View File
@@ -440,31 +440,11 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
div = cpg_pll_config->pll1_div;
break;
case CLK_TYPE_GEN4_PLL2:
mult = cpg_pll_config->pll2_mult;
div = cpg_pll_config->pll2_div;
break;
case CLK_TYPE_GEN4_PLL3:
mult = cpg_pll_config->pll3_mult;
div = cpg_pll_config->pll3_div;
break;
case CLK_TYPE_GEN4_PLL4:
mult = cpg_pll_config->pll4_mult;
div = cpg_pll_config->pll4_div;
break;
case CLK_TYPE_GEN4_PLL5:
mult = cpg_pll_config->pll5_mult;
div = cpg_pll_config->pll5_div;
break;
case CLK_TYPE_GEN4_PLL6:
mult = cpg_pll_config->pll6_mult;
div = cpg_pll_config->pll6_div;
break;
case CLK_TYPE_GEN4_PLL2X_3X:
value = readl(base + core->offset);
mult = (FIELD_GET(CPG_PLLxCR_STC, value) + 1) * 2;
drivers/clk/renesas/rcar-gen4-cpg.h
-4
View File
@@ -12,12 +12,8 @@
enum rcar_gen4_clk_types {
CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
CLK_TYPE_GEN4_PLL1,
CLK_TYPE_GEN4_PLL2,
CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
CLK_TYPE_GEN4_PLL3,
CLK_TYPE_GEN4_PLL4,
CLK_TYPE_GEN4_PLL5,
CLK_TYPE_GEN4_PLL6,
CLK_TYPE_GEN4_PLL_F8_25, /* Fixed fractional 8.25 PLL */
CLK_TYPE_GEN4_PLL_V8_25, /* Variable fractional 8.25 PLL */
CLK_TYPE_GEN4_PLL_F9_24, /* Fixed fractional 9.24 PLL */