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Merge db77b8502a ("Merge tag 'asm-generic-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic") into android-mainline

Browse Source 
Steps on the way to 6.3-rc1

Change-Id: I38c77192e21fa74aaab32a5726ca7f1077715b2c
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman
2023-03-02 11:33:10 +00:00
parent e6c45b356a db77b8502a
commit f6950e4e1f
1837 changed files with 78134 additions and 173068 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/admin-guide/media/davinci-vpbe.rst
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.. SPDX-License-Identifier: GPL-2.0
The VPBE V4L2 driver design
===========================
Functional partitioning
-----------------------
Consists of the following:
1. V4L2 display driver
Implements creation of video2 and video3 device nodes and
provides v4l2 device interface to manage VID0 and VID1 layers.
2. Display controller
Loads up VENC, OSD and external encoders such as ths8200. It provides
a set of API calls to V4L2 drivers to set the output/standards
in the VENC or external sub devices. It also provides
a device object to access the services from OSD subdevice
using sub device ops. The connection of external encoders to VENC LCD
controller port is done at init time based on default output and standard
selection or at run time when application change the output through
V4L2 IOCTLs.
When connected to an external encoder, vpbe controller is also responsible
for setting up the interface between VENC and external encoders based on
board specific settings (specified in board-xxx-evm.c). This allows
interfacing external encoders such as ths8200. The setup_if_config()
is implemented for this as well as configure_venc() (part of the next patch)
API to set timings in VENC for a specific display resolution. As of this
patch series, the interconnection and enabling and setting of the external
encoders is not present, and would be a part of the next patch series.
3. VENC subdevice module
Responsible for setting outputs provided through internal DACs and also
setting timings at LCD controller port when external encoders are connected
at the port or LCD panel timings required. When external encoder/LCD panel
is connected, the timings for a specific standard/preset is retrieved from
the board specific table and the values are used to set the timings in
venc using non-standard timing mode.
Support LCD Panel displays using the VENC. For example to support a Logic
PD display, it requires setting up the LCD controller port with a set of
timings for the resolution supported and setting the dot clock. So we could
add the available outputs as a board specific entry (i.e add the "LogicPD"
output name to board-xxx-evm.c). A table of timings for various LCDs
supported can be maintained in the board specific setup file to support
various LCD displays.As of this patch a basic driver is present, and this
support for external encoders and displays forms a part of the next
patch series.
4. OSD module
OSD module implements all OSD layer management and hardware specific
features. The VPBE module interacts with the OSD for enabling and
disabling appropriate features of the OSD.
Current status
--------------
A fully functional working version of the V4L2 driver is available. This
driver has been tested with NTSC and PAL standards and buffer streaming.
Documentation/admin-guide/media/platform-cardlist.rst
-1
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@@ -73,7 +73,6 @@ via-camera VIAFB camera controller
video-mux Video Multiplexer
vpif_display TI DaVinci VPIF V4L2-Display
vpif_capture TI DaVinci VPIF video capture
vpss TI DaVinci VPBE V4L2-Display
vsp1 Renesas VSP1 Video Processing Engine
xilinx-tpg Xilinx Video Test Pattern Generator
xilinx-video Xilinx Video IP (EXPERIMENTAL)
Documentation/admin-guide/media/v4l-drivers.rst
-1
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@@ -13,7 +13,6 @@ Video4Linux (V4L) driver-specific documentation
cafe_ccic
cpia2
cx88
davinci-vpbe
fimc
imx
imx7
Documentation/arm/index.rst
-1
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@@ -64,7 +64,6 @@ SoC-specific documents
sunxi
samsung/index
samsung-s3c24xx/index
sunxi/clocks
Documentation/arm/samsung-s3c24xx/cpufreq.rst
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.. SPDX-License-Identifier: GPL-2.0-only
=======================
S3C24XX CPUfreq support
=======================
Introduction
------------
The S3C24XX series support a number of power saving systems, such as
the ability to change the core, memory and peripheral operating
frequencies. The core control is exported via the CPUFreq driver
which has a number of different manual or automatic controls over the
rate the core is running at.
There are two forms of the driver depending on the specific CPU and
how the clocks are arranged. The first implementation used as single
PLL to feed the ARM, memory and peripherals via a series of dividers
and muxes and this is the implementation that is documented here. A
newer version where there is a separate PLL and clock divider for the
ARM core is available as a separate driver.
Layout
------
The code core manages the CPU specific drivers, any data that they
need to register and the interface to the generic drivers/cpufreq
system. Each CPU registers a driver to control the PLL, clock dividers
and anything else associated with it. Any board that wants to use this
framework needs to supply at least basic details of what is required.
The core registers with drivers/cpufreq at init time if all the data
necessary has been supplied.
CPU support
-----------
The support for each CPU depends on the facilities provided by the
SoC and the driver as each device has different PLL and clock chains
associated with it.
Slow Mode
---------
The SLOW mode where the PLL is turned off altogether and the
system is fed by the external crystal input is currently not
supported.
sysfs
-----
The core code exports extra information via sysfs in the directory
devices/system/cpu/cpu0/arch-freq.
Board Support
-------------
Each board that wants to use the cpufreq code must register some basic
information with the core driver to provide information about what the
board requires and any restrictions being placed on it.
The board needs to supply information about whether it needs the IO bank
timings changing, any maximum frequency limits and information about the
SDRAM refresh rate.
Document Author
---------------
Ben Dooks, Copyright 2009 Simtec Electronics
Documentation/arm/samsung-s3c24xx/eb2410itx.rst
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===================================
Simtec Electronics EB2410ITX (BAST)
===================================
http://www.simtec.co.uk/products/EB2410ITX/
Introduction
------------
The EB2410ITX is a S3C2410 based development board with a variety of
peripherals and expansion connectors. This board is also known by
the shortened name of Bast.
Configuration
-------------
To set the default configuration, use `make bast_defconfig` which
supports the commonly used features of this board.
Support
-------
Official support information can be found on the Simtec Electronics
website, at the product page http://www.simtec.co.uk/products/EB2410ITX/
Useful links:
- Resources Page http://www.simtec.co.uk/products/EB2410ITX/resources.html
- Board FAQ at http://www.simtec.co.uk/products/EB2410ITX/faq.html
- Bootloader info http://www.simtec.co.uk/products/SWABLE/resources.html
and FAQ http://www.simtec.co.uk/products/SWABLE/faq.html
MTD
---
The NAND and NOR support has been merged from the linux-mtd project.
Any problems, see http://www.linux-mtd.infradead.org/ for more
information or up-to-date versions of linux-mtd.
IDE
---
Both onboard IDE ports are supported, however there is no support for
changing speed of devices, PIO Mode 4 capable drives should be used.
Maintainers
-----------
This board is maintained by Simtec Electronics.
Copyright 2004 Ben Dooks, Simtec Electronics
Documentation/arm/samsung-s3c24xx/gpio.rst
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====================
S3C24XX GPIO Control
====================
Introduction
------------
The s3c2410 kernel provides an interface to configure and
manipulate the state of the GPIO pins, and find out other
information about them.
There are a number of conditions attached to the configuration
of the s3c2410 GPIO system, please read the Samsung provided
data-sheet/users manual to find out the complete list.
See Documentation/arm/samsung/gpio.rst for the core implementation.
GPIOLIB
-------
With the event of the GPIOLIB in drivers/gpio, support for some
of the GPIO functions such as reading and writing a pin will
be removed in favour of this common access method.
Once all the extant drivers have been converted, the functions
listed below will be removed (they may be marked as __deprecated
in the near future).
The following functions now either have a `s3c_` specific variant
or are merged into gpiolib. See the definitions in
arch/arm/mach-s3c/gpio-cfg.h:
- s3c2410_gpio_setpin() gpio_set_value() or gpio_direction_output()
- s3c2410_gpio_getpin() gpio_get_value() or gpio_direction_input()
- s3c2410_gpio_getirq() gpio_to_irq()
- s3c2410_gpio_cfgpin() s3c_gpio_cfgpin()
- s3c2410_gpio_getcfg() s3c_gpio_getcfg()
- s3c2410_gpio_pullup() s3c_gpio_setpull()
GPIOLIB conversion
------------------
If you need to convert your board or driver to use gpiolib from the phased
out s3c2410 API, then here are some notes on the process.
1) If your board is exclusively using an GPIO, say to control peripheral
power, then it will require to claim the gpio with gpio_request() before
it can use it.
It is recommended to check the return value, with at least WARN_ON()
during initialisation.
2) The s3c2410_gpio_cfgpin() can be directly replaced with s3c_gpio_cfgpin()
as they have the same arguments, and can either take the pin specific
values, or the more generic special-function-number arguments.
3) s3c2410_gpio_pullup() changes have the problem that while the
s3c2410_gpio_pullup(x, 1) can be easily translated to the
s3c_gpio_setpull(x, S3C_GPIO_PULL_NONE), the s3c2410_gpio_pullup(x, 0)
are not so easy.
The s3c2410_gpio_pullup(x, 0) case enables the pull-up (or in the case
of some of the devices, a pull-down) and as such the new API distinguishes
between the UP and DOWN case. There is currently no 'just turn on' setting
which may be required if this becomes a problem.
4) s3c2410_gpio_setpin() can be replaced by gpio_set_value(), the old call
does not implicitly configure the relevant gpio to output. The gpio
direction should be changed before using gpio_set_value().
5) s3c2410_gpio_getpin() is replaceable by gpio_get_value() if the pin
has been set to input. It is currently unknown what the behaviour is
when using gpio_get_value() on an output pin (s3c2410_gpio_getpin
would return the value the pin is supposed to be outputting).
6) s3c2410_gpio_getirq() should be directly replaceable with the
gpio_to_irq() call.
The s3c2410_gpio and `gpio_` calls have always operated on the same gpio
numberspace, so there is no problem with converting the gpio numbering
between the calls.
Headers
-------
See arch/arm/mach-s3c/regs-gpio-s3c24xx.h for the list
of GPIO pins, and the configuration values for them. This
is included by using #include <mach/regs-gpio.h>
PIN Numbers
-----------
Each pin has an unique number associated with it in regs-gpio.h,
e.g. S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
the GPIO functions which pin is to be used.
With the conversion to gpiolib, there is no longer a direct conversion
from gpio pin number to register base address as in earlier kernels. This
is due to the number space required for newer SoCs where the later
GPIOs are not contiguous.
Configuring a pin
-----------------
The following function allows the configuration of a given pin to
be changed.
void s3c_gpio_cfgpin(unsigned int pin, unsigned int function);
e.g.:
s3c_gpio_cfgpin(S3C2410_GPA(0), S3C_GPIO_SFN(1));
s3c_gpio_cfgpin(S3C2410_GPE(8), S3C_GPIO_SFN(2));
which would turn GPA(0) into the lowest Address line A0, and set
GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line.
Reading the current configuration
---------------------------------
The current configuration of a pin can be read by using standard
gpiolib function:
s3c_gpio_getcfg(unsigned int pin);
The return value will be from the same set of values which can be
passed to s3c_gpio_cfgpin().
Configuring a pull-up resistor
------------------------------
A large proportion of the GPIO pins on the S3C2410 can have weak
pull-up resistors enabled. This can be configured by the following
function:
void s3c_gpio_setpull(unsigned int pin, unsigned int to);
Where the to value is S3C_GPIO_PULL_NONE to set the pull-up off,
and S3C_GPIO_PULL_UP to enable the specified pull-up. Any other
values are currently undefined.
Getting and setting the state of a PIN
--------------------------------------
These calls are now implemented by the relevant gpiolib calls, convert
your board or driver to use gpiolib.
Getting the IRQ number associated with a PIN
--------------------------------------------
A standard gpiolib function can map the given pin number to an IRQ
number to pass to the IRQ system.
int gpio_to_irq(unsigned int pin);
Note, not all pins have an IRQ.
Author
-------
Ben Dooks, 03 October 2004
Copyright 2004 Ben Dooks, Simtec Electronics
Documentation/arm/samsung-s3c24xx/h1940.rst
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=============
HP IPAQ H1940
=============
http://www.handhelds.org/projects/h1940.html
Introduction
------------
The HP H1940 is a S3C2410 based handheld device, with
bluetooth connectivity.
Support
-------
A variety of information is available
handhelds.org project page:
http://www.handhelds.org/projects/h1940.html
handhelds.org wiki page:
http://handhelds.org/moin/moin.cgi/HpIpaqH1940
Herbert Pötzl pages:
http://vserver.13thfloor.at/H1940/
Maintainers
-----------
This project is being maintained and developed by a variety
of people, including Ben Dooks, Arnaud Patard, and Herbert Pötzl.
Thanks to the many others who have also provided support.
(c) 2005 Ben Dooks
Documentation/arm/samsung-s3c24xx/index.rst
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.. SPDX-License-Identifier: GPL-2.0
==========================
Samsung S3C24XX SoC Family
==========================
.. toctree::
:maxdepth: 1
h1940
gpio
cpufreq
suspend
usb-host
s3c2412
eb2410itx
nand
smdk2440
s3c2413
overview
Documentation/arm/samsung-s3c24xx/nand.rst
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====================
S3C24XX NAND Support
====================
Introduction
------------
Small Page NAND
---------------
The driver uses a 512 byte (1 page) ECC code for this setup. The
ECC code is not directly compatible with the default kernel ECC
code, so the driver enforces its own OOB layout and ECC parameters
Large Page NAND
---------------
The driver is capable of handling NAND flash with a 2KiB page
size, with support for hardware ECC generation and correction.
Unlike the 512byte page mode, the driver generates ECC data for
each 256 byte block in an 2KiB page. This means that more than
one error in a page can be rectified. It also means that the
OOB layout remains the default kernel layout for these flashes.
Document Author
---------------
Ben Dooks, Copyright 2007 Simtec Electronics
Documentation/arm/samsung-s3c24xx/overview.rst
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==========================
S3C24XX ARM Linux Overview
==========================
Introduction
------------
The Samsung S3C24XX range of ARM9 System-on-Chip CPUs are supported
by the 's3c2410' architecture of ARM Linux. Currently the S3C2410,
S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 and S3C2450 devices
are supported.
Support for the S3C2400 and S3C24A0 series was never completed and the
corresponding code has been removed after a while. If someone wishes to
revive this effort, partial support can be retrieved from earlier Linux
versions.
The S3C2416 and S3C2450 devices are very similar and S3C2450 support is
included under the arch/arm/mach-s3c directory. Note, while core
support for these SoCs is in, work on some of the extra peripherals
and extra interrupts is still ongoing.
Configuration
-------------
A generic S3C2410 configuration is provided, and can be used as the
default by `make s3c2410_defconfig`. This configuration has support
for all the machines, and the commonly used features on them.
Certain machines may have their own default configurations as well,
please check the machine specific documentation.
Layout
------
The core support files, register, kernel and paltform data are located in the
platform code contained in arch/arm/mach-s3c with headers in
arch/arm/mach-s3c/include
arch/arm/mach-s3c:
Files in here are either common to all the s3c24xx family,
or are common to only some of them with names to indicate this
status. The files that are not common to all are generally named
with the initial cpu they support in the series to ensure a short
name without any possibility of confusion with newer devices.
As an example, initially s3c244x would cover s3c2440 and s3c2442, but
with the s3c2443 which does not share many of the same drivers in
this directory, the name becomes invalid. We stick to s3c2440-<x>
to indicate a driver that is s3c2440 and s3c2442 compatible.
This does mean that to find the status of any given SoC, a number
of directories may need to be searched.
Machines
--------
The currently supported machines are as follows:
Simtec Electronics EB2410ITX (BAST)
A general purpose development board, see EB2410ITX.txt for further
details
Simtec Electronics IM2440D20 (Osiris)
CPU Module from Simtec Electronics, with a S3C2440A CPU, nand flash
and a PCMCIA controller.
Samsung SMDK2410
Samsung's own development board, geared for PDA work.
Samsung/Aiji SMDK2412
The S3C2412 version of the SMDK2440.
Samsung/Aiji SMDK2413
The S3C2412 version of the SMDK2440.
Samsung/Meritech SMDK2440
The S3C2440 compatible version of the SMDK2440, which has the
option of an S3C2440 or S3C2442 CPU module.
Thorcom VR1000
Custom embedded board
HP IPAQ 1940
Handheld (IPAQ), available in several varieties
HP iPAQ rx3715
S3C2440 based IPAQ, with a number of variations depending on
features shipped.
Acer N30
A S3C2410 based PDA from Acer. There is a Wiki page at
http://handhelds.org/moin/moin.cgi/AcerN30Documentation .
AML M5900
American Microsystems' M5900
Nex Vision Nexcoder
Nex Vision Otom
Two machines by Nex Vision
Adding New Machines
-------------------
The architecture has been designed to support as many machines as can
be configured for it in one kernel build, and any future additions
should keep this in mind before altering items outside of their own
machine files.
Machine definitions should be kept in arch/arm/mach-s3c,
and there are a number of examples that can be looked at.
Read the kernel patch submission policies as well as the
Documentation/arm directory before submitting patches. The
ARM kernel series is managed by Russell King, and has a patch system
located at http://www.arm.linux.org.uk/developer/patches/
as well as mailing lists that can be found from the same site.
As a courtesy, please notify <ben-linux@fluff.org> of any new
machines or other modifications.
Any large scale modifications, or new drivers should be discussed
on the ARM kernel mailing list (linux-arm-kernel) before being
attempted. See http://www.arm.linux.org.uk/mailinglists/ for the
mailing list information.
I2C
---
The hardware I2C core in the CPU is supported in single master
mode, and can be configured via platform data.
RTC
---
Support for the onboard RTC unit, including alarm function.
This has recently been upgraded to use the new RTC core,
and the module has been renamed to rtc-s3c to fit in with
the new rtc naming scheme.
Watchdog
--------
The onchip watchdog is available via the standard watchdog
interface.
NAND
----
The current kernels now have support for the s3c2410 NAND
controller. If there are any problems the latest linux-mtd
code can be found from http://www.linux-mtd.infradead.org/
For more information see Documentation/arm/samsung-s3c24xx/nand.rst
SD/MMC
------
The SD/MMC hardware pre S3C2443 is supported in the current
kernel, the driver is drivers/mmc/host/s3cmci.c and supports
1 and 4 bit SD or MMC cards.
The SDIO behaviour of this driver has not been fully tested. There is no
current support for hardware SDIO interrupts.
Serial
------
The s3c2410 serial driver provides support for the internal
serial ports. These devices appear as /dev/ttySAC0 through 3.
To create device nodes for these, use the following commands
mknod ttySAC0 c 204 64
mknod ttySAC1 c 204 65
mknod ttySAC2 c 204 66
GPIO
----
The core contains support for manipulating the GPIO, see the
documentation in GPIO.txt in the same directory as this file.
Newer kernels carry GPIOLIB, and support is being moved towards
this with some of the older support in line to be removed.
As of v2.6.34, the move towards using gpiolib support is almost
complete, and very little of the old calls are left.
See Documentation/arm/samsung-s3c24xx/gpio.rst for the S3C24XX specific
support and Documentation/arm/samsung/gpio.rst for the core Samsung
implementation.
Clock Management
----------------
The core provides the interface defined in the header file
include/asm-arm/hardware/clock.h, to allow control over the
various clock units
Suspend to RAM
--------------
For boards that provide support for suspend to RAM, the
system can be placed into low power suspend.
See Suspend.txt for more information.
SPI
---
SPI drivers are available for both the in-built hardware
(although there is no DMA support yet) and a generic
GPIO based solution.
LEDs
----
There is support for GPIO based LEDs via a platform driver
in the LED subsystem.
Platform Data
-------------
Whenever a device has platform specific data that is specified
on a per-machine basis, care should be taken to ensure the
following:
1) that default data is not left in the device to confuse the
driver if a machine does not set it at startup
2) the data should (if possible) be marked as __initdata,
to ensure that the data is thrown away if the machine is
not the one currently in use.
The best way of doing this is to make a function that
kmalloc()s an area of memory, and copies the __initdata
and then sets the relevant device's platform data. Making
the function `__init` takes care of ensuring it is discarded
with the rest of the initialisation code::
static __init void s3c24xx_xxx_set_platdata(struct xxx_data *pd)
{
struct s3c2410_xxx_mach_info *npd;
npd = kmalloc(sizeof(struct s3c2410_xxx_mach_info), GFP_KERNEL);
if (npd) {
memcpy(npd, pd, sizeof(struct s3c2410_xxx_mach_info));
s3c_device_xxx.dev.platform_data = npd;
} else {
printk(KERN_ERR "no memory for xxx platform data\n");
}
}
Note, since the code is marked as __init, it should not be
exported outside arch/arm/mach-s3c/, or exported to
modules via EXPORT_SYMBOL() and related functions.
Port Contributors
-----------------
Ben Dooks (BJD)
Vincent Sanders
Herbert Potzl
Arnaud Patard (RTP)
Roc Wu
Klaus Fetscher
Dimitry Andric
Shannon Holland
Guillaume Gourat (NexVision)
Christer Weinigel (wingel) (Acer N30)
Lucas Correia Villa Real (S3C2400 port)
Document Author
---------------
Ben Dooks, Copyright 2004-2006 Simtec Electronics
Documentation/arm/samsung-s3c24xx/s3c2412.rst
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==========================
S3C2412 ARM Linux Overview
==========================
Introduction
------------
The S3C2412 is part of the S3C24XX range of ARM9 System-on-Chip CPUs
from Samsung. This part has an ARM926-EJS core, capable of running up
to 266MHz (see data-sheet for more information)
Clock
-----
The core clock code provides a set of clocks to the drivers, and allows
for source selection and a number of other features.
Power
-----
No support for suspend/resume to RAM in the current system.
DMA
---
No current support for DMA.
GPIO
----
There is support for setting the GPIO to input/output/special function
and reading or writing to them.
UART
----
The UART hardware is similar to the S3C2440, and is supported by the
s3c2410 driver in the drivers/serial directory.
NAND
----
The NAND hardware is similar to the S3C2440, and is supported by the
s3c2410 driver in the drivers/mtd/nand/raw directory.
USB Host
--------
The USB hardware is similar to the S3C2410, with extended clock source
control. The OHCI portion is supported by the ohci-s3c2410 driver, and
the clock control selection is supported by the core clock code.
USB Device
----------
No current support in the kernel
IRQs
----
All the standard, and external interrupt sources are supported. The
extra sub-sources are not yet supported.
RTC
---
The RTC hardware is similar to the S3C2410, and is supported by the
s3c2410-rtc driver.
Watchdog
--------
The watchdog hardware is the same as the S3C2410, and is supported by
the s3c2410_wdt driver.
MMC/SD/SDIO
-----------
No current support for the MMC/SD/SDIO block.
IIC
---
The IIC hardware is the same as the S3C2410, and is supported by the
i2c-s3c24xx driver.
IIS
---
No current support for the IIS interface.
SPI
---
No current support for the SPI interfaces.
ATA
---
No current support for the on-board ATA block.
Document Author
---------------
Ben Dooks, Copyright 2006 Simtec Electronics
Documentation/arm/samsung-s3c24xx/s3c2413.rst
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==========================
S3C2413 ARM Linux Overview
==========================
Introduction
------------
The S3C2413 is an extended version of the S3C2412, with an camera
interface and mobile DDR memory support. See the S3C2412 support
documentation for more information.
Camera Interface
----------------
This block is currently not supported.
Document Author
---------------
Ben Dooks, Copyright 2006 Simtec Electronics
Documentation/arm/samsung-s3c24xx/smdk2440.rst
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=========================
Samsung/Meritech SMDK2440
=========================
Introduction
------------
The SMDK2440 is a two part evaluation board for the Samsung S3C2440
processor. It includes support for LCD, SmartMedia, Audio, SD and
10MBit Ethernet, and expansion headers for various signals, including
the camera and unused GPIO.
Configuration
-------------
To set the default configuration, use `make smdk2440_defconfig` which
will configure the common features of this board, or use
`make s3c2410_config` to include support for all s3c2410/s3c2440 machines
Support
-------
Ben Dooks' SMDK2440 site at http://www.fluff.org/ben/smdk2440/ which
includes linux based USB download tools.
Some of the h1940 patches that can be found from the H1940 project
site at http://www.handhelds.org/projects/h1940.html can also be
applied to this board.
Peripherals
-----------
There is no current support for any of the extra peripherals on the
base-board itself.
MTD
---
The NAND flash should be supported by the in kernel MTD NAND support,
NOR flash will be added later.
Maintainers
-----------
This board is being maintained by Ben Dooks, for more info, see
http://www.fluff.org/ben/smdk2440/
Many thanks to Dimitry Andric of TomTom for the loan of the SMDK2440,
and to Simtec Electronics for allowing me time to work on this.
(c) 2004 Ben Dooks
Documentation/arm/samsung-s3c24xx/suspend.rst
-137
View File
@@ -1,137 +0,0 @@
=======================
S3C24XX Suspend Support
=======================
Introduction
------------
The S3C24XX supports a low-power suspend mode, where the SDRAM is kept
in Self-Refresh mode, and all but the essential peripheral blocks are
powered down. For more information on how this works, please look
at the relevant CPU datasheet from Samsung.
Requirements
------------
1) A bootloader that can support the necessary resume operation
2) Support for at least 1 source for resume
3) CONFIG_PM enabled in the kernel
4) Any peripherals that are going to be powered down at the same
time require suspend/resume support.
Resuming
--------
The S3C2410 user manual defines the process of sending the CPU to
sleep and how it resumes. The default behaviour of the Linux code
is to set the GSTATUS3 register to the physical address of the
code to resume Linux operation.
GSTATUS4 is currently left alone by the sleep code, and is free to
use for any other purposes (for example, the EB2410ITX uses this to
save memory configuration in).
Machine Support
---------------
The machine specific functions must call the s3c_pm_init() function
to say that its bootloader is capable of resuming. This can be as
simple as adding the following to the machine's definition:
INITMACHINE(s3c_pm_init)
A board can do its own setup before calling s3c_pm_init, if it
needs to setup anything else for power management support.
There is currently no support for over-riding the default method of
saving the resume address, if your board requires it, then contact
the maintainer and discuss what is required.
Note, the original method of adding an late_initcall() is wrong,
and will end up initialising all compiled machines' pm init!
The following is an example of code used for testing wakeup from
an falling edge on IRQ_EINT0::
static irqreturn_t button_irq(int irq, void *pw)
{
return IRQ_HANDLED;
}
statuc void __init machine_init(void)
{
...
request_irq(IRQ_EINT0, button_irq, IRQF_TRIGGER_FALLING,
"button-irq-eint0", NULL);
enable_irq_wake(IRQ_EINT0);
s3c_pm_init();
}
Debugging
---------
There are several important things to remember when using PM suspend:
1) The uart drivers will disable the clocks to the UART blocks when
suspending, which means that use of printascii() or similar direct
access to the UARTs will cause the debug to stop.
2) While the pm code itself will attempt to re-enable the UART clocks,
care should be taken that any external clock sources that the UARTs
rely on are still enabled at that point.
3) If any debugging is placed in the resume path, then it must have the
relevant clocks and peripherals setup before use (ie, bootloader).
For example, if you transmit a character from the UART, the baud
rate and uart controls must be setup beforehand.
Configuration
-------------
The S3C2410 specific configuration in `System Type` defines various
aspects of how the S3C2410 suspend and resume support is configured
`S3C2410 PM Suspend debug`
This option prints messages to the serial console before and after
the actual suspend, giving detailed information on what is
happening
`S3C2410 PM Suspend Memory CRC`
Allows the entire memory to be checksummed before and after the
suspend to see if there has been any corruption of the contents.
Note, the time to calculate the CRC is dependent on the CPU speed
and the size of memory. For an 64Mbyte RAM area on an 200MHz
S3C2410, this can take approximately 4 seconds to complete.
This support requires the CRC32 function to be enabled.
`S3C2410 PM Suspend CRC Chunksize (KiB)`
Defines the size of memory each CRC chunk covers. A smaller value
will mean that the CRC data block will take more memory, but will
identify any faults with better precision
Document Author
---------------
Ben Dooks, Copyright 2004 Simtec Electronics
Documentation/arm/samsung-s3c24xx/usb-host.rst
-91
View File
@@ -1,91 +0,0 @@
========================
S3C24XX USB Host support
========================
Introduction
------------
This document details the S3C2410/S3C2440 in-built OHCI USB host support.
Configuration
-------------
Enable at least the following kernel options:
menuconfig::
Device Drivers --->
USB support --->
<*> Support for Host-side USB
<*> OHCI HCD support
.config:
- CONFIG_USB
- CONFIG_USB_OHCI_HCD
Once these options are configured, the standard set of USB device
drivers can be configured and used.
Board Support
-------------
The driver attaches to a platform device, which will need to be
added by the board specific support file in arch/arm/mach-s3c,
such as mach-bast.c or mach-smdk2410.c
The platform device's platform_data field is only needed if the
board implements extra power control or over-current monitoring.
The OHCI driver does not ensure the state of the S3C2410's MISCCTRL
register, so if both ports are to be used for the host, then it is
the board support file's responsibility to ensure that the second
port is configured to be connected to the OHCI core.
Platform Data
-------------
See include/linux/platform_data/usb-ohci-s3c2410.h for the
descriptions of the platform device data. An implementation
can be found in arch/arm/mach-s3c/simtec-usb.c .
The `struct s3c2410_hcd_info` contains a pair of functions
that get called to enable over-current detection, and to
control the port power status.
The ports are numbered 0 and 1.
power_control:
Called to enable or disable the power on the port.
enable_oc:
Called to enable or disable the over-current monitoring.
This should claim or release the resources being used to
check the power condition on the port, such as an IRQ.
report_oc:
The OHCI driver fills this field in for the over-current code
to call when there is a change to the over-current state on
an port. The ports argument is a bitmask of 1 bit per port,
with bit X being 1 for an over-current on port X.
The function s3c2410_usb_report_oc() has been provided to
ensure this is called correctly.
port[x]:
This is struct describes each port, 0 or 1. The platform driver
should set the flags field of each port to S3C_HCDFLG_USED if
the port is enabled.
Document Author
---------------
Ben Dooks, Copyright 2005 Simtec Electronics
Documentation/arm/samsung/gpio.rst
-8
View File
@@ -9,14 +9,6 @@ This outlines the Samsung GPIO implementation and the architecture
specific calls provided alongside the drivers/gpio core.
S3C24XX (Legacy)
----------------
See Documentation/arm/samsung-s3c24xx/gpio.rst for more information
about these devices. Their implementation has been brought into line
with the core samsung implementation described in this document.
GPIOLIB integration
-------------------
Documentation/arm/samsung/overview.rst
-13
View File
@@ -12,21 +12,10 @@ Introduction
The currently supported SoCs are:
- S3C24XX: See Documentation/arm/samsung-s3c24xx/overview.rst for full list
- S3C64XX: S3C6400 and S3C6410
- S5PC110 / S5PV210
S3C24XX Systems
---------------
There is still documentation in Documnetation/arm/Samsung-S3C24XX/ which
deals with the architecture and drivers specific to these devices.
See Documentation/arm/samsung-s3c24xx/overview.rst for more information
on the implementation details and specific support.
Configuration
-------------
@@ -51,8 +40,6 @@ Layout
specific information. It contains the base clock, GPIO and device definitions
to get the system running.
plat-s3c24xx is for s3c24xx specific builds, see the S3C24XX docs.
plat-s5p is for s5p specific builds, and contains common support for the
S5P specific systems. Not all S5Ps use all the features in this directory
due to differences in the hardware.
Documentation/devicetree/bindings/arm/altera.yaml
+1
View File
@@ -31,6 +31,7 @@ properties:
- description: Mercury+ AA1 boards
items:
- enum:
- enclustra,mercury-pe1
- google,chameleon-v3
- const: enclustra,mercury-aa1
- const: altr,socfpga-arria10
Documentation/devicetree/bindings/arm/amlogic.yaml
+3
View File
@@ -154,6 +154,7 @@ properties:
items:
- enum:
- khadas,vim3
- radxa,zero2
- const: amlogic,a311d
- const: amlogic,g12b
@@ -165,6 +166,7 @@ properties:
- azw,gtking-pro
- hardkernel,odroid-go-ultra
- hardkernel,odroid-n2
- hardkernel,odroid-n2l
- hardkernel,odroid-n2-plus
- khadas,vim3
- ugoos,am6
@@ -176,6 +178,7 @@ properties:
- enum:
- amediatech,x96-air
- amediatech,x96-air-gbit
- bananapi,bpi-m2-pro
- bananapi,bpi-m5
- cyx,a95xf3-air
- cyx,a95xf3-air-gbit
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+2
View File
@@ -78,6 +78,7 @@ properties:
- facebook,cloudripper-bmc
- facebook,elbert-bmc
- facebook,fuji-bmc
- facebook,greatlakes-bmc
- ibm,everest-bmc
- ibm,rainier-bmc
- ibm,tacoma-bmc
@@ -85,6 +86,7 @@ properties:
- jabil,rbp-bmc
- qcom,dc-scm-v1-bmc
- quanta,s6q-bmc
- ufispace,ncplite-bmc
- const: aspeed,ast2600
additionalProperties: true
Documentation/devicetree/bindings/arm/atmel-at91.yaml
+4 -2
View File
@@ -91,9 +91,11 @@ properties:
- const: atmel,sama5d2
- const: atmel,sama5
- description: SAM9X60-EK board
- description: Microchip SAM9X60 Evaluation Boards
items:
- const: microchip,sam9x60ek
- enum:
- microchip,sam9x60ek
- microchip,sam9x60-curiosity
- const: microchip,sam9x60
- const: atmel,at91sam9
Documentation/devicetree/bindings/arm/fsl.yaml
+90 -6
View File
@@ -88,12 +88,56 @@ properties:
items:
- enum:
- armadeus,imx28-apf28 # APF28 SoM
- armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board
- bluegiga,apx4devkit # Bluegiga APx4 SoM on dev board
- crystalfontz,cfa10036 # Crystalfontz CFA-10036 SoM
- eukrea,mbmx28lc
- fsl,imx28-evk
- i2se,duckbill
- i2se,duckbill-2
- karo,tx28 # Ka-Ro electronics TX28 module
- lwn,imx28-xea
- msr,m28cu3 # M28 SoM with custom base board
- schulercontrol,imx28-sps1
- technologic,imx28-ts4600
- const: fsl,imx28
- description: i.MX28 Aries M28 SoM Board
items:
- const: aries,m28
- const: denx,m28
- const: fsl,imx28
- description: i.MX28 Aries M28EVK Board
items:
- const: aries,m28evk
- const: denx,m28evk
- const: fsl,imx28
- description: i.MX28 Armadeus Systems APF28Dev Board
items:
- const: armadeus,imx28-apf28dev
- const: armadeus,imx28-apf28
- const: fsl,imx28
- description: i.MX28 Crystalfontz CFA-10036 based Boards
items:
- enum:
- crystalfontz,cfa10037
- crystalfontz,cfa10049
- crystalfontz,cfa10057
- crystalfontz,cfa10058
- const: crystalfontz,cfa10036
- const: fsl,imx28
- description: i.MX28 Crystalfontz CFA-10037 based Boards
items:
- enum:
- crystalfontz,cfa10055
- crystalfontz,cfa10056
- const: crystalfontz,cfa10037
- const: crystalfontz,cfa10036
- const: fsl,imx28
- description: i.MX28 Duckbill 2 based Boards
items:
- enum:
@@ -103,6 +147,19 @@ properties:
- const: i2se,duckbill-2
- const: fsl,imx28
- description: i.MX28 Eukrea Electromatique MBMX283LC Board
items:
- const: eukrea,mbmx283lc
- const: eukrea,mbmx28lc
- const: fsl,imx28
- description: i.MX28 Eukrea Electromatique MBMX287LC Board
items:
- const: eukrea,mbmx287lc
- const: eukrea,mbmx283lc
- const: eukrea,mbmx28lc
- const: fsl,imx28
- description: i.MX31 based Boards
items:
- enum:
@@ -173,6 +230,7 @@ properties:
- kiebackpeter,imx53-ddc # K+P imx53 DDC
- kiebackpeter,imx53-hsc # K+P imx53 HSC
- menlo,m53menlo # i.MX53 Menlo board
- starterkit,sk-imx53
- voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668
- const: fsl,imx53
@@ -644,6 +702,16 @@ properties:
- const: armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
- const: fsl,imx6ull
- description: i.MX6ULL DHCOM SoM based Boards
items:
- enum:
- dh,imx6ull-dhcom-drc02
- dh,imx6ull-dhcom-pdk2
- dh,imx6ull-dhcom-picoitx
- const: dh,imx6ull-dhcom-som # The DHCOR is soldered on the DHCOM
- const: dh,imx6ull-dhcor-som
- const: fsl,imx6ull
- description: i.MX6ULL PHYTEC phyBOARD-Segin
items:
- enum:
@@ -815,7 +883,6 @@ properties:
- enum:
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
- cloos,imx8mm-phg # i.MX8MM Cloos PHG Board
- dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC
- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
@@ -830,7 +897,6 @@ properties:
- innocomm,wb15-evk # i.MX8MM Innocomm EVK board with WB15 SoM
- kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM
- kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM
- menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
@@ -861,8 +927,10 @@ properties:
- description: Toradex Boards with Verdin iMX8M Mini Modules
items:
- enum:
- menlo,mx8menlo # Verdin iMX8M Mini Module on i.MX8MM Menlo board
- toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
- toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
- toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia
- const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
- const: fsl,imx8mm
@@ -872,6 +940,7 @@ properties:
- enum:
- toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
- toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
- toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia
- const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
- const: fsl,imx8mm
@@ -895,6 +964,7 @@ properties:
one compatible is needed.
items:
- enum:
- cloos,imx8mm-phg # i.MX8MM Cloos PHG Board
- tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx
- const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM
- const: fsl,imx8mm
@@ -931,10 +1001,11 @@ properties:
- description: i.MX8MP based Boards
items:
- enum:
- dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM
- dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit
- fsl,imx8mp-evk # i.MX8MP EVK Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- polyhex,imx8mp-debix # Polyhex Debix boards
- polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
@@ -947,6 +1018,12 @@ properties:
- const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM
- const: fsl,imx8mp
- description: i.MX8MP DHCOM based Boards
items:
- const: dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
- const: dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM
- const: fsl,imx8mp
- description: Engicam i.Core MX8M Plus SoM based boards
items:
- enum:
@@ -965,6 +1042,7 @@ properties:
- enum:
- toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
- toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
- toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia
- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
- const: fsl,imx8mp
@@ -974,6 +1052,7 @@ properties:
- enum:
- toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
- toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
- toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia
- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
- const: fsl,imx8mp
@@ -999,12 +1078,17 @@ properties:
- fsl,imx8mq-evk # i.MX8MQ EVK Board
- google,imx8mq-phanbell # Google Coral Edge TPU
- kontron,pitx-imx8m # Kontron pITX-imx8m Board
- mntre,reform2 # MNT Reform2 Laptop
- purism,librem5-devkit # Purism Librem5 devkit
- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
- const: fsl,imx8mq
- description: i.MX8MQ NITROGEN SoM based Boards
items:
- const: mntre,reform2 # MNT Reform2 Laptop
- const: boundary,imx8mq-nitrogen8m-som # i.MX8MQ NITROGEN SoM
- const: fsl,imx8mq
- description: Purism Librem5 phones
items:
- enum:
Documentation/devicetree/bindings/arm/mediatek.yaml
+4
View File
@@ -244,6 +244,10 @@ properties:
- enum:
- mediatek,mt8183-pumpkin
- const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8365-evk
- const: mediatek,mt8365
- items:
- enum:
- mediatek,mt8516-pumpkin
Documentation/devicetree/bindings/arm/qcom.yaml
+79
View File
@@ -35,6 +35,8 @@ description: |
mdm9615
msm8226
msm8916
msm8939
msm8953
msm8956
msm8974
msm8976
@@ -47,11 +49,13 @@ description: |
qru1000
sa8155p
sa8540p
sa8775p
sc7180
sc7280
sc8180x
sc8280xp
sda660
sdm450
sdm630
sdm632
sdm636
@@ -62,6 +66,7 @@ description: |
sdx65
sm4250
sm6115
sm6115p
sm6125
sm6350
sm6375
@@ -70,6 +75,7 @@ description: |
sm8250
sm8350
sm8450
sm8550
The 'board' element must be one of the following strings:
@@ -84,6 +90,7 @@ description: |
liquid
mtp
qrd
ride
sbc
x100
@@ -160,6 +167,12 @@ properties:
- samsung,s3ve3g
- const: qcom,msm8226
- items:
- enum:
- sony,kanuti-tulip
- square,apq8039-t2
- const: qcom,msm8939
- items:
- enum:
- sony,kugo-row
@@ -194,8 +207,10 @@ properties:
- items:
- enum:
- acer,a1-724
- alcatel,idol347
- asus,z00l
- gplus,fl8005a
- huawei,g7
- longcheer,l8910
- samsung,a3u-eur
@@ -203,8 +218,13 @@ properties:
- samsung,e5
- samsung,e7
- samsung,grandmax
- samsung,gt510
- samsung,gt58
- samsung,j5
- samsung,j5x
- samsung,serranove
- thwc,uf896
- thwc,ufi001c
- wingtech,wt88047
- const: qcom,msm8916
@@ -213,6 +233,15 @@ properties:
- const: qcom,msm8916-v1-qrd/9-v1
- const: qcom,msm8916
- items:
- enum:
- motorola,potter
- xiaomi,daisy
- xiaomi,mido
- xiaomi,tissot
- xiaomi,vince
- const: qcom,msm8953
- items:
- enum:
- lg,bullhead
@@ -627,6 +656,12 @@ properties:
- const: google,hoglin
- const: qcom,sc7280
- description: Qualcomm Technologies, Inc. sc7280 CRD Pro platform (newest rev)
items:
- const: google,zoglin-sku1536
- const: google,hoglin-sku1536
- const: qcom,sc7280
- description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform
items:
- const: qcom,sc7280-idp
@@ -679,6 +714,18 @@ properties:
- const: google,zombie-sku512
- const: qcom,sc7280
- description: Google Zombie with NVMe (newest rev)
items:
- const: google,zombie-sku2
- const: google,zombie-sku3
- const: google,zombie-sku515
- const: qcom,sc7280
- description: Google Zombie with LTE and NVMe (newest rev)
items:
- const: google,zombie-sku514
- const: qcom,sc7280
- items:
- enum:
- lenovo,flex-5g
@@ -693,6 +740,11 @@ properties:
- qcom,sc8280xp-qrd
- const: qcom,sc8280xp
- items:
- enum:
- motorola,ali
- const: qcom,sdm450
- items:
- enum:
- sony,discovery-row
@@ -709,6 +761,7 @@ properties:
- items:
- enum:
- fairphone,fp3
- motorola,ocean
- const: qcom,sdm632
- items:
@@ -762,6 +815,11 @@ properties:
- qcom,sa8540p-ride
- const: qcom,sa8540p
- items:
- enum:
- qcom,sa8775p-ride
- const: qcom,sa8775p
- items:
- enum:
- google,cheza
@@ -790,6 +848,12 @@ properties:
- oneplus,billie2
- const: qcom,sm4250
- items:
- enum:
- lenovo,j606f
- const: qcom,sm6115p
- const: qcom,sm6115
- items:
- enum:
- sony,pdx201
@@ -826,6 +890,7 @@ properties:
- qcom,sm8250-mtp
- sony,pdx203-generic
- sony,pdx206-generic
- xiaomi,elish
- const: qcom,sm8250
- items:
@@ -845,6 +910,11 @@ properties:
- sony,pdx224
- const: qcom,sm8450
- items:
- enum:
- qcom,sm8550-mtp
- const: qcom,sm8550
# Board compatibles go above
qcom,msm-id:
@@ -922,15 +992,22 @@ allOf:
- qcom,apq8026
- qcom,apq8094
- qcom,apq8096
- qcom,msm8939
- qcom,msm8953
- qcom,msm8956
- qcom,msm8992
- qcom,msm8994
- qcom,msm8996
- qcom,msm8998
- qcom,sdm450
- qcom,sdm630
- qcom,sdm632
- qcom,sdm636
- qcom,sdm845
- qcom,sdx55
- qcom,sdx65
- qcom,sm4250
- qcom,sm6115
- qcom,sm6125
- qcom,sm6350
- qcom,sm7225
@@ -954,6 +1031,8 @@ allOf:
- oneplus,dumpling
- oneplus,enchilada
- oneplus,fajita
- oneplus,oneplus3
- oneplus,oneplus3t
then:
properties:
qcom,board-id:
Documentation/devicetree/bindings/arm/rockchip.yaml
+61
View File
@@ -90,11 +90,33 @@ properties:
- const: chipspark,rayeager-px2
- const: rockchip,rk3066a
- description: Edgeble Neural Compute Module 2(Neu2) SoM based boards
items:
- const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board
- const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM
- const: rockchip,rv1126
- description: Edgeble Neural Compute Module 6(Neu6) Model A SoM based boards
items:
- const: edgeble,neural-compute-module-6a-io # Edgeble Neural Compute Module 6A IO Board
- const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
- const: rockchip,rk3588
- description: Elgin RV1108 R1
items:
- const: elgin,rv1108-r1
- const: rockchip,rv1108
- description: EmbedFire LubanCat 1
items:
- const: embedfire,lubancat-1
- const: rockchip,rk3566
- description: EmbedFire LubanCat 2
items:
- const: embedfire,lubancat-2
- const: rockchip,rk3568
- description: Engicam PX30.Core C.TOUCH 2.0
items:
- const: engicam,px30-core-ctouch2
@@ -599,6 +621,20 @@ properties:
- const: pine64,soquartz
- const: rockchip,rk3566
- description: Radxa Compute Module 3(CM3)
items:
- enum:
- radxa,cm3-io
- const: radxa,cm3
- const: rockchip,rk3566
- description: Radxa CM3 Industrial
items:
- enum:
- radxa,e25
- const: radxa,cm3i
- const: rockchip,rk3568
- description: Radxa Rock
items:
- const: radxa,rock
@@ -652,6 +688,16 @@ properties:
- const: radxa,rock3a
- const: rockchip,rk3568
- description: Radxa ROCK 5 Model A
items:
- const: radxa,rock-5a
- const: rockchip,rk3588s
- description: Radxa ROCK 5 Model B
items:
- const: radxa,rock-5b
- const: rockchip,rk3588
- description: Rikomagic MK808 v1
items:
- const: rikomagic,mk808
@@ -689,6 +735,11 @@ properties:
- const: rockchip,rk3036-evb
- const: rockchip,rk3036
- description: Rockchip RK3128 Evaluation board
items:
- const: rockchip,rk3128-evb
- const: rockchip,rk3128
- description: Rockchip RK3228 Evaluation board
items:
- const: rockchip,rk3228-evb
@@ -736,6 +787,11 @@ properties:
- const: rockchip,rk3399-sapphire-excavator
- const: rockchip,rk3399
- description: Rockchip RK3588 Evaluation board
items:
- const: rockchip,rk3588-evb1-v10
- const: rockchip,rk3588
- description: Rockchip RV1108 Evaluation board
items:
- const: rockchip,rv1108-evb
@@ -761,6 +817,11 @@ properties:
- const: tronsmart,orion-r68-meta
- const: rockchip,rk3368
- description: Xunlong Orange Pi R1 Plus
items:
- const: xunlong,orangepi-r1-plus
- const: rockchip,rk3328
- description: Zkmagic A95X Z2
items:
- const: zkmagic,a95x-z2
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
+2
View File
@@ -27,6 +27,7 @@ select:
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- rockchip,rk3588-pmu
- rockchip,rv1126-pmu
required:
- compatible
@@ -43,6 +44,7 @@ properties:
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- rockchip,rk3588-pmu
- rockchip,rv1126-pmu
- const: syscon
- const: simple-mfd
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+1
View File
@@ -171,6 +171,7 @@ properties:
- hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite
- hardkernel,odroid-xu4 # Hardkernel Odroid XU4
- hardkernel,odroid-hc1 # Hardkernel Odroid HC1
- samsung,k3g # Samsung Galaxy S5 (SM-G900H)
- const: samsung,exynos5800
- const: samsung,exynos5
Documentation/devicetree/bindings/arm/ti/k3.yaml
+15
View File
@@ -38,10 +38,17 @@ properties:
- ti,am642-sk
- const: ti,am642
- description: K3 AM642 SoC PHYTEC phyBOARD-Electra
items:
- const: phytec,am642-phyboard-electra-rdk
- const: phytec,am64-phycore-som
- const: ti,am642
- description: K3 AM654 SoC
items:
- enum:
- siemens,iot2050-advanced
- siemens,iot2050-advanced-m2
- siemens,iot2050-advanced-pg2
- siemens,iot2050-basic
- siemens,iot2050-basic-pg2
@@ -69,9 +76,17 @@ properties:
- description: K3 J721s2 SoC
items:
- enum:
- ti,am68-sk
- ti,j721s2-evm
- const: ti,j721s2
- description: K3 J784s4 SoC
items:
- enum:
- ti,am69-sk
- ti,j784s4-evm
- const: ti,j784s4
additionalProperties: true
...
Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml
+2 -2
View File
@@ -40,10 +40,10 @@ properties:
maxItems: 1
"#address-cells":
const: 1
enum: [ 1, 2 ]
"#size-cells":
const: 1
enum: [ 1, 2 ]
ranges: true
Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
+51
View File
@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
maintainers:
- Melody Olvera <quic_molvera@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on QDU1000 and QRU1000
See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h
properties:
compatible:
const: qcom,qdu1000-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 0 Phy Auxiliary clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,qdu1000-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>,
<&usb3_phy_wrapper_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml
+49
View File
@@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6350-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM6350
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM6350.
See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h
properties:
compatible:
const: qcom,sm6350-camcc
clocks:
items:
- description: Board XO source
reg:
maxItems: 1
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@ad00000 {
compatible = "qcom,sm6350-camcc";
reg = <0x0ad00000 0x16000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
+105
View File
@@ -0,0 +1,105 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller for SM8550
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8550.
See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
properties:
compatible:
enum:
- qcom,sm8550-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8550-dispcc";
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<&dp0_phy 0>,
<&dp0_phy 1>,
<&dp1_phy 0>,
<&dp1_phy 1>,
<&dp2_phy 0>,
<&dp2_phy 1>,
<&dp3_phy 0>,
<&dp3_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8550_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+55
View File
@@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm TCSR Clock Controller on SM8550
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm TCSR clock control module provides the clocks, resets and
power domains on SM8550
See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
properties:
compatible:
items:
- const: qcom,sm8550-tcsr
- const: syscon
clocks:
items:
- description: TCXO pad clock
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@1fc0000 {
compatible = "qcom,sm8550-tcsr", "syscon";
reg = <0x1fc0000 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt
-49
View File
@@ -1,49 +0,0 @@
* Samsung S3C2410 Clock Controller
The S3C2410 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to the s3c2410,
s3c2440 and s3c2442 SoCs in the s3c24x family.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
- "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
- "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2410.h header and can be used in device
tree sources.
External clocks:
The xti clock used as input for the plls is generated outside the SoC. It is
expected that is are defined using standard clock bindings with a
clock-output-names value of "xti".
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2410-clock";
reg = <0x4c000000 0x20>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2440-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
};
Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt
-49
View File
@@ -1,49 +0,0 @@
* Samsung S3C2412 Clock Controller
The S3C2412 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to the s3c2412
and s3c2413 SoCs in the s3c24x family.
Required Properties:
- compatible: should be "samsung,s3c2412-clock"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2412.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xti" - crystal input - required,
- "ext" - external clock source - optional,
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2412-clock";
reg = <0x4c000000 0x20>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2412-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
};
Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt
-55
View File
@@ -1,55 +0,0 @@
* Samsung S3C2443 Clock Controller
The S3C2443 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to all SoCs in
the s3c24x family starting with the s3c2443.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
- "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
- "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2443.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xti" - crystal input - required,
- "ext" - external clock source - optional,
- "ext_i2s" - external I2S clock - optional,
- "ext_uart" - external uart clock - optional,
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2416-clock";
reg = <0x4c000000 0x40>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2440-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
+2 -2
View File
@@ -20,10 +20,10 @@ properties:
- nvidia,tegra194-display
'#address-cells':
const: 1
enum: [ 1, 2 ]
'#size-cells':
const: 1
enum: [ 1, 2 ]
reg:
maxItems: 1
Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml
+70
View File
@@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000
maintainers:
- Georgi Djakov <djakov@kernel.org>
- Odelu Kukatla <quic_okukatla@quicinc.com>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
properties:
compatible:
enum:
- qcom,qdu1000-clk-virt
- qcom,qdu1000-gem-noc
- qcom,qdu1000-mc-virt
- qcom,qdu1000-system-noc
'#interconnect-cells': true
reg:
maxItems: 1
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,qdu1000-clk-virt
- qcom,qdu1000-mc-virt
then:
properties:
reg: false
else:
required:
- reg
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
system_noc: interconnect@1640000 {
compatible = "qcom,qdu1000-system-noc";
reg = <0x1640000 0x45080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
clk_virt: interconnect-0 {
compatible = "qcom,qdu1000-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
Documentation/devicetree/bindings/interconnect/qcom,sm8550-rpmh.yaml
+139
View File
@@ -0,0 +1,139 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550
maintainers:
- Abel Vesa <abel.vesa@linaro.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
properties:
compatible:
enum:
- qcom,sm8550-aggre1-noc
- qcom,sm8550-aggre2-noc
- qcom,sm8550-clk-virt
- qcom,sm8550-cnoc-main
- qcom,sm8550-config-noc
- qcom,sm8550-gem-noc
- qcom,sm8550-lpass-ag-noc
- qcom,sm8550-lpass-lpiaon-noc
- qcom,sm8550-lpass-lpicx-noc
- qcom,sm8550-mc-virt
- qcom,sm8550-mmss-noc
- qcom,sm8550-nsp-noc
- qcom,sm8550-pcie-anoc
- qcom,sm8550-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-clk-virt
- qcom,sm8550-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-pcie-anoc
then:
properties:
clocks:
items:
- description: aggre-NOC PCIe AXI clock
- description: cfg-NOC PCIe a-NOC AHB clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre USB3 PRIM AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-aggre2-noc
then:
properties:
clocks:
items:
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-aggre1-noc
- qcom,sm8550-aggre2-noc
- qcom,sm8550-pcie-anoc
then:
required:
- clocks
else:
properties:
clocks: false
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
clk_virt: interconnect-0 {
compatible = "qcom,sm8550-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8550-aggre1-noc";
reg = <0x016e0000 0x14400>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
-53
View File
@@ -1,53 +0,0 @@
Samsung S3C24XX Interrupt Controllers
The S3C24XX SoCs contain a custom set of interrupt controllers providing a
varying number of interrupt sources. The set consists of a main- and sub-
controller and on newer SoCs even a second main controller.
Required properties:
- compatible: Compatible property value should be "samsung,s3c2410-irq"
for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
- reg: Physical base address of the controller and length of memory mapped
region.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 4 and interrupt descriptor shall
have the following format:
<ctrl_num parent_irq ctrl_irq type>
ctrl_num contains the controller to use:
- 0 ... main controller
- 1 ... sub controller
- 2 ... second main controller on s3c2416 and s3c2450
parent_irq contains the parent bit in the main controller and will be
ignored in main controllers
ctrl_irq contains the interrupt bit of the controller
type contains the trigger type to use
Example:
interrupt-controller@4a000000 {
compatible = "samsung,s3c2410-irq";
reg = <0x4a000000 0x100>;
interrupt-controller;
#interrupt-cells=<4>;
};
[...]
serial@50000000 {
compatible = "samsung,s3c2410-uart";
reg = <0x50000000 0x4000>;
interrupt-parent = <&subintc>;
interrupts = <1 28 0 4>, <1 28 1 4>;
};
rtc@57000000 {
compatible = "samsung,s3c2410-rtc";
reg = <0x57000000 0x100>;
interrupt-parent = <&intc>;
interrupts = <0 30 0 3>, <0 8 0 3>;
};
Documentation/devicetree/bindings/mfd/syscon.yaml
-6
View File
@@ -64,12 +64,6 @@ properties:
- rockchip,rk3568-qos
- rockchip,rk3588-qos
- rockchip,rv1126-qos
- samsung,exynos3-sysreg
- samsung,exynos4-sysreg
- samsung,exynos5-sysreg
- samsung,exynos5433-sysreg
- samsung,exynos850-sysreg
- samsung,exynosautov9-sysreg
- const: syscon
Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt
-42
View File
@@ -1,42 +0,0 @@
* Samsung's S3C24XX MMC/SD/SDIO controller device tree bindings
Samsung's S3C24XX MMC/SD/SDIO controller is used as a connectivity interface
with external MMC, SD and SDIO storage mediums.
This file documents differences between the core mmc properties described by
mmc.txt and the properties used by the Samsung S3C24XX MMC/SD/SDIO controller
implementation.
Required SoC Specific Properties:
- compatible: should be one of the following
- "samsung,s3c2410-sdi": for controllers compatible with s3c2410
- "samsung,s3c2412-sdi": for controllers compatible with s3c2412
- "samsung,s3c2440-sdi": for controllers compatible with s3c2440
- reg: register location and length
- interrupts: mmc controller interrupt
- clocks: Should reference the controller clock
- clock-names: Should contain "sdi"
Required Board Specific Properties:
- pinctrl-0: Should specify pin control groups used for this controller.
- pinctrl-names: Should contain only one value - "default".
Optional Properties:
- bus-width: number of data lines (see mmc.txt)
- cd-gpios: gpio for card detection (see mmc.txt)
- wp-gpios: gpio for write protection (see mmc.txt)
Example:
mmc0: mmc@5a000000 {
compatible = "samsung,s3c2440-sdi";
pinctrl-names = "default";
pinctrl-0 = <&sdi_pins>;
reg = <0x5a000000 0x100000>;
interrupts = <0 0 21 3>;
clocks = <&clocks PCLK_SDI>;
clock-names = "sdi";
bus-width = <4>;
cd-gpios = <&gpg 8 GPIO_ACTIVE_LOW>;
wp-gpios = <&gph 8 GPIO_ACTIVE_LOW>;
};
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml → Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
+1 -1
View File
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
$id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip USB2.0 phy with inno IP block
Documentation/devicetree/bindings/phy/rockchip,rk3288-dp-phy.yaml
+41
View File
@@ -0,0 +1,41 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip specific extensions to the Analogix Display Port PHY
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
const: rockchip,rk3288-dp-phy
clocks:
maxItems: 1
clock-names:
const: 24m
"#phy-cells":
const: 0
required:
- compatible
- clocks
- clock-names
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3288-cru.h>
edp-phy {
compatible = "rockchip,rk3288-dp-phy";
clocks = <&cru SCLK_EDP_24M>;
clock-names = "24m";
#phy-cells = <0>;
};
Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
-26
View File
@@ -1,26 +0,0 @@
Rockchip specific extensions to the Analogix Display Port PHY
------------------------------------
Required properties:
- compatible : should be one of the following supported values:
- "rockchip.rk3288-dp-phy"
- clocks: from common clock binding: handle to dp clock.
of memory mapped region.
- clock-names: from common clock binding:
Required elements: "24m"
- #phy-cells : from the generic PHY bindings, must be 0;
Example:
grf: syscon@ff770000 {
compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
...
edp_phy: edp-phy {
compatible = "rockchip,rk3288-dp-phy";
clocks = <&cru SCLK_EDP_24M>;
clock-names = "24m";
#phy-cells = <0>;
};
};
Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml
+14 -5
View File
@@ -23,11 +23,16 @@ description: |
properties:
compatible:
enum:
- fsl,imx6q-gpc
- fsl,imx6qp-gpc
- fsl,imx6sl-gpc
- fsl,imx6sx-gpc
oneOf:
- enum:
- fsl,imx6q-gpc
- items:
- enum:
- fsl,imx6qp-gpc
- fsl,imx6sl-gpc
- fsl,imx6sx-gpc
- fsl,imx6ul-gpc
- const: fsl,imx6q-gpc
reg:
maxItems: 1
@@ -35,6 +40,10 @@ properties:
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 3
clocks:
maxItems: 1
Documentation/devicetree/bindings/riscv/microchip.yaml
+1
View File
@@ -27,6 +27,7 @@ properties:
- items:
- enum:
- aldec,tysom-m-mpfs250t-rev2
- aries,m100pfsevp
- microchip,mpfs-sev-kit
- sundance,polarberry
Documentation/devicetree/bindings/riscv/starfive.yaml
+6
View File
@@ -24,6 +24,12 @@ properties:
- starfive,visionfive-v1
- const: starfive,jh7100
- items:
- enum:
- starfive,visionfive-2-v1.2a
- starfive,visionfive-2-v1.3b
- const: starfive,jh7110
additionalProperties: true
...
Documentation/devicetree/bindings/riscv/sunxi.yaml
+69
View File
@@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/sunxi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner RISC-V SoC-based boards
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Jernej Skrabec <jernej.skrabec@gmail.com>
- Samuel Holland <samuel@sholland.org>
description:
Allwinner RISC-V SoC-based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Dongshan Nezha STU SoM
items:
- const: 100ask,dongshan-nezha-stu
- const: allwinner,sun20i-d1
- description: D1 Nezha board
items:
- const: allwinner,d1-nezha
- const: allwinner,sun20i-d1
- description: ClockworkPi R-01 SoM and v3.14 board
items:
- const: clockwork,r-01-clockworkpi-v3.14
- const: allwinner,sun20i-d1
- description: ClockworkPi R-01 SoM, v3.14 board, and DevTerm expansion
items:
- const: clockwork,r-01-devterm-v3.14
- const: clockwork,r-01-clockworkpi-v3.14
- const: allwinner,sun20i-d1
- description: Lichee RV SoM
items:
- const: sipeed,lichee-rv
- const: allwinner,sun20i-d1
- description: Carrier boards for the Lichee RV SoM
items:
- enum:
- sipeed,lichee-rv-86-panel-480p
- sipeed,lichee-rv-86-panel-720p
- sipeed,lichee-rv-dock
- const: sipeed,lichee-rv
- const: allwinner,sun20i-d1
- description: MangoPi MQ board
items:
- const: widora,mangopi-mq
- const: allwinner,sun20i-d1s
- description: MangoPi MQ Pro board
items:
- const: widora,mangopi-mq-pro
- const: allwinner,sun20i-d1
additionalProperties: true
...
Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml
+57
View File
@@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx-iomuxc-gpr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IOMUX Controller General Purpose Registers
maintainers:
- Peng Fan <peng.fan@nxp.com>
description:
i.MX Processors have an IOMUXC General Purpose Register group for
various System Settings
properties:
compatible:
oneOf:
- items:
- const: fsl,imx8mq-iomuxc-gpr
- const: syscon
- const: simple-mfd
- items:
- enum:
- fsl,imx8mm-iomuxc-gpr
- fsl,imx8mn-iomuxc-gpr
- fsl,imx8mp-iomuxc-gpr
- const: syscon
reg:
maxItems: 1
mux-controller:
type: object
$ref: /schemas/mux/reg-mux.yaml
additionalProperties: false
required:
- compatible
- reg
examples:
# Pinmux controller node
- |
iomuxc_gpr: syscon@30340000 {
compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd";
reg = <0x30340000 0x10000>;
mux: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
};
};
...
Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
+4
View File
@@ -39,6 +39,9 @@ properties:
- const: pcie
- const: pcie-phy
'#clock-cells':
const: 0
clocks:
minItems: 2
maxItems: 2
@@ -85,4 +88,5 @@ examples:
power-domain-names = "bus", "usb", "usb-phy1",
"usb-phy2", "pcie", "pcie-phy";
#power-domain-cells = <1>;
#clock-cells = <0>;
};
Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml
+56
View File
@@ -0,0 +1,56 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/renesas/renesas,rzv2m-pwc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/V2M External Power Sequence Controller (PWC)
description: |+
The PWC IP found in the RZ/V2M family of chips comes with the below
capabilities
- external power supply on/off sequence generation
- on/off signal generation for the LPDDR4 core power supply (LPVDD)
- key input signals processing
- general-purpose output pins
maintainers:
- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
properties:
compatible:
items:
- enum:
- renesas,r9a09g011-pwc # RZ/V2M
- renesas,r9a09g055-pwc # RZ/V2MA
- const: renesas,rzv2m-pwc
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
renesas,rzv2m-pwc-power:
description: The PWC is used to control the system power supplies.
type: boolean
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
additionalProperties: false
examples:
- |
pwc: pwc@a3700000 {
compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc";
reg = <0xa3700000 0x800>;
gpio-controller;
#gpio-cells = <2>;
renesas,rzv2m-pwc-power;
};
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+9 -3
View File
@@ -20,6 +20,11 @@ properties:
- rockchip,rk3568-pipe-grf
- rockchip,rk3568-pipe-phy-grf
- rockchip,rk3568-usb2phy-grf
- rockchip,rk3588-bigcore0-grf
- rockchip,rk3588-bigcore1-grf
- rockchip,rk3588-ioc
- rockchip,rk3588-php-grf
- rockchip,rk3588-sys-grf
- rockchip,rk3588-pcie3-phy-grf
- rockchip,rk3588-pcie3-pipe-grf
- rockchip,rv1108-usbgrf
@@ -92,8 +97,9 @@ allOf:
then:
properties:
edp-phy:
description:
Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
type: object
$ref: /schemas/phy/rockchip,rk3288-dp-phy.yaml#
unevaluatedProperties: false
- if:
properties:
@@ -200,7 +206,7 @@ allOf:
"usb2phy@[0-9a-f]+$":
type: object
$ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#"
$ref: /schemas/phy/rockchip,inno-usb2phy.yaml#
unevaluatedProperties: false
Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
+57 -14
View File
@@ -31,20 +31,28 @@ select:
properties:
compatible:
items:
- enum:
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4412-pmu
- samsung,exynos5250-pmu
- samsung,exynos5260-pmu
- samsung,exynos5410-pmu
- samsung,exynos5420-pmu
- samsung,exynos5433-pmu
- samsung,exynos7-pmu
- samsung,exynos850-pmu
- samsung-s5pv210-pmu
- const: syscon
oneOf:
- items:
- enum:
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4412-pmu
- samsung,exynos5250-pmu
- samsung,exynos5260-pmu
- samsung,exynos5410-pmu
- samsung,exynos5420-pmu
- samsung,exynos5433-pmu
- samsung,exynos7-pmu
- samsung,exynos850-pmu
- samsung-s5pv210-pmu
- const: syscon
- items:
- enum:
- samsung,exynos5250-pmu
- samsung,exynos5420-pmu
- samsung,exynos5433-pmu
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
@@ -64,6 +72,10 @@ properties:
minItems: 1
maxItems: 32
dp-phy:
$ref: /schemas/phy/samsung,dp-video-phy.yaml
unevaluatedProperties: false
interrupt-controller:
description:
Some PMUs are capable of behaving as an interrupt controller (mostly
@@ -74,6 +86,10 @@ properties:
Must be identical to the that of the parent interrupt controller.
const: 3
mipi-phy:
$ref: /schemas/phy/samsung,mipi-video-phy.yaml
unevaluatedProperties: false
reboot-mode:
$ref: /schemas/power/reset/syscon-reboot-mode.yaml
type: object
@@ -117,6 +133,23 @@ allOf:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5250-pmu
- samsung,exynos5420-pmu
- samsung,exynos5433-pmu
then:
properties:
dp-phy: true
mipi-phy: true
else:
properties:
dp-phy: false
mipi-phy: false
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
@@ -130,4 +163,14 @@ examples:
#clock-cells = <1>;
clock-names = "clkout16";
clocks = <&clock CLK_FIN_PLL>;
dp-phy {
compatible = "samsung,exynos5250-dp-video-phy";
#phy-cells = <0>;
};
mipi-phy {
compatible = "samsung,s5pv210-mipi-video-phy";
#phy-cells = <1>;
};
};
Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
+87
View File
@@ -0,0 +1,87 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/samsung/samsung,exynos-sysreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC series System Registers (SYSREG)
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
oneOf:
- items:
- enum:
- samsung,exynos3-sysreg
- samsung,exynos4-sysreg
- samsung,exynos5-sysreg
- tesla,fsd-cam-sysreg
- tesla,fsd-fsys0-sysreg
- tesla,fsd-fsys1-sysreg
- tesla,fsd-peric-sysreg
- const: syscon
- items:
- enum:
- samsung,exynos5433-cam0-sysreg
- samsung,exynos5433-cam1-sysreg
- samsung,exynos5433-disp-sysreg
- samsung,exynos5433-fsys-sysreg
- const: samsung,exynos5433-sysreg
- const: syscon
- items:
- enum:
- samsung,exynos5433-sysreg
- samsung,exynos850-sysreg
- samsung,exynosautov9-sysreg
- const: syscon
deprecated: true
- items:
- enum:
- samsung,exynos850-cmgp-sysreg
- samsung,exynos850-peri-sysreg
- const: samsung,exynos850-sysreg
- const: syscon
- items:
- enum:
- samsung,exynosautov9-fsys2-sysreg
- samsung,exynosautov9-peric0-sysreg
- samsung,exynosautov9-peric1-sysreg
- const: samsung,exynosautov9-sysreg
- const: syscon
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos850-cmgp-sysreg
- samsung,exynos850-peri-sysreg
- samsung,exynos850-sysreg
then:
required:
- clocks
else:
properties:
clocks: false
additionalProperties: false
examples:
- |
system-controller@10010000 {
compatible = "samsung,exynos4-sysreg", "syscon";
reg = <0x10010000 0x400>;
};
Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml
+2 -2
View File
@@ -50,10 +50,10 @@ properties:
maxItems: 1
"#address-cells":
const: 1
enum: [ 1, 2 ]
"#size-cells":
const: 1
enum: [ 1, 2 ]
ranges: true
Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml
+2 -2
View File
@@ -34,10 +34,10 @@ properties:
maxItems: 1
"#address-cells":
const: 1
enum: [ 1, 2 ]
"#size-cells":
const: 1
enum: [ 1, 2 ]
ranges: true
Documentation/devicetree/bindings/vendor-prefixes.yaml
+20
View File
@@ -69,6 +69,8 @@ patternProperties:
description: Annapurna Labs
"^alcatel,.*":
description: Alcatel
"^aldec,.*":
description: Aldec, Inc.
"^alfa-network,.*":
description: ALFA Network Inc.
"^allegro,.*":
@@ -264,6 +266,8 @@ patternProperties:
description: Cirrus Logic, Inc.
"^cisco,.*":
description: Cisco Systems, Inc.
"^clockwork,.*":
description: Clockwork Tech LLC
"^cloos,.*":
description: Carl Cloos Schweisstechnik GmbH.
"^cloudengines,.*":
@@ -374,6 +378,8 @@ patternProperties:
description: EBV Elektronik
"^eckelmann,.*":
description: Eckelmann AG
"^edgeble,.*":
description: Edgeble AI Technologies Pvt. Ltd.
"^edimax,.*":
description: EDIMAX Technology Co., Ltd
"^edt,.*":
@@ -396,6 +402,8 @@ patternProperties:
description: Elimo Engineering Ltd.
"^elpida,.*":
description: Elpida Memory, Inc.
"^embedfire,.*":
description: Dongguan EmbedFire Electronic Technology Co., Ltd.
"^embest,.*":
description: Shenzhen Embest Technology Co., Ltd.
"^emlid,.*":
@@ -512,6 +520,8 @@ patternProperties:
description: Shenzhen Huiding Technology Co., Ltd.
"^google,.*":
description: Google, Inc.
"^gplus,.*":
description: GPLUS
"^grinn,.*":
description: Grinn
"^grmn,.*":
@@ -1025,6 +1035,8 @@ patternProperties:
description: PocketBook International SA
"^polaroid,.*":
description: Polaroid Corporation
"^polyhex,.*":
description: Polyhex Technology Co. Ltd.
"^portwell,.*":
description: Portwell Inc.
"^poslab,.*":
@@ -1246,6 +1258,8 @@ patternProperties:
description: Starry Electronic Technology (ShenZhen) Co., LTD
"^startek,.*":
description: Startek
"^starterkit,.*":
description: Starterkit
"^ste,.*":
description: ST-Ericsson
deprecated: true
@@ -1319,6 +1333,8 @@ patternProperties:
description: thingy.jp
"^thundercomm,.*":
description: Thundercomm Technology Co., Ltd.
"^thwc,.*":
description: Shenzhen Tong Heng Wei Chuang Technology Co., Ltd.
"^ti,.*":
description: Texas Instruments
"^tianma,.*":
@@ -1372,6 +1388,8 @@ patternProperties:
description: uCRobotics
"^udoo,.*":
description: Udoo
"^ufispace,.*":
description: Ufi Space Co., Ltd.
"^ugoos,.*":
description: Ugoos Industrial Co., Ltd.
"^uniwest,.*":
@@ -1444,6 +1462,8 @@ patternProperties:
description: Shenzhen whwave Electronics, Inc.
"^wi2wi,.*":
description: Wi2Wi, Inc.
"^widora,.*":
description: Beijing Widora Technology Co., Ltd.
"^wiligear,.*":
description: Wiligear, Ltd.
"^willsemi,.*":
Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst
-39
View File
@@ -1,39 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0
The VPBE V4L2 driver design
===========================
File partitioning
-----------------
V4L2 display device driver
drivers/media/platform/ti/davinci/vpbe_display.c
drivers/media/platform/ti/davinci/vpbe_display.h
VPBE display controller
drivers/media/platform/ti/davinci/vpbe.c
drivers/media/platform/ti/davinci/vpbe.h
VPBE venc sub device driver
drivers/media/platform/ti/davinci/vpbe_venc.c
drivers/media/platform/ti/davinci/vpbe_venc.h
drivers/media/platform/ti/davinci/vpbe_venc_regs.h
VPBE osd driver
drivers/media/platform/ti/davinci/vpbe_osd.c
drivers/media/platform/ti/davinci/vpbe_osd.h
drivers/media/platform/ti/davinci/vpbe_osd_regs.h
To be done
----------
vpbe display controller
- Add support for external encoders.
- add support for selecting external encoder as default at probe time.
vpbe venc sub device
- add timings for supporting ths8200
- add support for LogicPD LCD.
FB drivers
- Add support for fbdev drivers.- Ready and part of subsequent patches.
Documentation/driver-api/media/drivers/index.rst
-1
View File
@@ -16,7 +16,6 @@ Video4Linux (V4L) drivers
cpia2_devel
cx2341x-devel
cx88-devel
davinci-vpbe-devel
fimc-devel
pvrusb2
pxa_camera
Documentation/power/power_supply_class.rst
+2 -2
View File
@@ -40,8 +40,8 @@ kind of power supply, and can process/present them to a user in consistent
manner. Results for different power supplies and machines are also directly
comparable.
See drivers/power/supply/ds2760_battery.c and drivers/power/supply/pda_power.c
for the example how to declare and handle attributes.
See drivers/power/supply/ds2760_battery.c for the example how to declare
and handle attributes.
Units
Documentation/userspace-api/ioctl/ioctl-number.rst
-1
View File
@@ -201,7 +201,6 @@ Code Seq# Include File Comments
'V' all linux/videodev2.h conflict!
'V' C0 linux/ivtvfb.h conflict!
'V' C0 linux/ivtv.h conflict!
'V' C0 media/davinci/vpfe_capture.h conflict!
'V' C0 media/si4713.h conflict!
'W' 00-1F linux/watchdog.h conflict!
'W' 00-1F linux/wanrouter.h conflict! (pre 3.9)
MAINTAINERS
+6 -200
View File
@@ -1851,21 +1851,6 @@ F: include/dt-bindings/reset/actions,*
F: include/linux/soc/actions/
N: owl
ARM/ADS SPHERE MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/AFEB9260 MACHINE SUPPORT
M: Sergey Lapin <slapin@ossfans.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/AJECO 1ARM MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/Allwinner SoC Clock Support
M: Emilio López <emilio@elopez.com.ar>
S: Maintained
@@ -1886,7 +1871,7 @@ F: drivers/pinctrl/sunxi/
F: drivers/soc/sunxi/
N: allwinner
N: sun[x456789]i
N: sun50i
N: sun[25]0i
ARM/Amlogic Meson SoC CLOCK FRAMEWORK
M: Neil Armstrong <neil.armstrong@linaro.org>
@@ -2056,11 +2041,6 @@ F: arch/arm/boot/dts/ecx-*.dts*
F: arch/arm/boot/dts/highbank.dts
F: arch/arm/mach-highbank/
ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT
M: Krzysztof Halasa <khalasa@piap.pl>
S: Maintained
F: arch/arm/mach-cns3xxx/
ARM/CAVIUM THUNDER NETWORK DRIVER
M: Sunil Goutham <sgoutham@marvell.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -2089,8 +2069,8 @@ M: Hartley Sweeten <hsweeten@visionengravers.com>
M: Alexander Sverdlin <alexander.sverdlin@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/boot/compressed/misc-ep93xx.h
F: arch/arm/mach-ep93xx/
F: arch/arm/mach-ep93xx/include/mach/
ARM/CLKDEV SUPPORT
M: Russell King <linux@armlinux.org.uk>
@@ -2106,11 +2086,6 @@ S: Maintained
F: arch/arm/boot/dts/cx92755*
N: digicolor
ARM/CONTEC MICRO9 MACHINE SUPPORT
M: Hubert Feurstein <hubert.feurstein@contec.at>
S: Maintained
F: arch/arm/mach-ep93xx/micro9.c
ARM/CORESIGHT FRAMEWORK AND DRIVERS
M: Mathieu Poirier <mathieu.poirier@linaro.org>
M: Suzuki K Poulose <suzuki.poulose@arm.com>
@@ -2137,10 +2112,6 @@ F: tools/perf/arch/arm/util/pmu.c
F: tools/perf/util/cs-etm-decoder/*
F: tools/perf/util/cs-etm.*
ARM/CORGI MACHINE SUPPORT
M: Richard Purdie <rpurdie@rpsys.net>
S: Maintained
ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
M: Hans Ulli Kroll <ulli.kroll@googlemail.com>
M: Linus Walleij <linus.walleij@linaro.org>
@@ -2180,12 +2151,6 @@ F: include/dt-bindings/bus/moxtet.h
F: include/linux/armada-37xx-rwtm-mailbox.h
F: include/linux/moxtet.h
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
M: Robert Jarzmik <robert.jarzmik@free.fr>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-pxa/ezx.c
ARM/FARADAY FA526 PORT
M: Hans Ulli Kroll <ulli.kroll@googlemail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -2238,25 +2203,11 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
F: arch/arm/boot/dts/vf*
F: arch/arm/mach-imx/*vf610*
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/GUMSTIX MACHINE SUPPORT
M: Steve Sakoman <sakoman@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/H4700 (HP IPAQ HX4700) MACHINE SUPPORT
M: Philipp Zabel <philipp.zabel@gmail.com>
M: Paul Parsons <lost.distance@yahoo.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-pxa/hx4700.c
F: arch/arm/mach-pxa/include/mach/hx4700.h
F: sound/soc/pxa/hx4700.c
ARM/HISILICON SOC SUPPORT
M: Wei Xu <xuwei5@hisilicon.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -2299,27 +2250,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/boot/dts/omap3-igep*
ARM/INCOME PXA270 SUPPORT
M: Marek Vasut <marek.vasut@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-pxa/colibri-pxa270-income.c
ARM/INTEL IOP32X ARM ARCHITECTURE
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IQ81342EX MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IXDP2850 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IXP4XX ARM ARCHITECTURE
M: Linus Walleij <linusw@kernel.org>
M: Imre Kaloz <kaloz@openwrt.org>
@@ -2352,22 +2282,12 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/IP FABRICS DOUBLE ESPRESSO MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/LG1K ARCHITECTURE
M: Chanho Min <chanho.min@lge.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/dts/lg/
ARM/LOGICPD PXA270 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/LPC18XX ARCHITECTURE
M: Vladimir Zapolskiy <vz@mleia.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -2394,10 +2314,6 @@ F: drivers/usb/host/ohci-nxp.c
F: drivers/watchdog/pnx4008_wdt.c
N: lpc32xx
ARM/MAGICIAN MACHINE SUPPORT
M: Philipp Zabel <philipp.zabel@gmail.com>
S: Maintained
ARM/Marvell Dove/MV78xx0/Orion SOC support
M: Andrew Lunn <andrew@lunn.ch>
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
@@ -2529,12 +2445,6 @@ F: arch/arm/boot/dts/milbeaut*
F: arch/arm/mach-milbeaut/
N: milbeaut
ARM/MIOA701 MACHINE SUPPORT
M: Robert Jarzmik <robert.jarzmik@free.fr>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-pxa/mioa701.c
ARM/MStar/Sigmastar Armv7 SoC support
M: Daniel Palmer <daniel@thingy.jp>
M: Romain Perier <romain.perier@gmail.com>
@@ -2555,10 +2465,6 @@ F: drivers/watchdog/msc313e_wdt.c
F: include/dt-bindings/clock/mstar-*
F: include/dt-bindings/gpio/msc313-gpio.h
ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT
M: Michael Petchkovsky <mkpetch@internode.on.net>
S: Maintained
ARM/NOMADIK/Ux500 ARCHITECTURES
M: Linus Walleij <linus.walleij@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -2614,6 +2520,7 @@ S: Maintained
W: https://github.com/neuschaefer/wpcm450/wiki
F: Documentation/devicetree/bindings/*/*wpcm*
F: arch/arm/boot/dts/nuvoton-wpcm450*
F: arch/arm/configs/wpcm450_defconfig
F: arch/arm/mach-npcm/wpcm450.c
F: drivers/*/*/*wpcm*
F: drivers/*/*wpcm*
@@ -2627,13 +2534,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/dts/freescale/s32g*.dts*
ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT
L: openmoko-kernel@lists.openmoko.org (subscribers-only)
S: Orphan
W: http://wiki.openmoko.org/wiki/Neo_FreeRunner
F: arch/arm/mach-s3c/gta02.h
F: arch/arm/mach-s3c/mach-gta02.c
ARM/Orion SoC/Technologic Systems TS-78xx platform support
M: Alexander Clouter <alex@digriz.org.uk>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -2651,43 +2551,6 @@ F: arch/arm/mach-oxnas/
F: drivers/power/reset/oxnas-restart.c
N: oxnas
ARM/PALM TREO SUPPORT
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Orphan
F: arch/arm/mach-pxa/palmtreo.*
ARM/PALMTX,PALMT5,PALMLD,PALMTE2,PALMTC SUPPORT
M: Marek Vasut <marek.vasut@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
W: http://hackndev.com
F: arch/arm/mach-pxa/include/mach/palmld.h
F: arch/arm/mach-pxa/include/mach/palmtc.h
F: arch/arm/mach-pxa/include/mach/palmtx.h
F: arch/arm/mach-pxa/palmld.c
F: arch/arm/mach-pxa/palmt5.*
F: arch/arm/mach-pxa/palmtc.c
F: arch/arm/mach-pxa/palmte2.*
F: arch/arm/mach-pxa/palmtx.c
ARM/PALMZ72 SUPPORT
M: Sergey Lapin <slapin@ossfans.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
W: http://hackndev.com
F: arch/arm/mach-pxa/palmz72.*
ARM/PLEB SUPPORT
M: Peter Chubb <pleb@gelato.unsw.edu.au>
S: Maintained
W: http://www.disy.cse.unsw.edu.au/Hardware/PLEB
ARM/PT DIGITAL BOARD PORT
M: Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
W: http://www.armlinux.org.uk/
ARM/QUALCOMM SUPPORT
M: Andy Gross <agross@kernel.org>
M: Bjorn Andersson <andersson@kernel.org>
@@ -2731,11 +2594,6 @@ F: include/dt-bindings/*/qcom*
F: include/linux/*/qcom*
F: include/linux/soc/qcom/
ARM/RADISYS ENP2611 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/RDA MICRO ARCHITECTURE
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -2811,7 +2669,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml
F: arch/arm/boot/dts/rk3*
F: arch/arm/boot/dts/rv1108*
F: arch/arm/boot/dts/rv11*
F: arch/arm/mach-rockchip/
F: drivers/*/*/*rockchip*
F: drivers/*/*rockchip*
@@ -2856,7 +2714,6 @@ F: include/linux/platform_data/*s3c*
F: include/linux/serial_s3c.h
F: include/linux/soc/samsung/
N: exynos
N: s3c2410
N: s3c64xx
N: s5pv210
@@ -3014,7 +2871,7 @@ M: linux-fsd@tesla.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-samsung-soc@vger.kernel.org
S: Maintained
F: arch/arm64/boot/dts/tesla*
F: arch/arm64/boot/dts/tesla/
ARM/TETON BGA MACHINE SUPPORT
M: "Mark F. Brown" <mark.brown314@gmail.com>
@@ -3067,16 +2924,6 @@ F: arch/arm64/boot/dts/ti/Makefile
F: arch/arm64/boot/dts/ti/k3-*
F: include/dt-bindings/pinctrl/k3.h
ARM/THECUS N2100 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/TOSA MACHINE SUPPORT
M: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
M: Dirk Opfer <dirk@opfer-online.de>
S: Maintained
ARM/TOSHIBA VISCONTI ARCHITECTURE
M: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -3133,7 +2980,7 @@ S: Maintained
F: */*/*/vexpress*
F: */*/vexpress*
F: arch/arm/boot/dts/vexpress*
F: arch/arm/mach-vexpress/
F: arch/arm/mach-versatile/
F: arch/arm64/boot/dts/arm/
F: drivers/clk/versatile/clk-vexpress-osc.c
F: drivers/clocksource/timer-versatile.c
@@ -3146,13 +2993,6 @@ S: Maintained
W: http://www.armlinux.org.uk/
F: arch/arm/vfp/
ARM/VOIPAC PXA270 SUPPORT
M: Marek Vasut <marek.vasut@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-pxa/include/mach/vpac270.h
F: arch/arm/mach-pxa/vpac270.c
ARM/VT8500 ARM ARCHITECTURE
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Orphan
@@ -3170,13 +3010,6 @@ F: drivers/video/fbdev/vt8500lcdfb.*
F: drivers/video/fbdev/wm8505fb*
F: drivers/video/fbdev/wmt_ge_rops.*
ARM/ZIPIT Z2 SUPPORT
M: Marek Vasut <marek.vasut@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-pxa/include/mach/z2.h
F: arch/arm/mach-pxa/z2.c
ARM/ZYNQ ARCHITECTURE
M: Michal Simek <michal.simek@xilinx.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -15329,7 +15162,6 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
F: arch/arm/configs/omap1_defconfig
F: arch/arm/mach-omap1/
F: arch/arm/plat-omap/
F: drivers/i2c/busses/i2c-omap.c
F: include/linux/platform_data/ams-delta-fiq.h
F: include/linux/platform_data/i2c-omap.h
@@ -15344,7 +15176,6 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
F: arch/arm/configs/omap2plus_defconfig
F: arch/arm/mach-omap2/
F: arch/arm/plat-omap/
F: drivers/bus/ti-sysc.c
F: drivers/i2c/busses/i2c-omap.c
F: drivers/irqchip/irq-omap-intc.c
@@ -18386,19 +18217,6 @@ L: linux-s390@vger.kernel.org
S: Supported
F: drivers/s390/scsi/zfcp_*
S3C ADC BATTERY DRIVER
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
L: linux-samsung-soc@vger.kernel.org
S: Odd Fixes
F: drivers/power/supply/s3c_adc_battery.c
F: include/linux/s3c_adc_battery.h
S3C24XX SD/MMC Driver
M: Ben Dooks <ben-linux@fluff.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
F: drivers/mmc/host/s3cmci.*
SAA6588 RDS RECEIVER DRIVER
M: Hans Verkuil <hverkuil@xs4all.nl>
L: linux-media@vger.kernel.org
@@ -18551,11 +18369,9 @@ F: Documentation/devicetree/bindings/clock/samsung,*.yaml
F: Documentation/devicetree/bindings/clock/samsung,s3c*
F: drivers/clk/samsung/
F: include/dt-bindings/clock/exynos*.h
F: include/dt-bindings/clock/s3c*.h
F: include/dt-bindings/clock/s5p*.h
F: include/dt-bindings/clock/samsung,*.h
F: include/linux/clk/samsung.h
F: include/linux/platform_data/clk-s3c2410.h
SAMSUNG SPI DRIVERS
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
@@ -18566,7 +18382,6 @@ S: Maintained
F: Documentation/devicetree/bindings/spi/samsung,spi*.yaml
F: drivers/spi/spi-s3c*
F: include/linux/platform_data/spi-s3c64xx.h
F: include/linux/spi/s3c24xx-fiq.h
SAMSUNG SXGBE DRIVERS
M: Byungho An <bh74.an@samsung.com>
@@ -19136,14 +18951,6 @@ M: Simtec Linux Team <linux@simtec.co.uk>
S: Supported
W: http://www.simtec.co.uk/products/EB110ATX/
SIMTEC EB2410ITX (BAST)
M: Simtec Linux Team <linux@simtec.co.uk>
S: Supported
W: http://www.simtec.co.uk/products/EB2410ITX/
F: arch/arm/mach-s3c/bast-ide.c
F: arch/arm/mach-s3c/bast-irq.c
F: arch/arm/mach-s3c/mach-bast.c
SIOX
M: Thorsten Scherer <t.scherer@eckelmann.de>
M: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
@@ -20880,7 +20687,6 @@ W: https://linuxtv.org
Q: http://patchwork.linuxtv.org/project/linux-media/list/
T: git git://linuxtv.org/mhadli/v4l-dvb-davinci_devices.git
F: drivers/media/platform/ti/davinci/
F: drivers/staging/media/deprecated/vpfe_capture/
F: include/media/davinci/
TI ENHANCED CAPTURE (eCAP) DRIVER
arch/alpha/include/asm/Kbuild
+1
View File
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
generated-y += syscall_table.h
generic-y += agp.h
generic-y += export.h
generic-y += kvm_para.h
generic-y += mcs_spinlock.h
arch/alpha/include/asm/agp.h
-19
View File
@@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef AGP_H
#define AGP_H 1
#include <asm/io.h>
/* dummy for now */
#define map_page_into_agp(page) do { } while (0)
#define unmap_page_from_agp(page) do { } while (0)
#define flush_agp_cache() mb()
/* GATT allocation. Returns/accepts GATT kernel virtual address. */
#define alloc_gatt_pages(order) \
((char *)__get_free_pages(GFP_KERNEL, (order)))
#define free_gatt_pages(table, order) \
free_pages((unsigned long)(table), (order))
#endif
arch/arm/Kconfig
+1 -25
View File
@@ -282,8 +282,7 @@ config PHYS_OFFSET
default DRAM_BASE if !MMU
default 0x00000000 if ARCH_FOOTBRIDGE
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
default 0x30000000 if ARCH_S3C24XX
default 0xa0000000 if ARCH_IOP32X || ARCH_PXA
default 0xa0000000 if ARCH_PXA
default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
default 0
help
@@ -438,8 +437,6 @@ source "arch/arm/mach-berlin/Kconfig"
source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig"
source "arch/arm/mach-davinci/Kconfig"
source "arch/arm/mach-digicolor/Kconfig"
@@ -462,8 +459,6 @@ source "arch/arm/mach-hpe/Kconfig"
source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-iop32x/Kconfig"
source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-keystone/Kconfig"
@@ -931,12 +926,6 @@ config ISA
config ISA_DMA_API
bool
config PCI_NANOENGINE
bool "BSE nanoEngine PCI support"
depends on SA1100_NANOENGINE
help
Enable PCI on the BSE nanoEngine board.
config ARM_ERRATA_814220
bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
depends on CPU_V7
@@ -1465,19 +1454,6 @@ config ATAGS
the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
to remove ATAGS support from your kernel binary.
config UNUSED_BOARD_FILES
bool "Board support for machines without known users"
depends on ATAGS
help
Most ATAGS based board files are completely unused and are
scheduled for removal in early 2023, and left out of kernels
by default now. If you are using a board file that is marked
as unused, turn on this option to build support into the kernel.
To keep support for your individual board from being removed,
send a reply to the email discussion at
https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/
config DEPRECATED_PARAM_STRUCT
bool "Provide old way to pass kernel parameters"
depends on ATAGS
arch/arm/Kconfig.debug
+16 -113
View File
@@ -307,14 +307,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to the second serial port on these devices.
config DEBUG_CNS3XXX
bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx"
depends on ARCH_CNS3XXX
select DEBUG_UART_8250
help
Say Y here if you want the debug print routines to direct
their output to the CNS3xxx UART0.
config DEBUG_DAVINCI_DA8XX_UART1
bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
depends on ARCH_DAVINCI_DA8XX
@@ -331,14 +323,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to UART2 serial port on DaVinci DA8XX devices.
config DEBUG_DAVINCI_DMx_UART0
bool "Kernel low-level debugging on DaVinci DMx using UART0"
depends on ARCH_DAVINCI_DMx
select DEBUG_UART_8250
help
Say Y here if you want the debug print routines to direct
their output to UART0 serial port on DaVinci DMx devices.
config DEBUG_DC21285_PORT
bool "Kernel low-level debugging messages via footbridge serial port"
depends on FOOTBRIDGE
@@ -768,30 +752,6 @@ choice
depends on ARCH_OMAP2PLUS
select DEBUG_UART_8250
config DEBUG_OMAP7XXUART1
bool "Kernel low-level debugging via OMAP730 UART1"
depends on ARCH_OMAP730
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on OMAP730 based platforms on the UART1.
config DEBUG_OMAP7XXUART2
bool "Kernel low-level debugging via OMAP730 UART2"
depends on ARCH_OMAP730
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on OMAP730 based platforms on the UART2.
config DEBUG_OMAP7XXUART3
bool "Kernel low-level debugging via OMAP730 UART3"
depends on ARCH_OMAP730
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on OMAP730 based platforms on the UART3.
config DEBUG_TI81XXUART1
bool "Kernel low-level debugging messages via TI81XX UART1 (ti8148evm)"
depends on ARCH_OMAP2PLUS
@@ -1046,7 +1006,6 @@ choice
config DEBUG_S3C_UART0
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 0 for low-level debug"
@@ -1058,7 +1017,6 @@ choice
config DEBUG_S3C_UART1
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 1 for low-level debug"
@@ -1070,7 +1028,6 @@ choice
config DEBUG_S3C_UART2
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 2 for low-level debug"
@@ -1090,33 +1047,6 @@ choice
their output to UART 3. The port must have been initialised
by the boot-loader before use.
config DEBUG_S3C2410_UART0
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 0. The port must have been initialised
by the boot-loader before use.
config DEBUG_S3C2410_UART1
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 1. The port must have been initialised
by the boot-loader before use.
config DEBUG_S3C2410_UART2
depends on ARCH_S3C24XX
select DEBUG_S3C2410_UART
bool "Use S3C2410/S3C2412 UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 2. The port must have been initialised
by the boot-loader before use.
config DEBUG_SA1100
depends on ARCH_SA1100
bool "Use SA1100 UARTs for low-level debug"
@@ -1479,13 +1409,6 @@ config DEBUG_AT91_UART
config DEBUG_EXYNOS_UART
bool
config DEBUG_S3C2410_UART
bool
select DEBUG_S3C24XX_UART
config DEBUG_S3C24XX_UART
bool
config DEBUG_S3C64XX_UART
bool
@@ -1493,8 +1416,7 @@ config DEBUG_S5PV210_UART
bool
config DEBUG_S3C_UART
depends on DEBUG_S3C2410_UART || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || DEBUG_S5PV210_UART || \
depends on DEBUG_S3C64XX_UART || DEBUG_S5PV210_UART || \
DEBUG_EXYNOS_UART
int
default "0" if DEBUG_S3C_UART0
@@ -1595,7 +1517,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART || DEBUG_S3C64XX_UART
default "debug/s3c24xx.S" if DEBUG_S3C64XX_UART
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sti.S" if DEBUG_STIH41X_ASC2
default "debug/sti.S" if DEBUG_STIH41X_SBC_ASC1
@@ -1618,11 +1540,10 @@ config DEBUG_UART_PL01X
# Compatibility options for 8250
config DEBUG_UART_8250
def_bool ARCH_IOP32X || ARCH_IXP4XX || ARCH_RPC
def_bool ARCH_IXP4XX || ARCH_RPC
config DEBUG_UART_PHYS
hex "Physical base address of debug UART"
default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
default 0x01c28000 if DEBUG_SUNXI_UART0
default 0x01c28400 if DEBUG_SUNXI_UART1
default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1
@@ -1679,13 +1600,6 @@ config DEBUG_UART_PHYS
default 0x4806e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4
default 0x49020000 if DEBUG_OMAP3UART3
default 0x49042000 if DEBUG_OMAP3UART4
default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
DEBUG_S3C2410_UART0)
default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
DEBUG_S3C2410_UART1)
default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2)
default 0x78000000 if DEBUG_CNS3XXX
default 0x7c0003f8 if DEBUG_FOOTBRIDGE_COM1
default 0x7f005000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0
default 0x7f005400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1
@@ -1729,7 +1643,6 @@ config DEBUG_UART_PHYS
default 0xfcb00000 if DEBUG_HI3620_UART
default 0xfd883000 if DEBUG_ALPINE_UART0
default 0xfe531000 if DEBUG_STIH41X_SBC_ASC1
default 0xfe800000 if ARCH_IOP32X
default 0xfed32000 if DEBUG_STIH41X_ASC2
default 0xff690000 if DEBUG_RK32_UART2
default 0xffc02000 if DEBUG_SOCFPGA_UART0
@@ -1738,9 +1651,9 @@ config DEBUG_UART_PHYS
default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
default 0xfff36000 if DEBUG_HIGHBANK_UART
default 0xfffb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
default 0xfffb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
default 0xfffb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
default 0xfffb0000 if DEBUG_OMAP1UART1
default 0xfffb0800 if DEBUG_OMAP1UART2
default 0xfffb9800 if DEBUG_OMAP1UART3
default 0xfffe8600 if DEBUG_BCM63XX_UART
default 0xffffee00 if DEBUG_AT91_SAM9263_DBGU
default 0xfffff200 if DEBUG_AT91_RM9200_DBGU
@@ -1754,7 +1667,7 @@ config DEBUG_UART_PHYS
DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
DEBUG_RCAR_GEN2_SCIFA2 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_RMOBILE_SCIFA4 || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_DIGICOLOR_UA0 || \
@@ -1791,15 +1704,9 @@ config DEBUG_UART_VIRT
default 0xf6200000 if DEBUG_PXA_UART1
default 0xf7000000 if DEBUG_SUN9I_UART0
default 0xf7000000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0
default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
DEBUG_S3C2410_UART0)
default 0xf7000400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1
default 0xf7000800 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART2
default 0xf7000c00 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART3
default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
DEBUG_S3C2410_UART1)
default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
DEBUG_S3C2410_UART2)
default 0xf7020000 if DEBUG_AT91_SAMA5D2_UART1
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8007000 if DEBUG_HIP04_UART
@@ -1818,7 +1725,6 @@ config DEBUG_UART_VIRT
DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2
default 0xfa06e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4
default 0xfa71e000 if DEBUG_QCOM_UARTDM
default 0xfb002000 if DEBUG_CNS3XXX
default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
default 0xfb00c000 if DEBUG_AT91_SAMA5D4_USART3
default 0xfb020000 if DEBUG_OMAP3UART3
@@ -1835,7 +1741,6 @@ config DEBUG_UART_VIRT
default 0xfe018000 if DEBUG_MMP_UART3
default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
default 0xfe300000 if DEBUG_BCM_KONA_UART
default 0xfe800000 if ARCH_IOP32X
default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
default 0xfeb24000 if DEBUG_RK3X_UART0
default 0xfeb26000 if DEBUG_RK3X_UART1
@@ -1846,7 +1751,6 @@ config DEBUG_UART_VIRT
default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART
@@ -1859,14 +1763,14 @@ config DEBUG_UART_VIRT
default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xfef36000 if DEBUG_HIGHBANK_UART
default 0xff0b0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
default 0xff0b0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
default 0xff0b9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
default 0xff0b0000 if DEBUG_OMAP1UART1
default 0xff0b0800 if DEBUG_OMAP1UART2
default 0xff0b9800 if DEBUG_OMAP1UART3
default 0xffd01000 if DEBUG_HIP01_UART
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
DEBUG_QCOM_UARTDM || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_DIGICOLOR_UA0 || \
@@ -1877,9 +1781,8 @@ config DEBUG_UART_VIRT
config DEBUG_UART_8250_SHIFT
int "Register offset shift for the 8250 debug UART"
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \
DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \
DEBUG_OMAP7XXUART3
default 0 if DEBUG_FOOTBRIDGE_COM1 || DEBUG_BCM_5301X || \
DEBUG_BCM_HR2
default 3 if DEBUG_MSTARV7_PMUART
default 2
@@ -1890,9 +1793,9 @@ config DEBUG_UART_8250_WORD
default y if DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \
DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
DEBUG_DAVINCI_DA8XX_UART1 || DEBUG_DAVINCI_DA8XX_UART2 || \
DEBUG_BCM_IPROC_UART3 || DEBUG_BCM_KONA_UART || \
DEBUG_RK32_UART2
config DEBUG_UART_8250_PALMCHIP
bool "8250 UART is Palmchip BK-310x"
arch/arm/Makefile
+6 -4
View File
@@ -152,8 +152,6 @@ CHECKFLAGS += -D__arm__
# during boot, and this offset is critical to the functioning of
# kexec-tools.
textofs-y := 0x00008000
# We don't want the htc bootloader to corrupt kernel during resume
textofs-$(CONFIG_PM_H1940) := 0x00108000
# RTD1195 has Boot ROM at start of address space
textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000
# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
@@ -178,7 +176,6 @@ machine-$(CONFIG_ARCH_AXXIA) += axxia
machine-$(CONFIG_ARCH_BCM) += bcm
machine-$(CONFIG_ARCH_BERLIN) += berlin
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
machine-$(CONFIG_ARCH_DOVE) += dove
@@ -189,7 +186,6 @@ machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISI) += hisi
machine-$(CONFIG_ARCH_HPE) += hpe
machine-$(CONFIG_ARCH_IOP32X) += iop32x
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
@@ -319,6 +315,10 @@ endif
# My testing targets (bypasses dependencies)
bp:; $(Q)$(MAKE) $(build)=$(boot) $(boot)/bootpImage
include $(srctree)/scripts/Makefile.defconf
PHONY += multi_v7_lpae_defconfig
multi_v7_lpae_defconfig:
$(call merge_into_defconfig,multi_v7_defconfig,lpae)
define archhelp
echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
@@ -334,4 +334,6 @@ define archhelp
echo ' (distribution) /sbin/$(INSTALLKERNEL) or'
echo ' install to $$(INSTALL_PATH) and run lilo'
echo ' vdso_install - Install unstripped vdso.so to $$(INSTALL_MOD_PATH)/vdso'
echo
echo ' multi_v7_lpae_defconfig - multi_v7_defconfig with CONFIG_ARM_LPAE enabled'
endef
arch/arm/boot/compressed/head-sa1100.S
-4
View File
@@ -19,10 +19,6 @@ __SA1100_start:
@ Preserve r8/r7 i.e. kernel entry values
#ifdef CONFIG_SA1100_COLLIE
mov r7, #MACH_TYPE_COLLIE
#endif
#ifdef CONFIG_SA1100_SIMPAD
@ UNTIL we've something like an open bootldr
mov r7, #MACH_TYPE_SIMPAD @should be 87
#endif
mrc p15, 0, r0, c1, c0, 0 @ read control reg
ands r0, r0, #0x0d
arch/arm/boot/compressed/misc-ep93xx.h
+1 -12
View File
@@ -57,8 +57,7 @@ static inline void ep93xx_decomp_setup(void)
if (machine_is_ts72xx())
ts72xx_watchdog_disable();
if (machine_is_adssphere() ||
machine_is_edb9301() ||
if (machine_is_edb9301() ||
machine_is_edb9302() ||
machine_is_edb9302a() ||
machine_is_edb9302a() ||
@@ -69,16 +68,6 @@ static inline void ep93xx_decomp_setup(void)
machine_is_edb9315() ||
machine_is_edb9315a() ||
machine_is_edb9315a() ||
machine_is_gesbc9312() ||
machine_is_micro9() ||
machine_is_micro9l() ||
machine_is_micro9m() ||
machine_is_micro9s() ||
machine_is_micro9m() ||
machine_is_micro9l() ||
machine_is_micro9s() ||
machine_is_sim_one() ||
machine_is_snapper_cl15() ||
machine_is_ts72xx() ||
machine_is_bk3() ||
machine_is_vision_ep9307())
arch/arm/boot/dts/Makefile
+11 -2
View File
@@ -51,6 +51,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
dtb-$(CONFIG_SOC_SAM9X60) += \
at91-sam9x60_curiosity.dtb \
at91-sam9x60ek.dtb
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2-2.dtb \
@@ -246,6 +247,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5422-odroidxu3.dtb \
exynos5422-odroidxu3-lite.dtb \
exynos5422-odroidxu4.dtb \
exynos5422-samsung-k3g.dtb \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_ARCH_GEMINI) += \
gemini-dlink-dir-685.dtb \
@@ -465,6 +467,7 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-ppd.dtb \
imx53-qsb.dtb \
imx53-qsrb.dtb \
imx53-sk-imx53.dtb \
imx53-smd.dtb \
imx53-tx53-x03x.dtb \
imx53-tx53-x13x.dtb \
@@ -740,6 +743,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-colibri-wifi-iris.dtb \
imx6ull-colibri-wifi-iris-v2.dtb \
imx6ull-dhcom-drc02.dtb \
imx6ull-dhcom-pdk2.dtb \
imx6ull-dhcom-picoitx.dtb \
imx6ull-jozacp.dtb \
imx6ull-kontron-bl.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
@@ -1127,12 +1133,14 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb \
rv1126-edgeble-neu2-io.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-mk808.dtb \
rk3066a-rayeager.dtb \
rk3128-evb.dtb \
rk3188-bqedison2qc.dtb \
rk3188-px3-evb.dtb \
rk3188-radxarock.dtb \
@@ -1163,8 +1171,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-speedy.dtb \
rk3288-veyron-tiger.dtb \
rk3288-vyasa.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += \
s3c6410-mini6410.dtb \
s3c6410-smdk6410.dtb
@@ -1179,6 +1185,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3.dtb \
socfpga_arria10_mercury_pe1.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
@@ -1605,6 +1612,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-facebook-elbert.dtb \
aspeed-bmc-facebook-fuji.dtb \
aspeed-bmc-facebook-galaxy100.dtb \
aspeed-bmc-facebook-greatlakes.dtb \
aspeed-bmc-facebook-minipack.dtb \
aspeed-bmc-facebook-tiogapass.dtb \
aspeed-bmc-facebook-wedge40.dtb \
@@ -1641,6 +1649,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-inventec-transformers.dtb \
aspeed-bmc-tyan-s7106.dtb \
aspeed-bmc-tyan-s8036.dtb \
aspeed-bmc-ufispace-ncplite.dtb \
aspeed-bmc-vegman-n110.dtb \
aspeed-bmc-vegman-rx20.dtb \
aspeed-bmc-vegman-sx20.dtb
arch/arm/boot/dts/alpine.dtsi
+2 -2
View File
@@ -126,7 +126,7 @@
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
uart0: uart@fd883000 {
uart0: serial@fd883000 {
compatible = "ns16550a";
reg = <0x0 0xfd883000 0x0 0x1000>;
clock-frequency = <375000000>;
@@ -135,7 +135,7 @@
reg-io-width = <4>;
};
uart1: uart@fd884000 {
uart1: serial@fd884000 {
compatible = "ns16550a";
reg = <0x0 0xfd884000 0x0 0x1000>;
clock-frequency = <375000000>;
arch/arm/boot/dts/am335x-nano.dts
+26 -6
View File
@@ -120,8 +120,8 @@
uart3_pins: uart3_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */
AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */
AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
>;
@@ -129,8 +129,8 @@
uart4_pins: uart4_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */
AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */
>;
@@ -187,12 +187,22 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
rts-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>;
rs485-rts-active-high;
rs485-rx-during-tx;
rs485-rts-delay = <1 1>;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
rts-gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
rs485-rts-active-high;
rs485-rx-during-tx;
rs485-rts-delay = <1 1>;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
@@ -220,6 +230,11 @@
reg = <0x24>;
};
temperature-sensor@48 {
compatible = "lm75";
reg = <0x48>;
};
eeprom@53 {
compatible = "microchip,24c02", "atmel,24c02";
reg = <0x53>;
@@ -403,8 +418,13 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
bus-width = <4>;
cd-gpios = <&gpio3 8 0>;
wp-gpios = <&gpio3 18 0>;
cd-debounce-delay-ms = <5>;
cd-gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
};
&usb0 {
dr_mode = "host";
};
#include "tps65217.dtsi"
arch/arm/boot/dts/am3874-iceboard.dts
+2 -2
View File
@@ -106,7 +106,7 @@
* "i2c-mux-idle-disconnect" is important.
*/
pca9548@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
@@ -256,7 +256,7 @@
};
&i2c2 {
pca9548@71 {
i2c-mux@71 {
compatible = "nxp,pca9548";
reg = <0x71>;
#address-cells = <1>;
arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
+23 -2
View File
@@ -5,6 +5,7 @@
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "AMD EthanolX BMC";
@@ -58,10 +59,22 @@
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "bios";
spi-max-frequency = <100000000>;
};
};
&mac0 {
status = "okay";
@@ -78,7 +91,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
&pinctrl_rxd1_default
&pinctrl_nrts1_default
&pinctrl_ncts1_default>;
};
&uart5 {
@@ -160,7 +175,7 @@
&i2c3 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c256";
compatible = "atmel,24c128";
reg = <0x50>;
pagesize = <64>;
};
@@ -261,6 +276,12 @@
status = "okay";
};
&vuart {
status = "okay";
aspeed,lpc-io-reg = <0x3f8>;
aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
+12 -1
View File
@@ -307,7 +307,7 @@
flash@1 {
status = "okay";
m25p,fast-read;
label = "flash1";
label = "alt-bmc";
spi-max-frequency = <50000000>;
};
};
@@ -1064,3 +1064,14 @@
bias-disable;
};
};
&wdt1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdtrst1_default>;
aspeed,reset-type = "soc";
aspeed,external-signal;
aspeed,ext-push-pull;
aspeed,ext-active-high;
aspeed,ext-pulse-duration = <256>;
};
arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
+241
View File
@@ -0,0 +1,241 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2022 Facebook Inc.
/dts-v1/;
#include "aspeed-g6.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/leds/leds-pca955x.h>
#include <dt-bindings/i2c/i2c.h>
/ {
model = "Facebook Greatlakes BMC";
compatible = "facebook,greatlakes-bmc", "aspeed,ast2600";
aliases {
serial4 = &uart5;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
<&adc1 0>, <&adc1 2>, <&adc1 3>, <&adc1 4>,
<&adc1 5>, <&adc1 6>;
};
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&uart5 {
status = "okay";
};
&wdt1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdtrst1_default>;
aspeed,reset-type = "soc";
aspeed,external-signal;
aspeed,ext-push-pull;
aspeed,ext-active-high;
aspeed,ext-pulse-duration = <256>;
};
&mac3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii4_default>;
no-hw-checksum;
use-ncsi;
mlx,multi-host;
ncsi-ctrl,start-redo-probe;
ncsi-ctrl,no-channel-monitor;
ncsi-package = <1>;
ncsi-channel = <1>;
ncsi-rexmit = <1>;
ncsi-timeout = <2>;
};
&rtc {
status = "okay";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "bmc2";
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
};
};
&i2c0 {
status = "okay";
multi-master;
ipmb@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};
&i2c1 {
status = "okay";
multi-master;
ipmb@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};
&i2c2 {
status = "okay";
multi-master;
ipmb@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};
&i2c3 {
status = "okay";
multi-master;
ipmb@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
// NIC EEPROM
eeprom@50 {
compatible = "st,24c32";
reg = <0x50>;
};
};
&i2c9 {
status = "okay";
multi-master;
ipmb@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
eeprom@51 {
compatible = "atmel,24c128";
reg = <0x51>;
};
eeprom@54 {
compatible = "atmel,24c128";
reg = <0x54>;
};
};
&i2c12 {
status = "okay";
temperature-sensor@4f {
compatible = "lm75";
reg = <0x4f>;
};
};
&i2c13 {
status = "okay";
};
&adc0 {
ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
&pinctrl_adc4_default &pinctrl_adc5_default
&pinctrl_adc6_default &pinctrl_adc7_default>;
};
&adc1 {
ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc10_default
&pinctrl_adc11_default &pinctrl_adc12_default
&pinctrl_adc13_default &pinctrl_adc14_default>;
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&uhci {
status = "okay";
};
&gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
};
arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts
+4
View File
@@ -857,6 +857,10 @@
status = "okay";
};
&uart2 {
status = "okay";
};
&vuart1 {
status = "okay";
};
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
+4
View File
@@ -3649,6 +3649,10 @@
status = "okay";
};
&uart2 {
status = "okay";
};
&vuart1 {
status = "okay";
};
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
+4
View File
@@ -2352,6 +2352,10 @@
};
};
&uart2 {
status = "okay";
};
&vuart1 {
status = "okay";
};
arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts
+1
View File
@@ -364,6 +364,7 @@
&kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
aspeed,lpc-interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */
arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts
+360
View File
@@ -0,0 +1,360 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright (c) 2022 Ufispace Co., Ltd.
/dts-v1/;
#include "aspeed-g6.dtsi"
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Ufispace NCPLite BMC";
compatible = "ufispace,ncplite-bmc", "aspeed,ast2600";
aliases {
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200n8 earlycon";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
<&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
<&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
};
gpio-keys {
compatible = "gpio-keys";
fan-status-int-l {
label = "fan-status-int-l";
gpios = <&gpio0 ASPEED_GPIO(M, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(M, 2)>;
};
allpwr-good {
label = "allpwr-good";
gpios = <&gpio0 ASPEED_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
linux,code = <ASPEED_GPIO(V, 4)>;
};
psu0-alert-n {
label = "psu0-alert-n";
gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(V, 1)>;
};
psu1-alert-n {
label = "psu1-alert-n";
gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(V, 2)>;
};
int-thermal-alert {
label = "int-thermal-alert";
gpios = <&gpio0 ASPEED_GPIO(P, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(P, 2)>;
};
cpu-caterr-l {
label = "cpu-caterr-l";
gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(N, 3)>;
};
cpu-thermtrip-l {
label = "cpu-thermtrip-l";
gpios = <&gpio0 ASPEED_GPIO(V, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(V, 5)>;
};
psu0-presence-l {
label = "psu0-presence-l";
gpios = <&gpio0 ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 6)>;
};
psu1-presence-l {
label = "psu1-presence-l";
gpios = <&gpio0 ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 7)>;
};
psu0-power-ok {
label = "psu0-power-ok";
gpios = <&gpio0 ASPEED_GPIO(M, 4) GPIO_ACTIVE_HIGH>;
linux,code = <ASPEED_GPIO(M, 4)>;
};
psu1-power-ok {
label = "psu1-power-ok";
gpios = <&gpio0 ASPEED_GPIO(M, 5) GPIO_ACTIVE_HIGH>;
linux,code = <ASPEED_GPIO(M, 5)>;
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
fan0-presence {
label = "fan0-presence";
gpios = <&fan_ioexp 2 GPIO_ACTIVE_LOW>;
linux,code = <2>;
};
fan1-presence {
label = "fan1-presence";
gpios = <&fan_ioexp 6 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
fan2-presence {
label = "fan2-presence";
gpios = <&fan_ioexp 10 GPIO_ACTIVE_LOW>;
linux,code = <10>;
};
fan3-presence {
label = "fan3-presence";
gpios = <&fan_ioexp 14 GPIO_ACTIVE_LOW>;
linux,code = <14>;
};
};
};
&mac2 {
status = "okay";
use-ncsi;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii3_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>,
<&syscon ASPEED_CLK_MAC3RCLK>;
clock-names = "MACCLK", "RCLK";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "alt-bmc";
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64-alt.dtsi"
};
};
&uart1 {
status = "okay";
};
&uart4 {
status = "okay";
};
&uart5 {
status = "okay";
};
&kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
};
&lpc_reset {
status = "okay";
};
&lpc_ctrl {
status = "okay";
};
&uart_routing {
status = "okay";
};
&wdt1 {
status = "okay";
};
&wdt2 {
status = "okay";
};
&peci0 {
status = "okay";
};
&udc {
status = "okay";
};
&adc0 {
vref = <2500>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
&pinctrl_adc4_default &pinctrl_adc5_default
&pinctrl_adc6_default &pinctrl_adc7_default>;
};
&adc1 {
vref = <2500>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
&pinctrl_adc10_default &pinctrl_adc11_default
&pinctrl_adc12_default &pinctrl_adc13_default
&pinctrl_adc14_default &pinctrl_adc15_default>;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
lm75@48 {
compatible = "national,lm75";
reg = <0x48>;
};
lm75@49 {
compatible = "national,lm75";
reg = <0x49>;
};
lm86@4c {
compatible = "national,lm86";
reg = <0x4c>;
};
};
&i2c2 {
status = "okay";
lm75@4f {
cpmpatible = "national,lm75";
reg = <0x4f>;
};
fan_ioexp: pca9535@20 {
compatible = "nxp,pca9535";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"","","presence-fan0","",
"","","presence-fan1","",
"","","presence-fan2","",
"","","presence-fan3","";
};
};
&i2c3 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
pagesize = <64>;
};
};
&i2c4 {
status = "okay";
psu@58 {
compatible = "pmbus";
reg = <0x58>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <1>;
};
};
&i2c5 {
status = "okay";
psu@58 {
compatible = "pmbus";
reg = <0x58>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <1>;
};
};
&i2c8 {
status = "okay";
};
&i2c10 {
status = "okay";
lm75@4d {
compatible = "national,lm75";
reg = <0x4d>;
};
};
&gpio0 {
status = "okay";
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
/*B0-B7*/ "","","","","","","","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
/*F0-F7*/ "CPU_PWRGD","","","power-button","host0-ready","","presence-ps0","presence-ps1",
/*G0-G7*/ "","","","","","","","",
/*H0-H7*/ "","","","","","","","",
/*I0-I7*/ "","","","","","reset-button","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "power-chassis-control0","power-chassis-control1","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","power-chassis-good","","","";
};
arch/arm/boot/dts/at91-gatwick.dts
+6 -6
View File
@@ -31,37 +31,37 @@
leds {
compatible = "gpio-leds";
ethernet {
led-ethernet {
label = "gatwick:yellow:ethernet";
gpios = <&pioA 10 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wifi {
led-wifi {
label = "gatwick:green:wifi";
gpios = <&pioA 28 GPIO_ACTIVE_LOW>;
default-state = "off";
};
ble {
led-ble {
label = "gatwick:blue:ble";
gpios = <&pioA 22 GPIO_ACTIVE_LOW>;
default-state = "off";
};
lora {
led-lora {
label = "gatwick:orange:lora";
gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
default-state = "off";
};
blank {
led-blank {
label = "gatwick:green:blank";
gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
default-state = "off";
};
user {
led-user {
label = "gatwick:yellow:user";
gpios = <&pioA 12 GPIO_ACTIVE_LOW>;
default-state = "off";
arch/arm/boot/dts/at91-sam9x60_curiosity.dts
+503
View File
@@ -0,0 +1,503 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sam9x60_curiosity.dts - Device Tree file for Microchip SAM9X60 Curiosity board
*
* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
*
* Author: Durai Manickam KR <durai.manickamkr@microchip.com>
*/
/dts-v1/;
#include "sam9x60.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Microchip SAM9X60 Curiosity";
compatible = "microchip,sam9x60-curiosity", "microchip,sam9x60", "atmel,at91sam9";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c6;
serial2 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@20000000 {
reg = <0x20000000 0x8000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
button-user {
label = "PB_USER";
gpios = <&pioA 29 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-red {
label = "red";
gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
};
led-green {
label = "green";
gpios = <&pioD 19 GPIO_ACTIVE_HIGH>;
};
led-blue {
label = "blue";
gpios = <&pioD 21 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
vdd_1v8: regulator-0 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VDD_1V8";
};
vdd_1v15: regulator-1 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <1150000>;
regulator-min-microvolt = <1150000>;
regulator-name = "VDD_1V15";
};
vdd1_3v3: regulator-2 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD1_3V3";
};
};
&adc {
vddana-supply = <&vdd1_3v3>;
vref-supply = <&vdd1_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
status = "okay";
};
&can0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
status = "disabled"; /* Conflict with dbgu. */
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
status = "okay";
};
&dbgu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
status = "okay"; /* Conflict with can0. */
};
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_lsb>;
status = "okay";
nand_controller: nand-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
uboot@40000 {
label = "u-boot";
reg = <0x40000 0xc0000>;
};
ubootenvred@100000 {
label = "U-Boot Env Redundant";
reg = <0x100000 0x40000>;
};
ubootenv@140000 {
label = "U-Boot Env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x1f800000>;
};
};
};
};
};
&flx0 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c0: i2c@600 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
};
&flx6 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c6: i2c@600 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx6_default>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "disabled";
};
};
&flx7 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart7: serial@200 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx7_default>;
status = "okay";
};
};
&macb0 {
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "okay";
ethernet-phy@0 {
reg = <0x0>;
};
};
&pinctrl {
adc {
pinctrl_adc_default: adc-default {
atmel,pins = <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adtrg_default: adtrg-default {
atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
};
can0 {
pinctrl_can0_rx_tx: can0-rx-tx {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0 */
AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX0 */
AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
};
};
can1 {
pinctrl_can1_rx_tx: can1-rx-tx {
atmel,pins =
<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1 */
AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX1 */
AT91_PIOB 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
};
};
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
ebi {
pinctrl_ebi_data_lsb: ebi-data-lsb {
atmel,pins =
<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_ebi_addr_nand: ebi-addr-nand {
atmel,pins =
<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
};
flexcom {
pinctrl_flx0_default: flx0-twi {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_flx6_default: flx6-twi {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_flx7_default: flx7-usart {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
};
gpio-keys {
pinctrl_key_gpio_default: pinctrl-key-gpio {
atmel,pins = <AT91_PIOA 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
leds {
pinctrl_gpio_leds: gpio-leds {
atmel,pins = <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
macb0 {
pinctrl_macb0_rmii: macb0-rmii-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
};
nand {
pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
pwm0 {
pinctrl_pwm0_0: pwm0-0 {
atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_1: pwm0-1 {
atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_2: pwm0-2 {
atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
sdmmc0 {
pinctrl_sdmmc0_default: sdmmc0 {
atmel,pins =
<AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA17 CK periph A with pullup */
AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA16 CMD periph A with pullup */
AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA15 DAT0 periph A */
AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA18 DAT1 periph A with pullup */
AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA19 DAT2 periph A with pullup */
AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA20 DAT3 periph A with pullup */
};
pinctrl_sdmmc0_cd: sdmmc0-cd {
atmel,pins =
<AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
sdmmc1 {
pinctrl_sdmmc1_default: sdmmc1 {
atmel,pins =
<AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
};
};
usb0 {
pinctrl_usba_vbus: usba-vbus {
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
usb1 {
pinctrl_usb_default: usb-default {
atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
}; /* pinctrl */
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default &pinctrl_sdmmc0_cd>;
cd-gpios = <&pioA 25 GPIO_ACTIVE_LOW>;
disable-wp;
status = "okay";
};
&sdmmc1 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
disable-wp;
status = "okay";
};
&shutdown_controller {
debounce-delay-us = <976>;
status = "okay";
input@0 {
reg = <0>;
};
};
&tcb0 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&usb0 {
atmel,vbus-gpio = <&pioA 27 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioD 18 GPIO_ACTIVE_HIGH
&pioD 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
status = "okay";
};
&watchdog {
status = "okay";
};
arch/arm/boot/dts/at91-sam9x60ek.dts
+10 -40
View File
@@ -16,8 +16,8 @@
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
serial1 = &uart1;
i2c1 = &i2c6;
serial1 = &uart5;
};
chosen {
@@ -207,15 +207,11 @@
status = "okay";
i2c0: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
atmel,fifo-size = <16>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
@@ -234,17 +230,10 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
status = "disabled";
spi0: spi@400 {
compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
spi4: spi@400 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
atmel,fifo-size = <16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@@ -253,24 +242,9 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart1: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(10))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(11))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "usart";
pinctrl-0 = <&pinctrl_flx5_default>;
uart5: serial@200 {
pinctrl-names = "default";
atmel,use-dma-rx;
atmel,use-dma-tx;
pinctrl-0 = <&pinctrl_flx5_default>;
status = "okay";
};
};
@@ -279,16 +253,12 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c1: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
i2c6: i2c@600 {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx6_default>;
atmel,fifo-size = <16>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
@@ -439,7 +409,7 @@
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_flx5_default: flx_uart {
pinctrl_flx5_default: flx5_uart {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+3 -3
View File
@@ -498,17 +498,17 @@
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay"; /* Conflict with pwm0. */
red {
led-red {
label = "red";
gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>;
};
green {
led-green {
label = "green";
gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
};
blue {
led-blue {
label = "blue";
gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
+3 -3
View File
@@ -46,17 +46,17 @@
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay";
red {
led-red {
label = "red";
gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>;
};
green {
led-green {
label = "green";
gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>;
};
blue {
led-blue {
label = "blue";
gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
arch/arm/boot/dts/at91-sama5d2_icp.dts
+3 -3
View File
@@ -62,17 +62,17 @@
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay"; /* conflict with pwm0 */
red {
led-red {
label = "red";
gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>;
};
green {
led-green {
label = "green";
gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
};
blue {
led-blue {
label = "blue";
gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+3 -3
View File
@@ -416,17 +416,17 @@
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay";
red {
led-red {
label = "red";
gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>;
};
green {
led-green {
label = "green";
gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
};
blue {
led-blue {
label = "blue";
gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
arch/arm/boot/dts/at91-sama5d2_xplained.dts
+3 -3
View File
@@ -725,18 +725,18 @@
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay"; /* conflict with pwm0 */
red {
led-red {
label = "red";
gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>;
};
green {
led-green {
label = "green";
gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>;
};
blue {
led-blue {
label = "blue";
gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
arch/arm/boot/dts/at91-sama5d3_xplained.dts
+2 -2
View File
@@ -392,13 +392,13 @@
pinctrl-0 = <&pinctrl_gpio_leds>;
status = "okay";
d2 {
led-d2 {
label = "d2";
gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */
linux,default-trigger = "heartbeat";
};
d3 {
led-d3 {
label = "d3"; /* Conflict with EBI CS0, USART2 CTS. */
gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
};
arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
+3 -3
View File
@@ -115,19 +115,19 @@
compatible = "gpio-leds";
status = "okay";
user1 {
led-user1 {
label = "user1";
gpios = <&pioD 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
user2 {
led-user2 {
label = "user2";
gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
user3 {
led-user3 {
label = "user3";
gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
arch/arm/boot/dts/at91-sama5d4_xplained.dts
+2 -2
View File
@@ -262,13 +262,13 @@
pinctrl-0 = <&pinctrl_gpio_leds>;
status = "okay";
d8 {
led-d8 {
label = "d8";
gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
d10 {
led-d10 {
label = "d10";
gpios = <&pioE 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
arch/arm/boot/dts/at91-sama5d4ek.dts
+3 -3
View File
@@ -287,18 +287,18 @@
compatible = "gpio-leds";
status = "okay";
d8 {
led-d8 {
label = "d8";
/* PE28, conflicts with usart4 rts pin */
gpios = <&pioE 28 GPIO_ACTIVE_LOW>;
};
d9 {
led-d9 {
label = "d9";
gpios = <&pioE 9 GPIO_ACTIVE_HIGH>;
};
d10 {
led-d10 {
label = "d10";
gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
arch/arm/boot/dts/at91-tse850-3.dts
+8 -8
View File
@@ -106,35 +106,35 @@
leds {
compatible = "gpio-leds";
ch1-red {
led-ch1-red {
label = "ch-1:red";
gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
};
ch1-green {
led-ch1-green {
label = "ch-1:green";
gpios = <&pioA 22 GPIO_ACTIVE_LOW>;
};
ch2-red {
led-ch2-red {
label = "ch-2:red";
gpios = <&pioA 21 GPIO_ACTIVE_LOW>;
};
ch2-green {
led-ch2-green {
label = "ch-2:green";
gpios = <&pioA 20 GPIO_ACTIVE_LOW>;
};
data-red {
led-data-red {
label = "data:red";
gpios = <&pioA 19 GPIO_ACTIVE_LOW>;
};
data-green {
led-data-green {
label = "data:green";
gpios = <&pioA 18 GPIO_ACTIVE_LOW>;
};
alarm-red {
led-alarm-red {
label = "alarm:red";
gpios = <&pioA 17 GPIO_ACTIVE_LOW>;
};
alarm-green {
led-alarm-green {
label = "alarm:green";
gpios = <&pioA 16 GPIO_ACTIVE_LOW>;
};
arch/arm/boot/dts/axm55xx.dtsi
+4 -4
View File
@@ -108,7 +108,7 @@
#size-cells = <2>;
ranges;
serial0: uart@2010080000 {
serial0: serial@2010080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10080000 0 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
@@ -117,7 +117,7 @@
status = "disabled";
};
serial1: uart@2010081000 {
serial1: serial@2010081000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10081000 0 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -126,7 +126,7 @@
status = "disabled";
};
serial2: uart@2010082000 {
serial2: serial@2010082000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10082000 0 0x1000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
@@ -135,7 +135,7 @@
status = "disabled";
};
serial3: uart@2010083000 {
serial3: serial@2010083000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10083000 0 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
arch/arm/boot/dts/bcm11351.dtsi
+4 -4
View File
@@ -50,7 +50,7 @@
reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
};
uart@3e000000 {
serial@3e000000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e000000 0x1000>;
@@ -60,7 +60,7 @@
reg-io-width = <4>;
};
uart@3e001000 {
serial@3e001000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e001000 0x1000>;
@@ -70,7 +70,7 @@
reg-io-width = <4>;
};
uart@3e002000 {
serial@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e002000 0x1000>;
@@ -80,7 +80,7 @@
reg-io-width = <4>;
};
uart@3e003000 {
serial@3e003000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e003000 0x1000>;
arch/arm/boot/dts/bcm21664-garnet.dts
+1 -1
View File
@@ -16,7 +16,7 @@
reg = <0x80000000 0x40000000>; /* 1 GB */
};
uart@3e000000 {
serial@3e000000 {
status = "okay";
};
arch/arm/boot/dts/bcm21664.dtsi
+3 -3
View File
@@ -50,7 +50,7 @@
reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
};
uart@3e000000 {
serial@3e000000 {
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e000000 0x118>;
@@ -60,7 +60,7 @@
reg-io-width = <4>;
};
uart@3e001000 {
serial@3e001000 {
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e001000 0x118>;
@@ -70,7 +70,7 @@
reg-io-width = <4>;
};
uart@3e002000 {
serial@3e002000 {
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e002000 0x118>;

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