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arm64: dts: qcom: x1e80100: Add UART2

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GENI SE2 within QUP0 is used as UART on some devices, describe it.
While at it, rewrite the adjacent UART21 pins node to make it more
easily modifiable.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Link: https://lore.kernel.org/r/20240826-topic-sl7-v2-4-c32ebae78789@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Konrad Dybcio
2024-08-26 16:37:53 +02:00
committed by Bjorn Andersson
parent 02a1bfb34c
commit ecbdce2041
1 changed files with 65 additions and 5 deletions
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70
arch/arm64/boot/dts/qcom/x1e80100.dtsi
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@@ -2143,6 +2143,28 @@
status = "disabled";
};
uart2: serial@b88000 {
compatible = "qcom,geni-uart";
reg = <0 0x00b88000 0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart2_default>;
pinctrl-names = "default";
status = "disabled";
};
spi2: spi@b88000 {
compatible = "qcom,geni-spi";
reg = <0 0x00b88000 0 0x4000>;
@@ -5558,12 +5580,50 @@
bias-disable;
};
qup_uart2_default: qup-uart2-default-state {
cts-pins {
pins = "gpio8";
function = "qup0_se2";
drive-strength = <2>;
bias-disable;
};
rts-pins {
pins = "gpio9";
function = "qup0_se2";
drive-strength = <2>;
bias-disable;
};
tx-pins {
pins = "gpio10";
function = "qup0_se2";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio11";
function = "qup0_se2";
drive-strength = <2>;
bias-disable;
};
};
qup_uart21_default: qup-uart21-default-state {
/* TX, RX */
pins = "gpio86", "gpio87";
function = "qup2_se5";
drive-strength = <2>;
bias-disable;
tx-pins {
pins = "gpio86";
function = "qup2_se5";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio87";
function = "qup2_se5";
drive-strength = <2>;
bias-disable;
};
};
};