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Merge 8ecd28b7a3 ("Merge tag 'ata-6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata") into android-mainline

Browse Source 
Steps on the way to 6.2-rc1

Change-Id: I297168b4601b38294e16110848a3bb025ff2eef9
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman
2023-01-21 10:46:25 +00:00
parent 82c4e09b2e 8ecd28b7a3
commit ea963e69f3
25 changed files with 248 additions and 657 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/ata/Kconfig
+1 -12
View File
@@ -295,7 +295,7 @@ config SATA_FSL
config SATA_GEMINI
tristate "Gemini SATA bridge support"
depends on ARCH_GEMINI || (OF && COMPILE_TEST)
depends on ARCH_GEMINI || COMPILE_TEST
select SATA_HOST
default ARCH_GEMINI
help
@@ -609,16 +609,6 @@ config PATA_ATP867X
If unsure, say N.
config PATA_BK3710
tristate "Palmchip BK3710 PATA support"
depends on ARCH_DAVINCI || COMPILE_TEST
select PATA_TIMINGS
help
This option enables support for the integrated IDE controller on
the TI DaVinci SoC.
If unsure, say N.
config PATA_CMD64X
tristate "CMD64x PATA support"
depends on PCI
@@ -696,7 +686,6 @@ config PATA_EP93XX
config PATA_FTIDE010
tristate "Faraday Technology FTIDE010 PATA support"
depends on OF
depends on ARM || COMPILE_TEST
depends on SATA_GEMINI
help
drivers/ata/Makefile
-1
View File
@@ -54,7 +54,6 @@ obj-$(CONFIG_PATA_AMD) += pata_amd.o
obj-$(CONFIG_PATA_ARTOP) += pata_artop.o
obj-$(CONFIG_PATA_ATIIXP) += pata_atiixp.o
obj-$(CONFIG_PATA_ATP867X) += pata_atp867x.o
obj-$(CONFIG_PATA_BK3710) += pata_bk3710.o
obj-$(CONFIG_PATA_CMD64X) += pata_cmd64x.o
obj-$(CONFIG_PATA_CS5520) += pata_cs5520.o
obj-$(CONFIG_PATA_CS5530) += pata_cs5530.o
drivers/ata/ahci.c
-1
View File
@@ -26,7 +26,6 @@
#include <linux/device.h>
#include <linux/dmi.h>
#include <linux/gfp.h>
#include <linux/msi.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <linux/libata.h>
drivers/ata/ahci.h
+121 -120
View File
@@ -24,6 +24,7 @@
#include <linux/libata.h>
#include <linux/phy/phy.h>
#include <linux/regulator/consumer.h>
#include <linux/bits.h>
/* Enclosure Management Control */
#define EM_CTRL_MSG_TYPE 0x000f0000
@@ -53,12 +54,12 @@ enum {
AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
AHCI_CMD_TBL_AR_SZ +
(AHCI_RX_FIS_SZ * 16),
AHCI_IRQ_ON_SG = (1 << 31),
AHCI_CMD_ATAPI = (1 << 5),
AHCI_CMD_WRITE = (1 << 6),
AHCI_CMD_PREFETCH = (1 << 7),
AHCI_CMD_RESET = (1 << 8),
AHCI_CMD_CLR_BUSY = (1 << 10),
AHCI_IRQ_ON_SG = BIT(31),
AHCI_CMD_ATAPI = BIT(5),
AHCI_CMD_WRITE = BIT(6),
AHCI_CMD_PREFETCH = BIT(7),
AHCI_CMD_RESET = BIT(8),
AHCI_CMD_CLR_BUSY = BIT(10),
RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
@@ -76,37 +77,37 @@ enum {
HOST_CAP2 = 0x24, /* host capabilities, extended */
/* HOST_CTL bits */
HOST_RESET = (1 << 0), /* reset controller; self-clear */
HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */
HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
HOST_RESET = BIT(0), /* reset controller; self-clear */
HOST_IRQ_EN = BIT(1), /* global IRQ enable */
HOST_MRSM = BIT(2), /* MSI Revert to Single Message */
HOST_AHCI_EN = BIT(31), /* AHCI enabled */
/* HOST_CAP bits */
HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
HOST_CAP_PART = (1 << 13), /* Partial state capable */
HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
HOST_CAP_CLO = (1 << 24), /* Command List Override support */
HOST_CAP_LED = (1 << 25), /* Supports activity LED */
HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
HOST_CAP_SNTF = (1 << 29), /* SNotification register */
HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
HOST_CAP_SXS = BIT(5), /* Supports External SATA */
HOST_CAP_EMS = BIT(6), /* Enclosure Management support */
HOST_CAP_CCC = BIT(7), /* Command Completion Coalescing */
HOST_CAP_PART = BIT(13), /* Partial state capable */
HOST_CAP_SSC = BIT(14), /* Slumber state capable */
HOST_CAP_PIO_MULTI = BIT(15), /* PIO multiple DRQ support */
HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
HOST_CAP_PMP = BIT(17), /* Port Multiplier support */
HOST_CAP_ONLY = BIT(18), /* Supports AHCI mode only */
HOST_CAP_CLO = BIT(24), /* Command List Override support */
HOST_CAP_LED = BIT(25), /* Supports activity LED */
HOST_CAP_ALPM = BIT(26), /* Aggressive Link PM support */
HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
HOST_CAP_MPS = BIT(28), /* Mechanical presence switch */
HOST_CAP_SNTF = BIT(29), /* SNotification register */
HOST_CAP_NCQ = BIT(30), /* Native Command Queueing */
HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */
/* HOST_CAP2 bits */
HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
HOST_CAP2_SDS = (1 << 3), /* Support device sleep */
HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */
HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */
HOST_CAP2_BOH = BIT(0), /* BIOS/OS handoff supported */
HOST_CAP2_NVMHCI = BIT(1), /* NVMHCI supported */
HOST_CAP2_APST = BIT(2), /* Automatic partial to slumber */
HOST_CAP2_SDS = BIT(3), /* Support device sleep */
HOST_CAP2_SADM = BIT(4), /* Support aggressive DevSlp */
HOST_CAP2_DESO = BIT(5), /* DevSlp from slumber only */
/* registers for each SATA port */
PORT_LST_ADDR = 0x00, /* command list DMA addr */
@@ -128,24 +129,24 @@ enum {
PORT_DEVSLP = 0x44, /* device sleep */
/* PORT_IRQ_{STAT,MASK} bits */
PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
PORT_IRQ_COLD_PRES = BIT(31), /* cold presence detect */
PORT_IRQ_TF_ERR = BIT(30), /* task file error */
PORT_IRQ_HBUS_ERR = BIT(29), /* host bus fatal error */
PORT_IRQ_HBUS_DATA_ERR = BIT(28), /* host bus data error */
PORT_IRQ_IF_ERR = BIT(27), /* interface fatal error */
PORT_IRQ_IF_NONFATAL = BIT(26), /* interface non-fatal error */
PORT_IRQ_OVERFLOW = BIT(24), /* xfer exhausted available S/G */
PORT_IRQ_BAD_PMP = BIT(23), /* incorrect port multiplier */
PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
PORT_IRQ_DMPS = (1 << 7), /* mechanical presence status */
PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
PORT_IRQ_PHYRDY = BIT(22), /* PhyRdy changed */
PORT_IRQ_DMPS = BIT(7), /* mechanical presence status */
PORT_IRQ_CONNECT = BIT(6), /* port connect change status */
PORT_IRQ_SG_DONE = BIT(5), /* descriptor processed */
PORT_IRQ_UNK_FIS = BIT(4), /* unknown FIS rx'd */
PORT_IRQ_SDB_FIS = BIT(3), /* Set Device Bits FIS rx'd */
PORT_IRQ_DMAS_FIS = BIT(2), /* DMA Setup FIS rx'd */
PORT_IRQ_PIOS_FIS = BIT(1), /* PIO Setup FIS rx'd */
PORT_IRQ_D2H_REG_FIS = BIT(0), /* D2H Register FIS rx'd */
PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
PORT_IRQ_IF_ERR |
@@ -161,27 +162,27 @@ enum {
PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
/* PORT_CMD bits */
PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
PORT_CMD_ESP = (1 << 21), /* External Sata Port */
PORT_CMD_CPD = (1 << 20), /* Cold Presence Detection */
PORT_CMD_MPSP = (1 << 19), /* Mechanical Presence Switch */
PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */
PORT_CMD_PMP = (1 << 17), /* PMP attached */
PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
PORT_CMD_CLO = (1 << 3), /* Command list override */
PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
PORT_CMD_ASP = BIT(27), /* Aggressive Slumber/Partial */
PORT_CMD_ALPE = BIT(26), /* Aggressive Link PM enable */
PORT_CMD_ATAPI = BIT(24), /* Device is ATAPI */
PORT_CMD_FBSCP = BIT(22), /* FBS Capable Port */
PORT_CMD_ESP = BIT(21), /* External Sata Port */
PORT_CMD_CPD = BIT(20), /* Cold Presence Detection */
PORT_CMD_MPSP = BIT(19), /* Mechanical Presence Switch */
PORT_CMD_HPCP = BIT(18), /* HotPlug Capable Port */
PORT_CMD_PMP = BIT(17), /* PMP attached */
PORT_CMD_LIST_ON = BIT(15), /* cmd list DMA engine running */
PORT_CMD_FIS_ON = BIT(14), /* FIS DMA engine running */
PORT_CMD_FIS_RX = BIT(4), /* Enable FIS receive DMA engine */
PORT_CMD_CLO = BIT(3), /* Command list override */
PORT_CMD_POWER_ON = BIT(2), /* Power up device */
PORT_CMD_SPIN_UP = BIT(1), /* Spin up device */
PORT_CMD_START = BIT(0), /* Enable port DMA engine */
PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
PORT_CMD_ICC_MASK = (0xfu << 28), /* i/f ICC state mask */
PORT_CMD_ICC_ACTIVE = (0x1u << 28), /* Put i/f in active state */
PORT_CMD_ICC_PARTIAL = (0x2u << 28), /* Put i/f in partial state */
PORT_CMD_ICC_SLUMBER = (0x6u << 28), /* Put i/f in slumber state */
/* PORT_CMD capabilities mask */
PORT_CMD_CAP = PORT_CMD_HPCP | PORT_CMD_MPSP |
@@ -192,9 +193,9 @@ enum {
PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
PORT_FBS_SDE = (1 << 2), /* FBS single device error */
PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
PORT_FBS_EN = (1 << 0), /* Enable FBS */
PORT_FBS_SDE = BIT(2), /* FBS single device error */
PORT_FBS_DEC = BIT(1), /* FBS device error clear */
PORT_FBS_EN = BIT(0), /* Enable FBS */
/* PORT_DEVSLP bits */
PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */
@@ -202,50 +203,50 @@ enum {
PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */
PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */
PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */
PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */
PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */
PORT_DEVSLP_DSP = BIT(1), /* DevSlp present */
PORT_DEVSLP_ADSE = BIT(0), /* Aggressive DevSlp enable */
/* hpriv->flags bits */
#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
AHCI_HFLAG_NO_NCQ = (1 << 0),
AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
link offline */
AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */
AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */
AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on
port start (wait until
error-handling stage) */
AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */
AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */
AHCI_HFLAG_NO_NCQ = BIT(0),
AHCI_HFLAG_IGN_IRQ_IF_ERR = BIT(1), /* ignore IRQ_IF_ERR */
AHCI_HFLAG_IGN_SERR_INTERNAL = BIT(2), /* ignore SERR_INTERNAL */
AHCI_HFLAG_32BIT_ONLY = BIT(3), /* force 32bit */
AHCI_HFLAG_MV_PATA = BIT(4), /* PATA port */
AHCI_HFLAG_NO_MSI = BIT(5), /* no PCI MSI */
AHCI_HFLAG_NO_PMP = BIT(6), /* no PMP */
AHCI_HFLAG_SECT255 = BIT(8), /* max 255 sectors */
AHCI_HFLAG_YES_NCQ = BIT(9), /* force NCQ cap on */
AHCI_HFLAG_NO_SUSPEND = BIT(10), /* don't suspend */
AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = BIT(11), /* treat SRST timeout as
link offline */
AHCI_HFLAG_NO_SNTF = BIT(12), /* no sntf */
AHCI_HFLAG_NO_FPDMA_AA = BIT(13), /* no FPDMA AA */
AHCI_HFLAG_YES_FBS = BIT(14), /* force FBS cap on */
AHCI_HFLAG_DELAY_ENGINE = BIT(15), /* do not start engine on
port start (wait until
error-handling stage) */
AHCI_HFLAG_NO_DEVSLP = BIT(17), /* no device sleep */
AHCI_HFLAG_NO_FBS = BIT(18), /* no FBS */
#ifdef CONFIG_PCI_MSI
AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */
AHCI_HFLAG_MULTI_MSI = BIT(20), /* per-port MSI(-X) */
#else
/* compile out MSI infrastructure */
AHCI_HFLAG_MULTI_MSI = 0,
#endif
AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */
AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */
AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
only registers */
AHCI_HFLAG_USE_LPM_POLICY = (1 << 25), /* chipset that should use
SATA_MOBILE_LPM_POLICY
as default lpm_policy */
AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
suspend/resume */
AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */
AHCI_HFLAG_WAKE_BEFORE_STOP = BIT(22), /* wake before DMA stop */
AHCI_HFLAG_YES_ALPM = BIT(23), /* force ALPM cap on */
AHCI_HFLAG_NO_WRITE_TO_RO = BIT(24), /* don't write to read
only registers */
AHCI_HFLAG_USE_LPM_POLICY = BIT(25), /* chipset that should use
SATA_MOBILE_LPM_POLICY
as default lpm_policy */
AHCI_HFLAG_SUSPEND_PHYS = BIT(26), /* handle PHYs during
suspend/resume */
AHCI_HFLAG_NO_SXS = BIT(28), /* SXS not supported */
/* ap->flags bits */
@@ -261,22 +262,22 @@ enum {
EM_MAX_RETRY = 5,
/* em_ctl bits */
EM_CTL_RST = (1 << 9), /* Reset */
EM_CTL_TM = (1 << 8), /* Transmit Message */
EM_CTL_MR = (1 << 0), /* Message Received */
EM_CTL_ALHD = (1 << 26), /* Activity LED */
EM_CTL_XMT = (1 << 25), /* Transmit Only */
EM_CTL_SMB = (1 << 24), /* Single Message Buffer */
EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */
EM_CTL_SES = (1 << 18), /* SES-2 messages supported */
EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */
EM_CTL_LED = (1 << 16), /* LED messages supported */
EM_CTL_RST = BIT(9), /* Reset */
EM_CTL_TM = BIT(8), /* Transmit Message */
EM_CTL_MR = BIT(0), /* Message Received */
EM_CTL_ALHD = BIT(26), /* Activity LED */
EM_CTL_XMT = BIT(25), /* Transmit Only */
EM_CTL_SMB = BIT(24), /* Single Message Buffer */
EM_CTL_SGPIO = BIT(19), /* SGPIO messages supported */
EM_CTL_SES = BIT(18), /* SES-2 messages supported */
EM_CTL_SAFTE = BIT(17), /* SAF-TE messages supported */
EM_CTL_LED = BIT(16), /* LED messages supported */
/* em message type */
EM_MSG_TYPE_LED = (1 << 0), /* LED */
EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */
EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */
EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */
EM_MSG_TYPE_LED = BIT(0), /* LED */
EM_MSG_TYPE_SAFTE = BIT(1), /* SAF-TE */
EM_MSG_TYPE_SES2 = BIT(2), /* SES-2 */
EM_MSG_TYPE_SGPIO = BIT(3), /* SGPIO */
};
struct ahci_cmd_hdr {
drivers/ata/libahci.c
+17 -3
View File
@@ -2071,6 +2071,20 @@ static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
!(qc->flags & ATA_QCFLAG_FAILED)) {
ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15];
/*
* For NCQ commands, we never get a D2H FIS, so reading the D2H Register
* FIS area of the Received FIS Structure (which contains a copy of the
* last D2H FIS received) will contain an outdated status code.
* For NCQ commands, we instead get a SDB FIS, so read the SDB FIS area
* instead. However, the SDB FIS does not contain the LBA, so we can't
* use the ata_tf_from_fis() helper.
*/
} else if (ata_is_ncq(qc->tf.protocol)) {
const u8 *fis = rx_fis + RX_FIS_SDB;
qc->result_tf.status = fis[2];
qc->result_tf.error = fis[3];
} else
ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
@@ -2106,7 +2120,7 @@ void ahci_error_handler(struct ata_port *ap)
{
struct ahci_host_priv *hpriv = ap->host->private_data;
if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
if (!ata_port_is_frozen(ap)) {
/* restart engine */
hpriv->stop_engine(ap);
hpriv->start_engine(ap);
@@ -2297,7 +2311,7 @@ static void ahci_pmp_attach(struct ata_port *ap)
* Note that during initialization, the port is marked as
* frozen since the irq handler is not yet registered.
*/
if (!(ap->pflags & ATA_PFLAG_FROZEN))
if (!ata_port_is_frozen(ap))
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
}
@@ -2316,7 +2330,7 @@ static void ahci_pmp_detach(struct ata_port *ap)
pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
/* see comment above in ahci_pmp_attach() */
if (!(ap->pflags & ATA_PFLAG_FROZEN))
if (!ata_port_is_frozen(ap))
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
}
drivers/ata/libata-acpi.c
+2 -2
View File
@@ -992,7 +992,7 @@ int ata_acpi_on_devcfg(struct ata_device *dev)
acpi_err:
/* ignore evaluation failure if we can continue safely */
if (rc == -EINVAL && !nr_executed && !(ap->pflags & ATA_PFLAG_FROZEN))
if (rc == -EINVAL && !nr_executed && !ata_port_is_frozen(ap))
return 0;
/* fail and let EH retry once more for unknown IO errors */
@@ -1007,7 +1007,7 @@ int ata_acpi_on_devcfg(struct ata_device *dev)
/* We can safely continue if no _GTF command has been executed
* and port is not frozen.
*/
if (!nr_executed && !(ap->pflags & ATA_PFLAG_FROZEN))
if (!nr_executed && !ata_port_is_frozen(ap))
return 0;
return rc;
drivers/ata/libata-core.c
+4 -3
View File
@@ -1489,7 +1489,7 @@ static unsigned ata_exec_internal_sg(struct ata_device *dev,
spin_lock_irqsave(ap->lock, flags);
/* no internal command while frozen */
if (ap->pflags & ATA_PFLAG_FROZEN) {
if (ata_port_is_frozen(ap)) {
spin_unlock_irqrestore(ap->lock, flags);
return AC_ERR_SYSTEM;
}
@@ -2000,7 +2000,8 @@ retry:
if (err_mask) {
if (dma) {
dev->horkage |= ATA_HORKAGE_NO_DMA_LOG;
goto retry;
if (!ata_port_is_frozen(dev->link->ap))
goto retry;
}
ata_dev_err(dev,
"Read log 0x%02x page 0x%02x failed, Emask 0x%x\n",
@@ -4721,7 +4722,7 @@ void ata_qc_complete(struct ata_queued_cmd *qc)
return;
}
WARN_ON_ONCE(ap->pflags & ATA_PFLAG_FROZEN);
WARN_ON_ONCE(ata_port_is_frozen(ap));
/* read result TF if requested */
if (qc->flags & ATA_QCFLAG_RESULT_TF)
drivers/ata/libata-eh.c
+25 -17
View File
@@ -1406,7 +1406,7 @@ static void ata_eh_request_sense(struct ata_queued_cmd *qc)
struct ata_taskfile tf;
unsigned int err_mask;
if (qc->ap->pflags & ATA_PFLAG_FROZEN) {
if (ata_port_is_frozen(qc->ap)) {
ata_dev_warn(dev, "sense data available but port frozen\n");
return;
}
@@ -1428,8 +1428,10 @@ static void ata_eh_request_sense(struct ata_queued_cmd *qc)
err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
/* Ignore err_mask; ATA_ERR might be set */
if (tf.status & ATA_SENSE) {
ata_scsi_set_sense(dev, cmd, tf.lbah, tf.lbam, tf.lbal);
qc->flags |= ATA_QCFLAG_SENSE_VALID;
if (ata_scsi_sense_is_valid(tf.lbah, tf.lbam, tf.lbal)) {
ata_scsi_set_sense(dev, cmd, tf.lbah, tf.lbam, tf.lbal);
qc->flags |= ATA_QCFLAG_SENSE_VALID;
}
} else {
ata_dev_warn(dev, "request sense failed stat %02x emask %x\n",
tf.status, err_mask);
@@ -1574,11 +1576,17 @@ static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc)
}
switch (qc->dev->class) {
case ATA_DEV_ZAC:
if (stat & ATA_SENSE)
ata_eh_request_sense(qc);
fallthrough;
case ATA_DEV_ATA:
case ATA_DEV_ZAC:
/*
* Fetch the sense data explicitly if:
* -It was a non-NCQ command that failed, or
* -It was a NCQ command that failed, but the sense data
* was not included in the NCQ command error log
* (i.e. NCQ autosense is not supported by the device).
*/
if (!(qc->flags & ATA_QCFLAG_SENSE_VALID) && (stat & ATA_SENSE))
ata_eh_request_sense(qc);
if (err & ATA_ICRC)
qc->err_mask |= AC_ERR_ATA_BUS;
if (err & (ATA_UNC | ATA_AMNF))
@@ -1588,7 +1596,7 @@ static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc)
break;
case ATA_DEV_ATAPI:
if (!(qc->ap->pflags & ATA_PFLAG_FROZEN)) {
if (!ata_port_is_frozen(qc->ap)) {
tmp = atapi_eh_request_sense(qc->dev,
qc->scsicmd->sense_buffer,
qc->result_tf.error >> 4);
@@ -1947,6 +1955,7 @@ static void ata_eh_link_autopsy(struct ata_link *link)
ata_qc_for_each_raw(ap, qc, tag) {
if (!(qc->flags & ATA_QCFLAG_FAILED) ||
qc->flags & ATA_QCFLAG_RETRY ||
ata_dev_phys_link(qc->dev) != link)
continue;
@@ -1995,7 +2004,7 @@ static void ata_eh_link_autopsy(struct ata_link *link)
ehc->i.flags |= ATA_EHI_QUIET;
/* enforce default EH actions */
if (ap->pflags & ATA_PFLAG_FROZEN ||
if (ata_port_is_frozen(ap) ||
all_err_mask & (AC_ERR_HSM | AC_ERR_TIMEOUT))
ehc->i.action |= ATA_EH_RESET;
else if (((eflags & ATA_EFLAG_IS_IO) && all_err_mask) ||
@@ -2238,7 +2247,7 @@ static void ata_eh_link_report(struct ata_link *link)
return;
frozen = "";
if (ap->pflags & ATA_PFLAG_FROZEN)
if (ata_port_is_frozen(ap))
frozen = " frozen";
if (ap->eh_tries < ATA_EH_MAX_TRIES)
@@ -2559,8 +2568,7 @@ int ata_eh_reset(struct ata_link *link, int classify,
if (reset && !(ehc->i.action & ATA_EH_RESET)) {
ata_for_each_dev(dev, link, ALL)
classes[dev->devno] = ATA_DEV_NONE;
if ((ap->pflags & ATA_PFLAG_FROZEN) &&
ata_is_host_link(link))
if (ata_port_is_frozen(ap) && ata_is_host_link(link))
ata_eh_thaw_port(ap);
rc = 0;
goto out;
@@ -2718,7 +2726,7 @@ int ata_eh_reset(struct ata_link *link, int classify,
ap->pflags &= ~ATA_PFLAG_EH_PENDING;
spin_unlock_irqrestore(link->ap->lock, flags);
if (ap->pflags & ATA_PFLAG_FROZEN)
if (ata_port_is_frozen(ap))
ata_eh_thaw_port(ap);
/*
@@ -3225,7 +3233,7 @@ static int ata_eh_maybe_retry_flush(struct ata_device *dev)
if (err_mask & AC_ERR_DEV) {
qc->err_mask |= AC_ERR_DEV;
qc->result_tf = tf;
if (!(ap->pflags & ATA_PFLAG_FROZEN))
if (!ata_port_is_frozen(ap))
rc = 0;
}
}
@@ -3402,7 +3410,7 @@ static int ata_eh_skip_recovery(struct ata_link *link)
return 1;
/* thaw frozen port and recover failed devices */
if ((ap->pflags & ATA_PFLAG_FROZEN) || ata_link_nr_enabled(link))
if (ata_port_is_frozen(ap) || ata_link_nr_enabled(link))
return 0;
/* reset at least once if reset is requested */
@@ -3757,7 +3765,7 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
if (dev)
ata_eh_handle_dev_fail(dev, rc);
if (ap->pflags & ATA_PFLAG_FROZEN) {
if (ata_port_is_frozen(ap)) {
/* PMP reset requires working host port.
* Can't retry if it's frozen.
*/
@@ -3931,7 +3939,7 @@ static void ata_eh_handle_port_suspend(struct ata_port *ap)
ap->pflags &= ~ATA_PFLAG_PM_PENDING;
if (rc == 0)
ap->pflags |= ATA_PFLAG_SUSPENDED;
else if (ap->pflags & ATA_PFLAG_FROZEN)
else if (ata_port_is_frozen(ap))
ata_port_schedule_eh(ap);
spin_unlock_irqrestore(ap->lock, flags);
drivers/ata/libata-sata.c
+42 -8
View File
@@ -1392,7 +1392,7 @@ static int ata_eh_read_log_10h(struct ata_device *dev,
tf->hob_lbah = buf[10];
tf->nsect = buf[12];
tf->hob_nsect = buf[13];
if (dev->class == ATA_DEV_ZAC && ata_id_has_ncq_autosense(dev->id))
if (ata_id_has_ncq_autosense(dev->id) && (tf->status & ATA_SENSE))
tf->auxiliary = buf[14] << 16 | buf[15] << 8 | buf[16];
return 0;
@@ -1420,7 +1420,7 @@ void ata_eh_analyze_ncq_error(struct ata_link *link)
int tag, rc;
/* if frozen, we can't do much */
if (ap->pflags & ATA_PFLAG_FROZEN)
if (ata_port_is_frozen(ap))
return;
/* is it NCQ device error? */
@@ -1456,17 +1456,51 @@ void ata_eh_analyze_ncq_error(struct ata_link *link)
memcpy(&qc->result_tf, &tf, sizeof(tf));
qc->result_tf.flags = ATA_TFLAG_ISADDR | ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
qc->err_mask |= AC_ERR_DEV | AC_ERR_NCQ;
if (dev->class == ATA_DEV_ZAC &&
((qc->result_tf.status & ATA_SENSE) || qc->result_tf.auxiliary)) {
/*
* If the device supports NCQ autosense, ata_eh_read_log_10h() will have
* stored the sense data in qc->result_tf.auxiliary.
*/
if (qc->result_tf.auxiliary) {
char sense_key, asc, ascq;
sense_key = (qc->result_tf.auxiliary >> 16) & 0xff;
asc = (qc->result_tf.auxiliary >> 8) & 0xff;
ascq = qc->result_tf.auxiliary & 0xff;
ata_scsi_set_sense(dev, qc->scsicmd, sense_key, asc, ascq);
ata_scsi_set_sense_information(dev, qc->scsicmd,
&qc->result_tf);
qc->flags |= ATA_QCFLAG_SENSE_VALID;
if (ata_scsi_sense_is_valid(sense_key, asc, ascq)) {
ata_scsi_set_sense(dev, qc->scsicmd, sense_key, asc,
ascq);
ata_scsi_set_sense_information(dev, qc->scsicmd,
&qc->result_tf);
qc->flags |= ATA_QCFLAG_SENSE_VALID;
}
}
ata_qc_for_each_raw(ap, qc, tag) {
if (!(qc->flags & ATA_QCFLAG_FAILED) ||
ata_dev_phys_link(qc->dev) != link)
continue;
/* Skip the single QC which caused the NCQ error. */
if (qc->err_mask)
continue;
/*
* For SATA, the STATUS and ERROR fields are shared for all NCQ
* commands that were completed with the same SDB FIS.
* Therefore, we have to clear the ATA_ERR bit for all QCs
* except the one that caused the NCQ error.
*/
qc->result_tf.status &= ~ATA_ERR;
qc->result_tf.error = 0;
/*
* If we get a NCQ error, that means that a single command was
* aborted. All other failed commands for our link should be
* retried and has no business of going though further scrutiny
* by ata_eh_link_autopsy().
*/
qc->flags |= ATA_QCFLAG_RETRY;
}
ehc->i.err_mask &= ~AC_ERR_DEV;
drivers/ata/libata-scsi.c
+17 -1
View File
@@ -188,6 +188,22 @@ DEVICE_ATTR(unload_heads, S_IRUGO | S_IWUSR,
ata_scsi_park_show, ata_scsi_park_store);
EXPORT_SYMBOL_GPL(dev_attr_unload_heads);
bool ata_scsi_sense_is_valid(u8 sk, u8 asc, u8 ascq)
{
/*
* If sk == NO_SENSE, and asc + ascq == NO ADDITIONAL SENSE INFORMATION,
* then there is no sense data to add.
*/
if (sk == 0 && asc == 0 && ascq == 0)
return false;
/* If sk > COMPLETED, sense data is bogus. */
if (sk > COMPLETED)
return false;
return true;
}
void ata_scsi_set_sense(struct ata_device *dev, struct scsi_cmnd *cmd,
u8 sk, u8 asc, u8 ascq)
{
@@ -642,7 +658,7 @@ static struct ata_queued_cmd *ata_scsi_qc_new(struct ata_device *dev,
struct ata_queued_cmd *qc;
int tag;
if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
if (unlikely(ata_port_is_frozen(ap)))
goto fail;
if (ap->flags & ATA_FLAG_SAS_HOST) {
drivers/ata/libata-sff.c
-56
View File
@@ -184,62 +184,6 @@ void ata_sff_dma_pause(struct ata_port *ap)
}
EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
/**
* ata_sff_busy_sleep - sleep until BSY clears, or timeout
* @ap: port containing status register to be polled
* @tmout_pat: impatience timeout in msecs
* @tmout: overall timeout in msecs
*
* Sleep until ATA Status register bit BSY clears,
* or a timeout occurs.
*
* LOCKING:
* Kernel thread context (may sleep).
*
* RETURNS:
* 0 on success, -errno otherwise.
*/
int ata_sff_busy_sleep(struct ata_port *ap,
unsigned long tmout_pat, unsigned long tmout)
{
unsigned long timer_start, timeout;
u8 status;
status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
timer_start = jiffies;
timeout = ata_deadline(timer_start, tmout_pat);
while (status != 0xff && (status & ATA_BUSY) &&
time_before(jiffies, timeout)) {
ata_msleep(ap, 50);
status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
}
if (status != 0xff && (status & ATA_BUSY))
ata_port_warn(ap,
"port is slow to respond, please be patient (Status 0x%x)\n",
status);
timeout = ata_deadline(timer_start, tmout);
while (status != 0xff && (status & ATA_BUSY) &&
time_before(jiffies, timeout)) {
ata_msleep(ap, 50);
status = ap->ops->sff_check_status(ap);
}
if (status == 0xff)
return -ENODEV;
if (status & ATA_BUSY) {
ata_port_err(ap,
"port failed to respond (%lu secs, Status 0x%x)\n",
DIV_ROUND_UP(tmout, 1000), status);
return -EBUSY;
}
return 0;
}
EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
static int ata_sff_check_ready(struct ata_link *link)
{
u8 status = link->ap->ops->sff_check_status(link->ap);
drivers/ata/libata.h
+1
View File
@@ -114,6 +114,7 @@ extern int ata_scsi_add_hosts(struct ata_host *host,
struct scsi_host_template *sht);
extern void ata_scsi_scan_host(struct ata_port *ap, int sync);
extern int ata_scsi_offline_dev(struct ata_device *dev);
extern bool ata_scsi_sense_is_valid(u8 sk, u8 asc, u8 ascq);
extern void ata_scsi_set_sense(struct ata_device *dev,
struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq);
extern void ata_scsi_set_sense_information(struct ata_device *dev,
drivers/ata/pata_bk3710.c
-380
View File
@@ -1,380 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Palmchip BK3710 PATA controller driver
*
* Copyright (c) 2017 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Based on palm_bk3710.c:
*
* Copyright (C) 2006 Texas Instruments.
* Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
*/
#include <linux/ata.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/libata.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#define DRV_NAME "pata_bk3710"
#define BK3710_TF_OFFSET 0x1F0
#define BK3710_CTL_OFFSET 0x3F6
#define BK3710_BMISP 0x02
#define BK3710_IDETIMP 0x40
#define BK3710_UDMACTL 0x48
#define BK3710_MISCCTL 0x50
#define BK3710_REGSTB 0x54
#define BK3710_REGRCVR 0x58
#define BK3710_DATSTB 0x5C
#define BK3710_DATRCVR 0x60
#define BK3710_DMASTB 0x64
#define BK3710_DMARCVR 0x68
#define BK3710_UDMASTB 0x6C
#define BK3710_UDMATRP 0x70
#define BK3710_UDMAENV 0x74
#define BK3710_IORDYTMP 0x78
static struct scsi_host_template pata_bk3710_sht = {
ATA_BMDMA_SHT(DRV_NAME),
};
static unsigned int ideclk_period; /* in nanoseconds */
struct pata_bk3710_udmatiming {
unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
/* tENV is always a minimum of 20 nsec */
};
static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = {
{ 160, 240 / 2 }, /* UDMA Mode 0 */
{ 125, 160 / 2 }, /* UDMA Mode 1 */
{ 100, 120 / 2 }, /* UDMA Mode 2 */
{ 100, 90 / 2 }, /* UDMA Mode 3 */
{ 100, 60 / 2 }, /* UDMA Mode 4 */
{ 85, 40 / 2 }, /* UDMA Mode 5 */
};
static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev,
unsigned int mode)
{
u32 val32;
u16 val16;
u8 tenv, trp, t0;
/* DMA Data Setup */
t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime,
ideclk_period) - 1;
tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime,
ideclk_period) - 1;
/* udmastb Ultra DMA Access Strobe Width */
val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
val32 |= t0 << (dev ? 8 : 0);
iowrite32(val32, base + BK3710_UDMASTB);
/* udmatrp Ultra DMA Ready to Pause Time */
val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
val32 |= trp << (dev ? 8 : 0);
iowrite32(val32, base + BK3710_UDMATRP);
/* udmaenv Ultra DMA envelop Time */
val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
val32 |= tenv << (dev ? 8 : 0);
iowrite32(val32, base + BK3710_UDMAENV);
/* Enable UDMA for Device */
val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev);
iowrite16(val16, base + BK3710_UDMACTL);
}
static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev,
unsigned short min_cycle,
unsigned int mode)
{
const struct ata_timing *t;
int cycletime;
u32 val32;
u16 val16;
u8 td, tkw, t0;
t = ata_timing_find_mode(mode);
cycletime = max_t(int, t->cycle, min_cycle);
/* DMA Data Setup */
t0 = DIV_ROUND_UP(cycletime, ideclk_period);
td = DIV_ROUND_UP(t->active, ideclk_period);
tkw = t0 - td - 1;
td--;
val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
val32 |= td << (dev ? 8 : 0);
iowrite32(val32, base + BK3710_DMASTB);
val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
val32 |= tkw << (dev ? 8 : 0);
iowrite32(val32, base + BK3710_DMARCVR);
/* Disable UDMA for Device */
val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev);
iowrite16(val16, base + BK3710_UDMACTL);
}
static void pata_bk3710_set_dmamode(struct ata_port *ap,
struct ata_device *adev)
{
void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
int is_slave = adev->devno;
const u8 xferspeed = adev->dma_mode;
if (xferspeed >= XFER_UDMA_0)
pata_bk3710_setudmamode(base, is_slave,
xferspeed - XFER_UDMA_0);
else
pata_bk3710_setmwdmamode(base, is_slave,
adev->id[ATA_ID_EIDE_DMA_MIN],
xferspeed);
}
static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair,
unsigned int dev, unsigned int cycletime,
unsigned int mode)
{
const struct ata_timing *t;
u32 val32;
u8 t2, t2i, t0;
t = ata_timing_find_mode(XFER_PIO_0 + mode);
/* PIO Data Setup */
t0 = DIV_ROUND_UP(cycletime, ideclk_period);
t2 = DIV_ROUND_UP(t->active, ideclk_period);
t2i = t0 - t2 - 1;
t2--;
val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
val32 |= t2 << (dev ? 8 : 0);
iowrite32(val32, base + BK3710_DATSTB);
val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
val32 |= t2i << (dev ? 8 : 0);
iowrite32(val32, base + BK3710_DATRCVR);
/* FIXME: this is broken also in the old driver */
if (pair) {
u8 mode2 = pair->pio_mode - XFER_PIO_0;
if (mode2 < mode)
mode = mode2;
}
/* TASKFILE Setup */
t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
t2i = t0 - t2 - 1;
t2--;
val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
val32 |= t2 << (dev ? 8 : 0);
iowrite32(val32, base + BK3710_REGSTB);
val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
val32 |= t2i << (dev ? 8 : 0);
iowrite32(val32, base + BK3710_REGRCVR);
}
static void pata_bk3710_set_piomode(struct ata_port *ap,
struct ata_device *adev)
{
void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
struct ata_device *pair = ata_dev_pair(adev);
const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode);
const u16 *id = adev->id;
unsigned int cycle_time = 0;
int is_slave = adev->devno;
const u8 pio = adev->pio_mode - XFER_PIO_0;
if (id[ATA_ID_FIELD_VALID] & 2) {
if (ata_id_has_iordy(id))
cycle_time = id[ATA_ID_EIDE_PIO_IORDY];
else
cycle_time = id[ATA_ID_EIDE_PIO];
/* conservative "downgrade" for all pre-ATA2 drives */
if (pio < 3 && cycle_time < t->cycle)
cycle_time = 0; /* use standard timing */
}
if (!cycle_time)
cycle_time = t->cycle;
pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio);
}
static void pata_bk3710_chipinit(void __iomem *base)
{
/*
* REVISIT: the ATA reset signal needs to be managed through a
* GPIO, which means it should come from platform_data. Until
* we get and use such information, we have to trust that things
* have been reset before we get here.
*/
/*
* Program the IDETIMP Register Value based on the following assumptions
*
* (ATA_IDETIMP_IDEEN , ENABLE ) |
* (ATA_IDETIMP_PREPOST1 , DISABLE) |
* (ATA_IDETIMP_PREPOST0 , DISABLE) |
*
* DM6446 silicon rev 2.1 and earlier have no observed net benefit
* from enabling prefetch/postwrite.
*/
iowrite16(BIT(15), base + BK3710_IDETIMP);
/*
* UDMACTL Ultra-ATA DMA Control
* (ATA_UDMACTL_UDMAP1 , 0 ) |
* (ATA_UDMACTL_UDMAP0 , 0 )
*
*/
iowrite16(0, base + BK3710_UDMACTL);
/*
* MISCCTL Miscellaneous Conrol Register
* (ATA_MISCCTL_HWNHLD1P , 1 cycle)
* (ATA_MISCCTL_HWNHLD0P , 1 cycle)
* (ATA_MISCCTL_TIMORIDE , 1)
*/
iowrite32(0x001, base + BK3710_MISCCTL);
/*
* IORDYTMP IORDY Timer for Primary Register
* (ATA_IORDYTMP_IORDYTMP , DISABLE)
*/
iowrite32(0, base + BK3710_IORDYTMP);
/*
* Configure BMISP Register
* (ATA_BMISP_DMAEN1 , DISABLE ) |
* (ATA_BMISP_DMAEN0 , DISABLE ) |
* (ATA_BMISP_IORDYINT , CLEAR) |
* (ATA_BMISP_INTRSTAT , CLEAR) |
* (ATA_BMISP_DMAERROR , CLEAR)
*/
iowrite16(0xE, base + BK3710_BMISP);
pata_bk3710_setpiomode(base, NULL, 0, 600, 0);
pata_bk3710_setpiomode(base, NULL, 1, 600, 0);
}
static struct ata_port_operations pata_bk3710_ports_ops = {
.inherits = &ata_bmdma_port_ops,
.cable_detect = ata_cable_80wire,
.set_piomode = pata_bk3710_set_piomode,
.set_dmamode = pata_bk3710_set_dmamode,
};
static int __init pata_bk3710_probe(struct platform_device *pdev)
{
struct clk *clk;
struct resource *mem;
struct ata_host *host;
struct ata_port *ap;
void __iomem *base;
unsigned long rate;
int irq;
clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(clk))
return -ENODEV;
clk_enable(clk);
rate = clk_get_rate(clk);
if (!rate)
return -EINVAL;
/* NOTE: round *down* to meet minimum timings; we count in clocks */
ideclk_period = 1000000000UL / rate;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
pr_err(DRV_NAME ": failed to get IRQ resource\n");
return irq;
}
base = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(base))
return PTR_ERR(base);
/* configure the Palmchip controller */
pata_bk3710_chipinit(base);
/* allocate host */
host = ata_host_alloc(&pdev->dev, 1);
if (!host)
return -ENOMEM;
ap = host->ports[0];
ap->ops = &pata_bk3710_ports_ops;
ap->pio_mask = ATA_PIO4;
ap->mwdma_mask = ATA_MWDMA2;
ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5;
ap->flags |= ATA_FLAG_SLAVE_POSS;
ap->ioaddr.data_addr = base + BK3710_TF_OFFSET;
ap->ioaddr.error_addr = base + BK3710_TF_OFFSET + 1;
ap->ioaddr.feature_addr = base + BK3710_TF_OFFSET + 1;
ap->ioaddr.nsect_addr = base + BK3710_TF_OFFSET + 2;
ap->ioaddr.lbal_addr = base + BK3710_TF_OFFSET + 3;
ap->ioaddr.lbam_addr = base + BK3710_TF_OFFSET + 4;
ap->ioaddr.lbah_addr = base + BK3710_TF_OFFSET + 5;
ap->ioaddr.device_addr = base + BK3710_TF_OFFSET + 6;
ap->ioaddr.status_addr = base + BK3710_TF_OFFSET + 7;
ap->ioaddr.command_addr = base + BK3710_TF_OFFSET + 7;
ap->ioaddr.altstatus_addr = base + BK3710_CTL_OFFSET;
ap->ioaddr.ctl_addr = base + BK3710_CTL_OFFSET;
ap->ioaddr.bmdma_addr = base;
ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
(unsigned long)base + BK3710_TF_OFFSET,
(unsigned long)base + BK3710_CTL_OFFSET);
/* activate */
return ata_host_activate(host, irq, ata_sff_interrupt, 0,
&pata_bk3710_sht);
}
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:palm_bk3710");
static struct platform_driver pata_bk3710_driver = {
.driver = {
.name = "palm_bk3710",
},
};
static int __init pata_bk3710_init(void)
{
return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe);
}
module_init(pata_bk3710_init);
MODULE_LICENSE("GPL v2");
drivers/ata/pata_ep93xx.c
+1 -2
View File
@@ -931,8 +931,7 @@ static int ep93xx_pata_probe(struct platform_device *pdev)
goto err_rel_gpio;
}
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ide_base = devm_ioremap_resource(&pdev->dev, mem_res);
ide_base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
if (IS_ERR(ide_base)) {
err = PTR_ERR(ide_base);
goto err_rel_gpio;
drivers/ata/pata_ftide010.c
+1 -1
View File
@@ -560,7 +560,7 @@ static const struct of_device_id pata_ftide010_of_match[] = {
static struct platform_driver pata_ftide010_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(pata_ftide010_of_match),
.of_match_table = pata_ftide010_of_match,
},
.probe = pata_ftide010_probe,
.remove = pata_ftide010_remove,
drivers/ata/pata_mpc52xx.c
+1 -1
View File
@@ -731,7 +731,7 @@ static int mpc52xx_ata_probe(struct platform_device *op)
udma_mask = ATA_UDMA2 & ((1 << (*prop + 1)) - 1);
ata_irq = irq_of_parse_and_map(op->dev.of_node, 0);
if (ata_irq == NO_IRQ) {
if (!ata_irq) {
dev_err(&op->dev, "error mapping irq\n");
return -EINVAL;
}
drivers/ata/sata_dwc_460ex.c
+3 -9
View File
@@ -42,10 +42,6 @@
#define sata_dwc_writel(a, v) writel_relaxed(v, a)
#define sata_dwc_readl(a) readl_relaxed(a)
#ifndef NO_IRQ
#define NO_IRQ 0
#endif
#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
enum {
@@ -242,7 +238,7 @@ static int sata_dwc_dma_init_old(struct platform_device *pdev,
/* Get SATA DMA interrupt number */
hsdev->dma->irq = irq_of_parse_and_map(np, 1);
if (hsdev->dma->irq == NO_IRQ) {
if (!hsdev->dma->irq) {
dev_err(dev, "no SATA DMA irq\n");
return -ENODEV;
}
@@ -472,7 +468,7 @@ static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
struct ata_queued_cmd *qc;
unsigned long flags;
u8 status, tag;
int handled, num_processed, port = 0;
int handled, port = 0;
uint intpr, sactive, sactive2, tag_mask;
struct sata_dwc_device_port *hsdevp;
hsdev->sactive_issued = 0;
@@ -618,9 +614,7 @@ DRVSTILLBUSY:
dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
tag = 0;
num_processed = 0;
while (tag_mask) {
num_processed++;
while (!(tag_mask & 0x00000001)) {
tag++;
tag_mask <<= 1;
@@ -1180,7 +1174,7 @@ static int sata_dwc_probe(struct platform_device *ofdev)
/* Get SATA interrupt number */
irq = irq_of_parse_and_map(np, 0);
if (irq == NO_IRQ) {
if (!irq) {
dev_err(dev, "no SATA DMA irq\n");
return -ENODEV;
}
drivers/ata/sata_gemini.c
+1 -1
View File
@@ -421,7 +421,7 @@ static const struct of_device_id gemini_sata_of_match[] = {
static struct platform_driver gemini_sata_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(gemini_sata_of_match),
.of_match_table = gemini_sata_of_match,
},
.probe = gemini_sata_probe,
.remove = gemini_sata_remove,
drivers/ata/sata_nv.c
+1 -1
View File
@@ -2185,7 +2185,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
if (!fis)
return;
if (ap->pflags & ATA_PFLAG_FROZEN)
if (ata_port_is_frozen(ap))
return;
if (fis & NV_SWNCQ_IRQ_HOTPLUG) {
drivers/ata/sata_promise.c
+1 -1
View File
@@ -817,7 +817,7 @@ static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
static void pdc_error_handler(struct ata_port *ap)
{
if (!(ap->pflags & ATA_PFLAG_FROZEN))
if (!ata_port_is_frozen(ap))
pdc_reset_port(ap);
ata_sff_error_handler(ap);
drivers/ata/sata_sx4.c
+1 -1
View File
@@ -855,7 +855,7 @@ static int pdc_softreset(struct ata_link *link, unsigned int *class,
static void pdc_error_handler(struct ata_port *ap)
{
if (!(ap->pflags & ATA_PFLAG_FROZEN))
if (!ata_port_is_frozen(ap))
pdc_reset_port(ap);
ata_sff_error_handler(ap);
drivers/scsi/libsas/sas_ata.c
+1 -1
View File
@@ -101,7 +101,7 @@ static void sas_ata_task_done(struct sas_task *task)
spin_lock_irqsave(ap->lock, flags);
/* check if we lost the race with libata/sas_ata_post_internal() */
if (unlikely(ap->pflags & ATA_PFLAG_FROZEN)) {
if (unlikely(ata_port_is_frozen(ap))) {
spin_unlock_irqrestore(ap->lock, flags);
if (qc->scsicmd)
goto qc_already_gone;
include/linux/ata.h
-31
View File
@@ -615,15 +615,6 @@ static inline bool ata_id_has_flush(const u16 *id)
return id[ATA_ID_COMMAND_SET_2] & (1 << 12);
}
static inline bool ata_id_flush_enabled(const u16 *id)
{
if (ata_id_has_flush(id) == 0)
return false;
if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
return false;
return id[ATA_ID_CFS_ENABLE_2] & (1 << 12);
}
static inline bool ata_id_has_flush_ext(const u16 *id)
{
if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
@@ -631,19 +622,6 @@ static inline bool ata_id_has_flush_ext(const u16 *id)
return id[ATA_ID_COMMAND_SET_2] & (1 << 13);
}
static inline bool ata_id_flush_ext_enabled(const u16 *id)
{
if (ata_id_has_flush_ext(id) == 0)
return false;
if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
return false;
/*
* some Maxtor disks have bit 13 defined incorrectly
* so check bit 10 too
*/
return (id[ATA_ID_CFS_ENABLE_2] & 0x2400) == 0x2400;
}
static inline u32 ata_id_logical_sector_size(const u16 *id)
{
/* T13/1699-D Revision 6a, Sep 6, 2008. Page 128.
@@ -698,15 +676,6 @@ static inline bool ata_id_has_lba48(const u16 *id)
return id[ATA_ID_COMMAND_SET_2] & (1 << 10);
}
static inline bool ata_id_lba48_enabled(const u16 *id)
{
if (ata_id_has_lba48(id) == 0)
return false;
if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
return false;
return id[ATA_ID_CFS_ENABLE_2] & (1 << 10);
}
static inline bool ata_id_hpa_enabled(const u16 *id)
{
/* Yes children, word 83 valid bits cover word 82 data */
include/linux/libata.h
+5 -2
View File
@@ -1043,6 +1043,11 @@ static inline int ata_port_is_dummy(struct ata_port *ap)
return ap->ops == &ata_dummy_port_ops;
}
static inline bool ata_port_is_frozen(const struct ata_port *ap)
{
return ap->pflags & ATA_PFLAG_FROZEN;
}
extern int ata_std_prereset(struct ata_link *link, unsigned long deadline);
extern int ata_wait_after_reset(struct ata_link *link, unsigned long deadline,
int (*check_ready)(struct ata_link *link));
@@ -1913,8 +1918,6 @@ extern void ata_sff_dev_select(struct ata_port *ap, unsigned int device);
extern u8 ata_sff_check_status(struct ata_port *ap);
extern void ata_sff_pause(struct ata_port *ap);
extern void ata_sff_dma_pause(struct ata_port *ap);
extern int ata_sff_busy_sleep(struct ata_port *ap,
unsigned long timeout_pat, unsigned long timeout);
extern int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline);
extern void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf);
extern void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
include/scsi/scsi_proto.h
+2 -2
View File
@@ -205,10 +205,10 @@ enum sam_status {
};
#define STATUS_MASK 0xfe
/*
* SENSE KEYS
*/
#define NO_SENSE 0x00
#define RECOVERED_ERROR 0x01
#define NOT_READY 0x02
@@ -223,7 +223,7 @@ enum sam_status {
#define ABORTED_COMMAND 0x0b
#define VOLUME_OVERFLOW 0x0d
#define MISCOMPARE 0x0e
#define COMPLETED 0x0f
/*
* DEVICE TYPES