drm/etnaviv: Disable SH_EU clock gating on VIPNano-Si+
Disable SH_EU clock gating for the VIPNano-Si+ NPU on i.MX8MP and for other affected core revisions. Taken from linux-imx lf-6.1.36-2.1.0, specifically [1]. [1] https://github.com/nxp-imx/linux-imx/blob/lf-6.1.36-2.1.0/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c#L2747-L2761 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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Lucas Stach
parent
37d5927a85
commit
e843e87abb
@@ -654,6 +654,12 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
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pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
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VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
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/* Disable SH_EU clock gating on affected core revisions. */
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if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) ||
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etnaviv_is_model_rev(gpu, 0x8000, 0x8002) ||
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etnaviv_is_model_rev(gpu, 0x9200, 0x6304))
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pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU;
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pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
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pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
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