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PCI: tegra: Fix incorrect CLKREQ and PLLE programming

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CLKREQ_EN bit should be cleared to control REFCLK through CLKREQ# pin.
Enable PCIE2PLLE bit to control PLLE through clock clamp signal.
Program PADS2PLLE and PCIE2PLLE bits only if Tegra PCIe supports L1SS.

bug 200420606

Change-Id: I04cacf64fce8eed0f17bb632457ffcc9f052819d
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786550
(cherry picked from commit e71a64e47225b848c9b8a1d33e8c80a7bdb9d3cc)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407876
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Manikanta Maddireddy
2018-07-17 23:39:55 +05:30
committed by Thomas Makin
parent 00f1cf7c84
commit e3a136b7a7
1 changed files with 6 additions and 2 deletions
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8
drivers/pci/controller/pci-tegra.c
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@@ -163,7 +163,9 @@
#define AFI_PLLE_CONTROL 0x160 #define AFI_PLLE_CONTROL 0x160
#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
#define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8)
#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
#define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0)
#define AFI_PEXBIAS_CTRL_0 0x168 #define AFI_PEXBIAS_CTRL_0 0x168
@@ -896,7 +898,7 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
value |= AFI_PEX_CTRL_REFCLK_EN; value |= AFI_PEX_CTRL_REFCLK_EN;
if (soc->has_pex_clkreq_en) if (soc->has_pex_clkreq_en)
value |= AFI_PEX_CTRL_CLKREQ_EN; value &= ~AFI_PEX_CTRL_CLKREQ_EN;
value |= AFI_PEX_CTRL_OVERRIDE_EN; value |= AFI_PEX_CTRL_OVERRIDE_EN;
@@ -1326,10 +1328,12 @@ static void tegra_pcie_enable_controller(struct tegra_pcie *pcie)
unsigned long value; unsigned long value;
/* enable PLL power down */ /* enable PLL power down */
if (pcie->phy) { if (soc->has_aspm_l1ss) {
value = afi_readl(pcie, AFI_PLLE_CONTROL); value = afi_readl(pcie, AFI_PLLE_CONTROL);
value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
value &= ~AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL;
value |= AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN;
afi_writel(pcie, value, AFI_PLLE_CONTROL); afi_writel(pcie, value, AFI_PLLE_CONTROL);
} }