From e3a136b7a73dfabb6c6f412b8f49ffd9a02e8bf5 Mon Sep 17 00:00:00 2001 From: Manikanta Maddireddy Date: Tue, 17 Jul 2018 23:39:55 +0530 Subject: [PATCH] PCI: tegra: Fix incorrect CLKREQ and PLLE programming CLKREQ_EN bit should be cleared to control REFCLK through CLKREQ# pin. Enable PCIE2PLLE bit to control PLLE through clock clamp signal. Program PADS2PLLE and PCIE2PLLE bits only if Tegra PCIe supports L1SS. bug 200420606 Change-Id: I04cacf64fce8eed0f17bb632457ffcc9f052819d Signed-off-by: Manikanta Maddireddy Reviewed-on: https://git-master.nvidia.com/r/1786550 (cherry picked from commit e71a64e47225b848c9b8a1d33e8c80a7bdb9d3cc) Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407876 Reviewed-by: Bitan Biswas Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/pci/controller/pci-tegra.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 4d8045b67291..e97cf6f71e32 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -163,7 +163,9 @@ #define AFI_PLLE_CONTROL 0x160 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) +#define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) +#define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) #define AFI_PEXBIAS_CTRL_0 0x168 @@ -896,7 +898,7 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port) value |= AFI_PEX_CTRL_REFCLK_EN; if (soc->has_pex_clkreq_en) - value |= AFI_PEX_CTRL_CLKREQ_EN; + value &= ~AFI_PEX_CTRL_CLKREQ_EN; value |= AFI_PEX_CTRL_OVERRIDE_EN; @@ -1326,10 +1328,12 @@ static void tegra_pcie_enable_controller(struct tegra_pcie *pcie) unsigned long value; /* enable PLL power down */ - if (pcie->phy) { + if (soc->has_aspm_l1ss) { value = afi_readl(pcie, AFI_PLLE_CONTROL); value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; + value &= ~AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL; + value |= AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN; afi_writel(pcie, value, AFI_PLLE_CONTROL); }