BACKPORT: FROMLIST: iommu/io-pgtable-arm: Split the page table driver
To allow the KVM IOMMU driver to populate page tables using the io-pgtable-arm code, move the shared bits into io-pgtable-arm-common.c. Here we move the bulk of the common code, and a subsequent patch handles the bits that require more care. phys_to_virt() and virt_to_phys() do need special handling here because the hypervisor will have its own version. It will also implement its own version of __arm_lpae_alloc_pages(), __arm_lpae_free_pages() and __arm_lpae_sync_pte() since the hypervisor needs some assistance for allocating pages. Some other minor changes around mapping existing or unmapping empty PTEs as WARN_ON is fatal in the hypervisor. Link: https://lore.kernel.org/all/20241212180423.1578358-2-smostafa@google.com/ Bug: 357781595 Bug: 384432312 Change-Id: I42ce5fc61a594d9ebf66a74eaa30aaccd7eb8d14 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Signed-off-by: Mostafa Saleh <smostafa@google.com>
This commit is contained in:
Jean-Philippe Brucker
committed by
Mostafa Saleh
Mostafa Saleh
parent
7a77fcee95
commit
cb4ade8d9b
@@ -7,7 +7,7 @@ obj-$(CONFIG_IOMMU_DEBUGFS) += iommu-debugfs.o
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obj-$(CONFIG_IOMMU_DMA) += dma-iommu.o
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obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o
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obj-$(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) += io-pgtable-arm-v7s.o
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obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o
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obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o io-pgtable-arm-common.o
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obj-$(CONFIG_IOMMU_IO_PGTABLE_DART) += io-pgtable-dart.o
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obj-$(CONFIG_IOMMU_IOVA) += iova.o
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obj-$(CONFIG_OF_IOMMU) += of_iommu.o
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@@ -11,7 +11,7 @@
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#include <kunit/visibility.h>
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#include "arm-smmu-v3.h"
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#include "../../io-pgtable-arm.h"
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#include <linux/io-pgtable-arm.h>
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static DEFINE_MUTEX(sva_lock);
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@@ -0,0 +1,587 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* CPU-agnostic ARM page table allocator.
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* A copy of this library is embedded in the KVM nVHE image.
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*
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* Copyright (C) 2022 Arm Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#include <linux/io-pgtable-arm.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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#define iopte_deref(pte, d) __arm_lpae_phys_to_virt(iopte_to_paddr(pte, d))
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static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr,
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struct arm_lpae_io_pgtable *data)
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{
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arm_lpae_iopte pte = paddr;
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/* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */
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return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK;
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}
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static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte,
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struct arm_lpae_io_pgtable *data)
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{
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u64 paddr = pte & ARM_LPAE_PTE_ADDR_MASK;
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if (ARM_LPAE_GRANULE(data) < SZ_64K)
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return paddr;
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/* Rotate the packed high-order bits back to the top */
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return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4);
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}
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/*
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* Convert an index returned by ARM_LPAE_PGD_IDX(), which can point into
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* a concatenated PGD, into the maximum number of entries that can be
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* mapped in the same table page.
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*/
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static inline int arm_lpae_max_entries(int i, struct arm_lpae_io_pgtable *data)
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{
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int ptes_per_table = ARM_LPAE_PTES_PER_TABLE(data);
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return ptes_per_table - (i & (ptes_per_table - 1));
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}
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static void __arm_lpae_clear_pte(arm_lpae_iopte *ptep, struct io_pgtable_cfg *cfg, int num_entries)
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{
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for (int i = 0; i < num_entries; i++)
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ptep[i] = 0;
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if (!cfg->coherent_walk && num_entries)
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__arm_lpae_sync_pte(ptep, num_entries, cfg);
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}
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static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
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struct iommu_iotlb_gather *gather,
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unsigned long iova, size_t size, size_t pgcount,
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int lvl, arm_lpae_iopte *ptep);
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static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
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phys_addr_t paddr, arm_lpae_iopte prot,
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int lvl, int num_entries, arm_lpae_iopte *ptep)
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{
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arm_lpae_iopte pte = prot;
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struct io_pgtable_cfg *cfg = &data->iop.cfg;
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size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
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int i;
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if (data->iop.fmt != ARM_MALI_LPAE && lvl == ARM_LPAE_MAX_LEVELS - 1)
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pte |= ARM_LPAE_PTE_TYPE_PAGE;
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else
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pte |= ARM_LPAE_PTE_TYPE_BLOCK;
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for (i = 0; i < num_entries; i++)
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ptep[i] = pte | paddr_to_iopte(paddr + i * sz, data);
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if (!cfg->coherent_walk)
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__arm_lpae_sync_pte(ptep, num_entries, cfg);
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}
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static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
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unsigned long iova, phys_addr_t paddr,
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arm_lpae_iopte prot, int lvl, int num_entries,
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arm_lpae_iopte *ptep)
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{
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int i;
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for (i = 0; i < num_entries; i++)
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if (iopte_leaf(ptep[i], lvl, data->iop.fmt)) {
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/* We require an unmap first */
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return arm_lpae_map_exists();
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} else if (iopte_type(ptep[i]) == ARM_LPAE_PTE_TYPE_TABLE) {
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/*
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* We need to unmap and free the old table before
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* overwriting it with a block entry.
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*/
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arm_lpae_iopte *tblp;
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size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
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tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
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if (__arm_lpae_unmap(data, NULL, iova + i * sz, sz, 1,
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lvl, tblp) != sz) {
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WARN_ON(1);
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return -EINVAL;
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}
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}
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__arm_lpae_init_pte(data, paddr, prot, lvl, num_entries, ptep);
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return 0;
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}
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static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table,
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arm_lpae_iopte *ptep,
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arm_lpae_iopte curr,
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struct arm_lpae_io_pgtable *data)
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{
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arm_lpae_iopte old, new;
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struct io_pgtable_cfg *cfg = &data->iop.cfg;
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new = paddr_to_iopte(__arm_lpae_virt_to_phys(table), data) |
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ARM_LPAE_PTE_TYPE_TABLE;
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if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
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new |= ARM_LPAE_PTE_NSTABLE;
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/*
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* Ensure the table itself is visible before its PTE can be.
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* Whilst we could get away with cmpxchg64_release below, this
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* doesn't have any ordering semantics when !CONFIG_SMP.
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*/
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dma_wmb();
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old = cmpxchg64_relaxed(ptep, curr, new);
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if (cfg->coherent_walk || (old & ARM_LPAE_PTE_SW_SYNC))
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return old;
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/* Even if it's not ours, there's no point waiting; just kick it */
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__arm_lpae_sync_pte(ptep, 1, cfg);
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if (old == curr)
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WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC);
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return old;
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}
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static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
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phys_addr_t paddr, size_t size, size_t pgcount,
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arm_lpae_iopte prot, int lvl, arm_lpae_iopte *ptep,
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gfp_t gfp, size_t *mapped)
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{
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arm_lpae_iopte *cptep, pte;
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size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
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size_t tblsz = ARM_LPAE_GRANULE(data);
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struct io_pgtable_cfg *cfg = &data->iop.cfg;
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int ret = 0, num_entries, max_entries, map_idx_start;
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/* Find our entry at the current level */
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map_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data);
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ptep += map_idx_start;
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/* If we can install a leaf entry at this level, then do so */
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if (size == block_size) {
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max_entries = arm_lpae_max_entries(map_idx_start, data);
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num_entries = min_t(int, pgcount, max_entries);
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ret = arm_lpae_init_pte(data, iova, paddr, prot, lvl, num_entries, ptep);
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if (!ret)
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*mapped += num_entries * size;
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return ret;
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}
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/* We can't allocate tables at the final level */
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if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
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return -EINVAL;
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/* Grab a pointer to the next level */
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pte = READ_ONCE(*ptep);
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if (!pte) {
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cptep = __arm_lpae_alloc_pages(tblsz, gfp, cfg, data->iop.cookie);
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if (!cptep)
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return -ENOMEM;
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pte = arm_lpae_install_table(cptep, ptep, 0, data);
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if (pte)
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__arm_lpae_free_pages(cptep, tblsz, cfg, data->iop.cookie);
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} else if (!cfg->coherent_walk && !(pte & ARM_LPAE_PTE_SW_SYNC)) {
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__arm_lpae_sync_pte(ptep, 1, cfg);
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}
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if (pte && !iopte_leaf(pte, lvl, data->iop.fmt)) {
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cptep = iopte_deref(pte, data);
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} else if (pte) {
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/* We require an unmap first */
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return arm_lpae_unmap_empty();
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}
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/* Rinse, repeat */
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return __arm_lpae_map(data, iova, paddr, size, pgcount, prot, lvl + 1,
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cptep, gfp, mapped);
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}
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static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
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int prot)
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{
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arm_lpae_iopte pte;
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if (data->iop.fmt == ARM_64_LPAE_S1 ||
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data->iop.fmt == ARM_32_LPAE_S1) {
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pte = ARM_LPAE_PTE_nG;
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if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
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pte |= ARM_LPAE_PTE_AP_RDONLY;
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else if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_HD)
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pte |= ARM_LPAE_PTE_DBM;
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if (!(prot & IOMMU_PRIV))
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pte |= ARM_LPAE_PTE_AP_UNPRIV;
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} else {
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pte = ARM_LPAE_PTE_HAP_FAULT;
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if (prot & IOMMU_READ)
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pte |= ARM_LPAE_PTE_HAP_READ;
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if (prot & IOMMU_WRITE)
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pte |= ARM_LPAE_PTE_HAP_WRITE;
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}
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/*
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* Note that this logic is structured to accommodate Mali LPAE
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* having stage-1-like attributes but stage-2-like permissions.
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*/
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if (data->iop.fmt == ARM_64_LPAE_S2 ||
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data->iop.fmt == ARM_32_LPAE_S2) {
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if (prot & IOMMU_MMIO)
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pte |= ARM_LPAE_PTE_MEMATTR_DEV;
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else if (prot & IOMMU_CACHE)
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pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
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else
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pte |= ARM_LPAE_PTE_MEMATTR_NC;
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} else {
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if (prot & IOMMU_MMIO)
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pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
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<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
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else if (prot & IOMMU_CACHE)
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pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
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<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
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}
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/*
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* Also Mali has its own notions of shareability wherein its Inner
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* domain covers the cores within the GPU, and its Outer domain is
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* "outside the GPU" (i.e. either the Inner or System domain in CPU
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* terms, depending on coherency).
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*/
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if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
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pte |= ARM_LPAE_PTE_SH_IS;
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else
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pte |= ARM_LPAE_PTE_SH_OS;
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if (prot & IOMMU_NOEXEC)
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pte |= ARM_LPAE_PTE_XN;
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if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS)
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pte |= ARM_LPAE_PTE_NS;
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if (data->iop.fmt != ARM_MALI_LPAE)
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pte |= ARM_LPAE_PTE_AF;
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return pte;
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}
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int arm_lpae_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
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phys_addr_t paddr, size_t pgsize, size_t pgcount,
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int iommu_prot, gfp_t gfp, size_t *mapped)
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{
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struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
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struct io_pgtable_cfg *cfg = &data->iop.cfg;
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arm_lpae_iopte *ptep = data->pgd;
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int ret, lvl = data->start_level;
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arm_lpae_iopte prot;
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long iaext = (s64)iova >> cfg->ias;
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if (WARN_ON(!pgsize || (pgsize & cfg->pgsize_bitmap) != pgsize))
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return -EINVAL;
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if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
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iaext = ~iaext;
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if (WARN_ON(iaext || paddr >> cfg->oas))
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return -ERANGE;
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if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
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return -EINVAL;
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prot = arm_lpae_prot_to_pte(data, iommu_prot);
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ret = __arm_lpae_map(data, iova, paddr, pgsize, pgcount, prot, lvl,
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ptep, gfp, mapped);
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/*
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* Synchronise all PTE updates for the new mapping before there's
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* a chance for anything to kick off a table walk for the new iova.
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*/
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wmb();
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return ret;
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}
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void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
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arm_lpae_iopte *ptep)
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{
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arm_lpae_iopte *start, *end;
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unsigned long table_size;
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if (lvl == data->start_level)
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table_size = ARM_LPAE_PGD_SIZE(data);
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else
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table_size = ARM_LPAE_GRANULE(data);
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start = ptep;
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/* Only leaf entries at the last level */
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if (lvl == ARM_LPAE_MAX_LEVELS - 1)
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end = ptep;
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else
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end = (void *)ptep + table_size;
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while (ptep != end) {
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arm_lpae_iopte pte = *ptep++;
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if (!pte || iopte_leaf(pte, lvl, data->iop.fmt))
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continue;
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__arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
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}
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__arm_lpae_free_pages(start, table_size, &data->iop.cfg, data->iop.cookie);
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}
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static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
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struct iommu_iotlb_gather *gather,
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unsigned long iova, size_t size,
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arm_lpae_iopte blk_pte, int lvl,
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arm_lpae_iopte *ptep, size_t pgcount)
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{
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struct io_pgtable_cfg *cfg = &data->iop.cfg;
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arm_lpae_iopte pte, *tablep;
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phys_addr_t blk_paddr;
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size_t tablesz = ARM_LPAE_GRANULE(data);
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size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
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int ptes_per_table = ARM_LPAE_PTES_PER_TABLE(data);
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int i, unmap_idx_start = -1, num_entries = 0, max_entries;
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if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
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return 0;
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tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg, data->iop.cookie);
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if (!tablep)
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return 0; /* Bytes unmapped */
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if (size == split_sz) {
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unmap_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data);
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max_entries = arm_lpae_max_entries(unmap_idx_start, data);
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num_entries = min_t(int, pgcount, max_entries);
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}
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blk_paddr = iopte_to_paddr(blk_pte, data);
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pte = iopte_prot(blk_pte);
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for (i = 0; i < ptes_per_table; i++, blk_paddr += split_sz) {
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/* Unmap! */
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if (i >= unmap_idx_start && i < (unmap_idx_start + num_entries))
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continue;
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__arm_lpae_init_pte(data, blk_paddr, pte, lvl, 1, &tablep[i]);
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}
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pte = arm_lpae_install_table(tablep, ptep, blk_pte, data);
|
||||
if (pte != blk_pte) {
|
||||
__arm_lpae_free_pages(tablep, tablesz, cfg, data->iop.cookie);
|
||||
/*
|
||||
* We may race against someone unmapping another part of this
|
||||
* block, but anything else is invalid. We can't misinterpret
|
||||
* a page entry here since we're never at the last level.
|
||||
*/
|
||||
if (iopte_type(pte) != ARM_LPAE_PTE_TYPE_TABLE)
|
||||
return 0;
|
||||
|
||||
tablep = iopte_deref(pte, data);
|
||||
} else if (unmap_idx_start >= 0) {
|
||||
for (i = 0; i < num_entries; i++)
|
||||
io_pgtable_tlb_add_page(&data->iop, gather, iova + i * size, size);
|
||||
|
||||
return num_entries * size;
|
||||
}
|
||||
|
||||
return __arm_lpae_unmap(data, gather, iova, size, pgcount, lvl, tablep);
|
||||
}
|
||||
|
||||
static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
|
||||
struct iommu_iotlb_gather *gather,
|
||||
unsigned long iova, size_t size, size_t pgcount,
|
||||
int lvl, arm_lpae_iopte *ptep)
|
||||
{
|
||||
arm_lpae_iopte pte;
|
||||
struct io_pgtable *iop = &data->iop;
|
||||
int i = 0, num_entries, max_entries, unmap_idx_start;
|
||||
|
||||
/* Something went horribly wrong and we ran out of page table */
|
||||
if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
|
||||
return 0;
|
||||
|
||||
unmap_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data);
|
||||
ptep += unmap_idx_start;
|
||||
pte = READ_ONCE(*ptep);
|
||||
if (WARN_ON(!pte))
|
||||
return 0;
|
||||
|
||||
/* If the size matches this level, we're in the right place */
|
||||
if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) {
|
||||
max_entries = arm_lpae_max_entries(unmap_idx_start, data);
|
||||
num_entries = min_t(int, pgcount, max_entries);
|
||||
|
||||
/* Find and handle non-leaf entries */
|
||||
for (i = 0; i < num_entries; i++) {
|
||||
pte = READ_ONCE(ptep[i]);
|
||||
if (WARN_ON(!pte))
|
||||
break;
|
||||
|
||||
if (!iopte_leaf(pte, lvl, iop->fmt)) {
|
||||
__arm_lpae_clear_pte(&ptep[i], &iop->cfg, 1);
|
||||
|
||||
/* Also flush any partial walks */
|
||||
io_pgtable_tlb_flush_walk(iop, iova + i * size, size,
|
||||
ARM_LPAE_GRANULE(data));
|
||||
__arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the remaining entries */
|
||||
__arm_lpae_clear_pte(ptep, &iop->cfg, i);
|
||||
|
||||
if (gather && !iommu_iotlb_gather_queued(gather))
|
||||
for (int j = 0; j < i; j++)
|
||||
io_pgtable_tlb_add_page(iop, gather, iova + j * size, size);
|
||||
|
||||
return i * size;
|
||||
} else if (iopte_leaf(pte, lvl, iop->fmt)) {
|
||||
/*
|
||||
* Insert a table at the next level to map the old region,
|
||||
* minus the part we want to unmap
|
||||
*/
|
||||
return arm_lpae_split_blk_unmap(data, gather, iova, size, pte,
|
||||
lvl + 1, ptep, pgcount);
|
||||
}
|
||||
|
||||
/* Keep on walkin' */
|
||||
ptep = iopte_deref(pte, data);
|
||||
return __arm_lpae_unmap(data, gather, iova, size, pgcount, lvl + 1, ptep);
|
||||
}
|
||||
|
||||
size_t arm_lpae_unmap_pages(struct io_pgtable_ops *ops, unsigned long iova,
|
||||
size_t pgsize, size_t pgcount,
|
||||
struct iommu_iotlb_gather *gather)
|
||||
{
|
||||
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
||||
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
||||
arm_lpae_iopte *ptep = data->pgd;
|
||||
long iaext = (s64)iova >> cfg->ias;
|
||||
|
||||
if (WARN_ON(!pgsize || (pgsize & cfg->pgsize_bitmap) != pgsize || !pgcount))
|
||||
return 0;
|
||||
|
||||
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
|
||||
iaext = ~iaext;
|
||||
if (WARN_ON(iaext))
|
||||
return 0;
|
||||
|
||||
return __arm_lpae_unmap(data, gather, iova, pgsize, pgcount,
|
||||
data->start_level, ptep);
|
||||
}
|
||||
|
||||
struct iova_to_phys_data {
|
||||
arm_lpae_iopte pte;
|
||||
int lvl;
|
||||
};
|
||||
|
||||
static int visit_iova_to_phys(struct io_pgtable_walk_data *walk_data, int lvl,
|
||||
arm_lpae_iopte *ptep, size_t size)
|
||||
{
|
||||
struct iova_to_phys_data *data = walk_data->data;
|
||||
data->pte = *ptep;
|
||||
data->lvl = lvl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
|
||||
unsigned long iova)
|
||||
{
|
||||
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
||||
struct iova_to_phys_data d;
|
||||
struct io_pgtable_walk_data walk_data = {
|
||||
.data = &d,
|
||||
.visit = visit_iova_to_phys,
|
||||
.addr = iova,
|
||||
.end = iova + 1,
|
||||
};
|
||||
int ret;
|
||||
|
||||
ret = __arm_lpae_iopte_walk(data, &walk_data, data->pgd, data->start_level);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
iova &= (ARM_LPAE_BLOCK_SIZE(d.lvl, data) - 1);
|
||||
return iopte_to_paddr(d.pte, data) | iova;
|
||||
}
|
||||
|
||||
static int visit_pgtable_walk(struct io_pgtable_walk_data *walk_data, int lvl,
|
||||
arm_lpae_iopte *ptep, size_t size)
|
||||
{
|
||||
struct arm_lpae_io_pgtable_walk_data *data = walk_data->data;
|
||||
data->ptes[data->level++] = *ptep;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arm_lpae_pgtable_walk(struct io_pgtable_ops *ops, unsigned long iova, void *wd)
|
||||
{
|
||||
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
||||
struct io_pgtable_walk_data walk_data = {
|
||||
.data = wd,
|
||||
.visit = visit_pgtable_walk,
|
||||
.addr = iova,
|
||||
.end = iova + 1,
|
||||
};
|
||||
|
||||
((struct arm_lpae_io_pgtable_walk_data *)wd)->level = 0;
|
||||
|
||||
return __arm_lpae_iopte_walk(data, &walk_data, data->pgd, data->start_level);
|
||||
}
|
||||
|
||||
static int io_pgtable_visit(struct arm_lpae_io_pgtable *data,
|
||||
struct io_pgtable_walk_data *walk_data,
|
||||
arm_lpae_iopte *ptep, int lvl)
|
||||
{
|
||||
struct io_pgtable *iop = &data->iop;
|
||||
arm_lpae_iopte pte = READ_ONCE(*ptep);
|
||||
|
||||
size_t size = ARM_LPAE_BLOCK_SIZE(lvl, data);
|
||||
int ret = walk_data->visit(walk_data, lvl, ptep, size);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (iopte_leaf(pte, lvl, iop->fmt)) {
|
||||
walk_data->addr += size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!iopte_table(pte, lvl)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ptep = iopte_deref(pte, data);
|
||||
return __arm_lpae_iopte_walk(data, walk_data, ptep, lvl + 1);
|
||||
}
|
||||
|
||||
int __arm_lpae_iopte_walk(struct arm_lpae_io_pgtable *data,
|
||||
struct io_pgtable_walk_data *walk_data,
|
||||
arm_lpae_iopte *ptep,
|
||||
int lvl)
|
||||
{
|
||||
u32 idx;
|
||||
int max_entries, ret;
|
||||
|
||||
if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
|
||||
return -EINVAL;
|
||||
|
||||
if (lvl == data->start_level)
|
||||
max_entries = ARM_LPAE_PGD_SIZE(data) / sizeof(arm_lpae_iopte);
|
||||
else
|
||||
max_entries = ARM_LPAE_PTES_PER_TABLE(data);
|
||||
|
||||
for (idx = ARM_LPAE_LVL_IDX(walk_data->addr, lvl, data);
|
||||
(idx < max_entries) && (walk_data->addr < walk_data->end); ++idx) {
|
||||
ret = io_pgtable_visit(data, walk_data, ptep + idx, lvl);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
+26
-754
@@ -1,6 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* CPU-agnostic ARM page table allocator.
|
||||
* Host-specific functions. The rest is in io-pgtable-arm-common.c.
|
||||
*
|
||||
* Copyright (C) 2014 ARM Limited
|
||||
*
|
||||
@@ -11,7 +12,7 @@
|
||||
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/io-pgtable.h>
|
||||
#include <linux/io-pgtable-arm.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/slab.h>
|
||||
@@ -20,207 +21,33 @@
|
||||
|
||||
#include <asm/barrier.h>
|
||||
|
||||
#include "io-pgtable-arm.h"
|
||||
#include "iommu-pages.h"
|
||||
|
||||
#define ARM_LPAE_MAX_ADDR_BITS 52
|
||||
#define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
|
||||
#define ARM_LPAE_MAX_LEVELS 4
|
||||
|
||||
/* Struct accessors */
|
||||
#define io_pgtable_to_data(x) \
|
||||
container_of((x), struct arm_lpae_io_pgtable, iop)
|
||||
|
||||
#define io_pgtable_ops_to_data(x) \
|
||||
io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
|
||||
|
||||
/*
|
||||
* Calculate the right shift amount to get to the portion describing level l
|
||||
* in a virtual address mapped by the pagetable in d.
|
||||
*/
|
||||
#define ARM_LPAE_LVL_SHIFT(l,d) \
|
||||
(((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level) + \
|
||||
ilog2(sizeof(arm_lpae_iopte)))
|
||||
|
||||
#define ARM_LPAE_GRANULE(d) \
|
||||
(sizeof(arm_lpae_iopte) << (d)->bits_per_level)
|
||||
#define ARM_LPAE_PGD_SIZE(d) \
|
||||
(sizeof(arm_lpae_iopte) << (d)->pgd_bits)
|
||||
|
||||
#define ARM_LPAE_PTES_PER_TABLE(d) \
|
||||
(ARM_LPAE_GRANULE(d) >> ilog2(sizeof(arm_lpae_iopte)))
|
||||
|
||||
/*
|
||||
* Calculate the index at level l used to map virtual address a using the
|
||||
* pagetable in d.
|
||||
*/
|
||||
#define ARM_LPAE_PGD_IDX(l,d) \
|
||||
((l) == (d)->start_level ? (d)->pgd_bits - (d)->bits_per_level : 0)
|
||||
|
||||
#define ARM_LPAE_LVL_IDX(a,l,d) \
|
||||
(((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
|
||||
((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
|
||||
|
||||
/* Calculate the block/page mapping size at level l for pagetable in d. */
|
||||
#define ARM_LPAE_BLOCK_SIZE(l,d) (1ULL << ARM_LPAE_LVL_SHIFT(l,d))
|
||||
|
||||
/* Page table bits */
|
||||
#define ARM_LPAE_PTE_TYPE_SHIFT 0
|
||||
#define ARM_LPAE_PTE_TYPE_MASK 0x3
|
||||
|
||||
#define ARM_LPAE_PTE_TYPE_BLOCK 1
|
||||
#define ARM_LPAE_PTE_TYPE_TABLE 3
|
||||
#define ARM_LPAE_PTE_TYPE_PAGE 3
|
||||
|
||||
#define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12)
|
||||
|
||||
#define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
|
||||
#define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
|
||||
#define ARM_LPAE_PTE_DBM (((arm_lpae_iopte)1) << 51)
|
||||
#define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
|
||||
#define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
|
||||
#define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
|
||||
#define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
|
||||
#define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
|
||||
#define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
|
||||
|
||||
#define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
|
||||
/* Ignore the contiguous bit for block splitting */
|
||||
#define ARM_LPAE_PTE_ATTR_HI_MASK (ARM_LPAE_PTE_XN | ARM_LPAE_PTE_DBM)
|
||||
#define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
|
||||
ARM_LPAE_PTE_ATTR_HI_MASK)
|
||||
/* Software bit for solving coherency races */
|
||||
#define ARM_LPAE_PTE_SW_SYNC (((arm_lpae_iopte)1) << 55)
|
||||
|
||||
/* Stage-1 PTE */
|
||||
#define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
|
||||
#define ARM_LPAE_PTE_AP_RDONLY_BIT 7
|
||||
#define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)1) << \
|
||||
ARM_LPAE_PTE_AP_RDONLY_BIT)
|
||||
#define ARM_LPAE_PTE_AP_WR_CLEAN_MASK (ARM_LPAE_PTE_AP_RDONLY | \
|
||||
ARM_LPAE_PTE_DBM)
|
||||
#define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
|
||||
#define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
|
||||
|
||||
/* Stage-2 PTE */
|
||||
#define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
|
||||
#define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
|
||||
#define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
|
||||
#define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
|
||||
#define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
|
||||
#define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
|
||||
|
||||
/* Register bits */
|
||||
#define ARM_LPAE_VTCR_SL0_MASK 0x3
|
||||
|
||||
#define ARM_LPAE_TCR_T0SZ_SHIFT 0
|
||||
|
||||
#define ARM_LPAE_VTCR_PS_SHIFT 16
|
||||
#define ARM_LPAE_VTCR_PS_MASK 0x7
|
||||
|
||||
#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
|
||||
#define ARM_LPAE_MAIR_ATTR_MASK 0xff
|
||||
#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
|
||||
#define ARM_LPAE_MAIR_ATTR_NC 0x44
|
||||
#define ARM_LPAE_MAIR_ATTR_INC_OWBRWA 0xf4
|
||||
#define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
|
||||
#define ARM_LPAE_MAIR_ATTR_IDX_NC 0
|
||||
#define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
|
||||
#define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
|
||||
#define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE 3
|
||||
|
||||
#define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0)
|
||||
#define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2)
|
||||
#define ARM_MALI_LPAE_TTBR_SHARE_OUTER BIT(4)
|
||||
|
||||
#define ARM_MALI_LPAE_MEMATTR_IMP_DEF 0x88ULL
|
||||
#define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL
|
||||
|
||||
/* IOPTE accessors */
|
||||
#define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
|
||||
|
||||
#define iopte_type(pte) \
|
||||
(((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
|
||||
|
||||
#define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
|
||||
|
||||
#define iopte_writeable_dirty(pte) \
|
||||
(((pte) & ARM_LPAE_PTE_AP_WR_CLEAN_MASK) == ARM_LPAE_PTE_DBM)
|
||||
|
||||
#define iopte_set_writeable_clean(ptep) \
|
||||
set_bit(ARM_LPAE_PTE_AP_RDONLY_BIT, (unsigned long *)(ptep))
|
||||
|
||||
struct arm_lpae_io_pgtable {
|
||||
struct io_pgtable iop;
|
||||
|
||||
int pgd_bits;
|
||||
int start_level;
|
||||
int bits_per_level;
|
||||
|
||||
void *pgd;
|
||||
};
|
||||
|
||||
typedef u64 arm_lpae_iopte;
|
||||
|
||||
static inline bool iopte_leaf(arm_lpae_iopte pte, int lvl,
|
||||
enum io_pgtable_fmt fmt)
|
||||
{
|
||||
if (lvl == (ARM_LPAE_MAX_LEVELS - 1) && fmt != ARM_MALI_LPAE)
|
||||
return iopte_type(pte) == ARM_LPAE_PTE_TYPE_PAGE;
|
||||
|
||||
return iopte_type(pte) == ARM_LPAE_PTE_TYPE_BLOCK;
|
||||
}
|
||||
|
||||
static inline bool iopte_table(arm_lpae_iopte pte, int lvl)
|
||||
{
|
||||
if (lvl == (ARM_LPAE_MAX_LEVELS - 1))
|
||||
return false;
|
||||
return iopte_type(pte) == ARM_LPAE_PTE_TYPE_TABLE;
|
||||
}
|
||||
|
||||
static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr,
|
||||
struct arm_lpae_io_pgtable *data)
|
||||
{
|
||||
arm_lpae_iopte pte = paddr;
|
||||
|
||||
/* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */
|
||||
return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK;
|
||||
}
|
||||
|
||||
static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte,
|
||||
struct arm_lpae_io_pgtable *data)
|
||||
{
|
||||
u64 paddr = pte & ARM_LPAE_PTE_ADDR_MASK;
|
||||
|
||||
if (ARM_LPAE_GRANULE(data) < SZ_64K)
|
||||
return paddr;
|
||||
|
||||
/* Rotate the packed high-order bits back to the top */
|
||||
return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4);
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert an index returned by ARM_LPAE_PGD_IDX(), which can point into
|
||||
* a concatenated PGD, into the maximum number of entries that can be
|
||||
* mapped in the same table page.
|
||||
*/
|
||||
static inline int arm_lpae_max_entries(int i, struct arm_lpae_io_pgtable *data)
|
||||
{
|
||||
int ptes_per_table = ARM_LPAE_PTES_PER_TABLE(data);
|
||||
|
||||
return ptes_per_table - (i & (ptes_per_table - 1));
|
||||
}
|
||||
|
||||
static bool selftest_running = false;
|
||||
|
||||
int arm_lpae_map_exists(void)
|
||||
{
|
||||
WARN_ON(!selftest_running);
|
||||
return -EEXIST;
|
||||
}
|
||||
|
||||
int arm_lpae_unmap_empty(void)
|
||||
{
|
||||
WARN_ON(!selftest_running);
|
||||
return -EEXIST;
|
||||
}
|
||||
|
||||
static dma_addr_t __arm_lpae_dma_addr(void *pages)
|
||||
{
|
||||
return (dma_addr_t)virt_to_phys(pages);
|
||||
}
|
||||
|
||||
static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
|
||||
struct io_pgtable_cfg *cfg,
|
||||
void *cookie)
|
||||
void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
|
||||
struct io_pgtable_cfg *cfg,
|
||||
void *cookie)
|
||||
{
|
||||
struct device *dev = cfg->iommu_dev;
|
||||
int order = get_order(size);
|
||||
@@ -265,9 +92,9 @@ out_free:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void __arm_lpae_free_pages(void *pages, size_t size,
|
||||
struct io_pgtable_cfg *cfg,
|
||||
void *cookie)
|
||||
void __arm_lpae_free_pages(void *pages, size_t size,
|
||||
struct io_pgtable_cfg *cfg,
|
||||
void *cookie)
|
||||
{
|
||||
if (!cfg->coherent_walk)
|
||||
dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages),
|
||||
@@ -279,300 +106,13 @@ static void __arm_lpae_free_pages(void *pages, size_t size,
|
||||
iommu_free_pages(pages, get_order(size));
|
||||
}
|
||||
|
||||
static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, int num_entries,
|
||||
struct io_pgtable_cfg *cfg)
|
||||
void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, int num_entries,
|
||||
struct io_pgtable_cfg *cfg)
|
||||
{
|
||||
dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep),
|
||||
sizeof(*ptep) * num_entries, DMA_TO_DEVICE);
|
||||
}
|
||||
|
||||
static void __arm_lpae_clear_pte(arm_lpae_iopte *ptep, struct io_pgtable_cfg *cfg, int num_entries)
|
||||
{
|
||||
for (int i = 0; i < num_entries; i++)
|
||||
ptep[i] = 0;
|
||||
|
||||
if (!cfg->coherent_walk && num_entries)
|
||||
__arm_lpae_sync_pte(ptep, num_entries, cfg);
|
||||
}
|
||||
|
||||
static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
|
||||
struct iommu_iotlb_gather *gather,
|
||||
unsigned long iova, size_t size, size_t pgcount,
|
||||
int lvl, arm_lpae_iopte *ptep);
|
||||
|
||||
static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
|
||||
phys_addr_t paddr, arm_lpae_iopte prot,
|
||||
int lvl, int num_entries, arm_lpae_iopte *ptep)
|
||||
{
|
||||
arm_lpae_iopte pte = prot;
|
||||
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
||||
size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
|
||||
int i;
|
||||
|
||||
if (data->iop.fmt != ARM_MALI_LPAE && lvl == ARM_LPAE_MAX_LEVELS - 1)
|
||||
pte |= ARM_LPAE_PTE_TYPE_PAGE;
|
||||
else
|
||||
pte |= ARM_LPAE_PTE_TYPE_BLOCK;
|
||||
|
||||
for (i = 0; i < num_entries; i++)
|
||||
ptep[i] = pte | paddr_to_iopte(paddr + i * sz, data);
|
||||
|
||||
if (!cfg->coherent_walk)
|
||||
__arm_lpae_sync_pte(ptep, num_entries, cfg);
|
||||
}
|
||||
|
||||
static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
|
||||
unsigned long iova, phys_addr_t paddr,
|
||||
arm_lpae_iopte prot, int lvl, int num_entries,
|
||||
arm_lpae_iopte *ptep)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_entries; i++)
|
||||
if (iopte_leaf(ptep[i], lvl, data->iop.fmt)) {
|
||||
/* We require an unmap first */
|
||||
WARN_ON(!selftest_running);
|
||||
return -EEXIST;
|
||||
} else if (iopte_type(ptep[i]) == ARM_LPAE_PTE_TYPE_TABLE) {
|
||||
/*
|
||||
* We need to unmap and free the old table before
|
||||
* overwriting it with a block entry.
|
||||
*/
|
||||
arm_lpae_iopte *tblp;
|
||||
size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
|
||||
|
||||
tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
|
||||
if (__arm_lpae_unmap(data, NULL, iova + i * sz, sz, 1,
|
||||
lvl, tblp) != sz) {
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
__arm_lpae_init_pte(data, paddr, prot, lvl, num_entries, ptep);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table,
|
||||
arm_lpae_iopte *ptep,
|
||||
arm_lpae_iopte curr,
|
||||
struct arm_lpae_io_pgtable *data)
|
||||
{
|
||||
arm_lpae_iopte old, new;
|
||||
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
||||
|
||||
new = paddr_to_iopte(__pa(table), data) | ARM_LPAE_PTE_TYPE_TABLE;
|
||||
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
|
||||
new |= ARM_LPAE_PTE_NSTABLE;
|
||||
|
||||
/*
|
||||
* Ensure the table itself is visible before its PTE can be.
|
||||
* Whilst we could get away with cmpxchg64_release below, this
|
||||
* doesn't have any ordering semantics when !CONFIG_SMP.
|
||||
*/
|
||||
dma_wmb();
|
||||
|
||||
old = cmpxchg64_relaxed(ptep, curr, new);
|
||||
|
||||
if (cfg->coherent_walk || (old & ARM_LPAE_PTE_SW_SYNC))
|
||||
return old;
|
||||
|
||||
/* Even if it's not ours, there's no point waiting; just kick it */
|
||||
__arm_lpae_sync_pte(ptep, 1, cfg);
|
||||
if (old == curr)
|
||||
WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC);
|
||||
|
||||
return old;
|
||||
}
|
||||
|
||||
static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
|
||||
phys_addr_t paddr, size_t size, size_t pgcount,
|
||||
arm_lpae_iopte prot, int lvl, arm_lpae_iopte *ptep,
|
||||
gfp_t gfp, size_t *mapped)
|
||||
{
|
||||
arm_lpae_iopte *cptep, pte;
|
||||
size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
|
||||
size_t tblsz = ARM_LPAE_GRANULE(data);
|
||||
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
||||
int ret = 0, num_entries, max_entries, map_idx_start;
|
||||
|
||||
/* Find our entry at the current level */
|
||||
map_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data);
|
||||
ptep += map_idx_start;
|
||||
|
||||
/* If we can install a leaf entry at this level, then do so */
|
||||
if (size == block_size) {
|
||||
max_entries = arm_lpae_max_entries(map_idx_start, data);
|
||||
num_entries = min_t(int, pgcount, max_entries);
|
||||
ret = arm_lpae_init_pte(data, iova, paddr, prot, lvl, num_entries, ptep);
|
||||
if (!ret)
|
||||
*mapped += num_entries * size;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* We can't allocate tables at the final level */
|
||||
if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
|
||||
return -EINVAL;
|
||||
|
||||
/* Grab a pointer to the next level */
|
||||
pte = READ_ONCE(*ptep);
|
||||
if (!pte) {
|
||||
cptep = __arm_lpae_alloc_pages(tblsz, gfp, cfg, data->iop.cookie);
|
||||
if (!cptep)
|
||||
return -ENOMEM;
|
||||
|
||||
pte = arm_lpae_install_table(cptep, ptep, 0, data);
|
||||
if (pte)
|
||||
__arm_lpae_free_pages(cptep, tblsz, cfg, data->iop.cookie);
|
||||
} else if (!cfg->coherent_walk && !(pte & ARM_LPAE_PTE_SW_SYNC)) {
|
||||
__arm_lpae_sync_pte(ptep, 1, cfg);
|
||||
}
|
||||
|
||||
if (pte && !iopte_leaf(pte, lvl, data->iop.fmt)) {
|
||||
cptep = iopte_deref(pte, data);
|
||||
} else if (pte) {
|
||||
/* We require an unmap first */
|
||||
WARN_ON(!selftest_running);
|
||||
return -EEXIST;
|
||||
}
|
||||
|
||||
/* Rinse, repeat */
|
||||
return __arm_lpae_map(data, iova, paddr, size, pgcount, prot, lvl + 1,
|
||||
cptep, gfp, mapped);
|
||||
}
|
||||
|
||||
static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
|
||||
int prot)
|
||||
{
|
||||
arm_lpae_iopte pte;
|
||||
|
||||
if (data->iop.fmt == ARM_64_LPAE_S1 ||
|
||||
data->iop.fmt == ARM_32_LPAE_S1) {
|
||||
pte = ARM_LPAE_PTE_nG;
|
||||
if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
|
||||
pte |= ARM_LPAE_PTE_AP_RDONLY;
|
||||
else if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_HD)
|
||||
pte |= ARM_LPAE_PTE_DBM;
|
||||
if (!(prot & IOMMU_PRIV))
|
||||
pte |= ARM_LPAE_PTE_AP_UNPRIV;
|
||||
} else {
|
||||
pte = ARM_LPAE_PTE_HAP_FAULT;
|
||||
if (prot & IOMMU_READ)
|
||||
pte |= ARM_LPAE_PTE_HAP_READ;
|
||||
if (prot & IOMMU_WRITE)
|
||||
pte |= ARM_LPAE_PTE_HAP_WRITE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Note that this logic is structured to accommodate Mali LPAE
|
||||
* having stage-1-like attributes but stage-2-like permissions.
|
||||
*/
|
||||
if (data->iop.fmt == ARM_64_LPAE_S2 ||
|
||||
data->iop.fmt == ARM_32_LPAE_S2) {
|
||||
if (prot & IOMMU_MMIO)
|
||||
pte |= ARM_LPAE_PTE_MEMATTR_DEV;
|
||||
else if (prot & IOMMU_CACHE)
|
||||
pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
|
||||
else
|
||||
pte |= ARM_LPAE_PTE_MEMATTR_NC;
|
||||
} else {
|
||||
if (prot & IOMMU_MMIO)
|
||||
pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
|
||||
<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
|
||||
else if (prot & IOMMU_CACHE)
|
||||
pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
|
||||
<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
|
||||
}
|
||||
|
||||
/*
|
||||
* Also Mali has its own notions of shareability wherein its Inner
|
||||
* domain covers the cores within the GPU, and its Outer domain is
|
||||
* "outside the GPU" (i.e. either the Inner or System domain in CPU
|
||||
* terms, depending on coherency).
|
||||
*/
|
||||
if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
|
||||
pte |= ARM_LPAE_PTE_SH_IS;
|
||||
else
|
||||
pte |= ARM_LPAE_PTE_SH_OS;
|
||||
|
||||
if (prot & IOMMU_NOEXEC)
|
||||
pte |= ARM_LPAE_PTE_XN;
|
||||
|
||||
if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS)
|
||||
pte |= ARM_LPAE_PTE_NS;
|
||||
|
||||
if (data->iop.fmt != ARM_MALI_LPAE)
|
||||
pte |= ARM_LPAE_PTE_AF;
|
||||
|
||||
return pte;
|
||||
}
|
||||
|
||||
static int arm_lpae_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
|
||||
phys_addr_t paddr, size_t pgsize, size_t pgcount,
|
||||
int iommu_prot, gfp_t gfp, size_t *mapped)
|
||||
{
|
||||
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
||||
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
||||
arm_lpae_iopte *ptep = data->pgd;
|
||||
int ret, lvl = data->start_level;
|
||||
arm_lpae_iopte prot;
|
||||
long iaext = (s64)iova >> cfg->ias;
|
||||
|
||||
if (WARN_ON(!pgsize || (pgsize & cfg->pgsize_bitmap) != pgsize))
|
||||
return -EINVAL;
|
||||
|
||||
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
|
||||
iaext = ~iaext;
|
||||
if (WARN_ON(iaext || paddr >> cfg->oas))
|
||||
return -ERANGE;
|
||||
|
||||
if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
|
||||
return -EINVAL;
|
||||
|
||||
prot = arm_lpae_prot_to_pte(data, iommu_prot);
|
||||
ret = __arm_lpae_map(data, iova, paddr, pgsize, pgcount, prot, lvl,
|
||||
ptep, gfp, mapped);
|
||||
/*
|
||||
* Synchronise all PTE updates for the new mapping before there's
|
||||
* a chance for anything to kick off a table walk for the new iova.
|
||||
*/
|
||||
wmb();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
|
||||
arm_lpae_iopte *ptep)
|
||||
{
|
||||
arm_lpae_iopte *start, *end;
|
||||
unsigned long table_size;
|
||||
|
||||
if (lvl == data->start_level)
|
||||
table_size = ARM_LPAE_PGD_SIZE(data);
|
||||
else
|
||||
table_size = ARM_LPAE_GRANULE(data);
|
||||
|
||||
start = ptep;
|
||||
|
||||
/* Only leaf entries at the last level */
|
||||
if (lvl == ARM_LPAE_MAX_LEVELS - 1)
|
||||
end = ptep;
|
||||
else
|
||||
end = (void *)ptep + table_size;
|
||||
|
||||
while (ptep != end) {
|
||||
arm_lpae_iopte pte = *ptep++;
|
||||
|
||||
if (!pte || iopte_leaf(pte, lvl, data->iop.fmt))
|
||||
continue;
|
||||
|
||||
__arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
|
||||
}
|
||||
|
||||
__arm_lpae_free_pages(start, table_size, &data->iop.cfg, data->iop.cookie);
|
||||
}
|
||||
|
||||
static void arm_lpae_free_pgtable(struct io_pgtable *iop)
|
||||
{
|
||||
struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
|
||||
@@ -581,274 +121,6 @@ static void arm_lpae_free_pgtable(struct io_pgtable *iop)
|
||||
kfree(data);
|
||||
}
|
||||
|
||||
static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
|
||||
struct iommu_iotlb_gather *gather,
|
||||
unsigned long iova, size_t size,
|
||||
arm_lpae_iopte blk_pte, int lvl,
|
||||
arm_lpae_iopte *ptep, size_t pgcount)
|
||||
{
|
||||
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
||||
arm_lpae_iopte pte, *tablep;
|
||||
phys_addr_t blk_paddr;
|
||||
size_t tablesz = ARM_LPAE_GRANULE(data);
|
||||
size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
|
||||
int ptes_per_table = ARM_LPAE_PTES_PER_TABLE(data);
|
||||
int i, unmap_idx_start = -1, num_entries = 0, max_entries;
|
||||
|
||||
if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
|
||||
return 0;
|
||||
|
||||
tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg, data->iop.cookie);
|
||||
if (!tablep)
|
||||
return 0; /* Bytes unmapped */
|
||||
|
||||
if (size == split_sz) {
|
||||
unmap_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data);
|
||||
max_entries = arm_lpae_max_entries(unmap_idx_start, data);
|
||||
num_entries = min_t(int, pgcount, max_entries);
|
||||
}
|
||||
|
||||
blk_paddr = iopte_to_paddr(blk_pte, data);
|
||||
pte = iopte_prot(blk_pte);
|
||||
|
||||
for (i = 0; i < ptes_per_table; i++, blk_paddr += split_sz) {
|
||||
/* Unmap! */
|
||||
if (i >= unmap_idx_start && i < (unmap_idx_start + num_entries))
|
||||
continue;
|
||||
|
||||
__arm_lpae_init_pte(data, blk_paddr, pte, lvl, 1, &tablep[i]);
|
||||
}
|
||||
|
||||
pte = arm_lpae_install_table(tablep, ptep, blk_pte, data);
|
||||
if (pte != blk_pte) {
|
||||
__arm_lpae_free_pages(tablep, tablesz, cfg, data->iop.cookie);
|
||||
/*
|
||||
* We may race against someone unmapping another part of this
|
||||
* block, but anything else is invalid. We can't misinterpret
|
||||
* a page entry here since we're never at the last level.
|
||||
*/
|
||||
if (iopte_type(pte) != ARM_LPAE_PTE_TYPE_TABLE)
|
||||
return 0;
|
||||
|
||||
tablep = iopte_deref(pte, data);
|
||||
} else if (unmap_idx_start >= 0) {
|
||||
for (i = 0; i < num_entries; i++)
|
||||
io_pgtable_tlb_add_page(&data->iop, gather, iova + i * size, size);
|
||||
|
||||
return num_entries * size;
|
||||
}
|
||||
|
||||
return __arm_lpae_unmap(data, gather, iova, size, pgcount, lvl, tablep);
|
||||
}
|
||||
|
||||
static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
|
||||
struct iommu_iotlb_gather *gather,
|
||||
unsigned long iova, size_t size, size_t pgcount,
|
||||
int lvl, arm_lpae_iopte *ptep)
|
||||
{
|
||||
arm_lpae_iopte pte;
|
||||
struct io_pgtable *iop = &data->iop;
|
||||
int i = 0, num_entries, max_entries, unmap_idx_start;
|
||||
|
||||
/* Something went horribly wrong and we ran out of page table */
|
||||
if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
|
||||
return 0;
|
||||
|
||||
unmap_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data);
|
||||
ptep += unmap_idx_start;
|
||||
pte = READ_ONCE(*ptep);
|
||||
if (WARN_ON(!pte))
|
||||
return 0;
|
||||
|
||||
/* If the size matches this level, we're in the right place */
|
||||
if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) {
|
||||
max_entries = arm_lpae_max_entries(unmap_idx_start, data);
|
||||
num_entries = min_t(int, pgcount, max_entries);
|
||||
|
||||
/* Find and handle non-leaf entries */
|
||||
for (i = 0; i < num_entries; i++) {
|
||||
pte = READ_ONCE(ptep[i]);
|
||||
if (WARN_ON(!pte))
|
||||
break;
|
||||
|
||||
if (!iopte_leaf(pte, lvl, iop->fmt)) {
|
||||
__arm_lpae_clear_pte(&ptep[i], &iop->cfg, 1);
|
||||
|
||||
/* Also flush any partial walks */
|
||||
io_pgtable_tlb_flush_walk(iop, iova + i * size, size,
|
||||
ARM_LPAE_GRANULE(data));
|
||||
__arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the remaining entries */
|
||||
__arm_lpae_clear_pte(ptep, &iop->cfg, i);
|
||||
|
||||
if (gather && !iommu_iotlb_gather_queued(gather))
|
||||
for (int j = 0; j < i; j++)
|
||||
io_pgtable_tlb_add_page(iop, gather, iova + j * size, size);
|
||||
|
||||
return i * size;
|
||||
} else if (iopte_leaf(pte, lvl, iop->fmt)) {
|
||||
/*
|
||||
* Insert a table at the next level to map the old region,
|
||||
* minus the part we want to unmap
|
||||
*/
|
||||
return arm_lpae_split_blk_unmap(data, gather, iova, size, pte,
|
||||
lvl + 1, ptep, pgcount);
|
||||
}
|
||||
|
||||
/* Keep on walkin' */
|
||||
ptep = iopte_deref(pte, data);
|
||||
return __arm_lpae_unmap(data, gather, iova, size, pgcount, lvl + 1, ptep);
|
||||
}
|
||||
|
||||
static size_t arm_lpae_unmap_pages(struct io_pgtable_ops *ops, unsigned long iova,
|
||||
size_t pgsize, size_t pgcount,
|
||||
struct iommu_iotlb_gather *gather)
|
||||
{
|
||||
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
||||
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
||||
arm_lpae_iopte *ptep = data->pgd;
|
||||
long iaext = (s64)iova >> cfg->ias;
|
||||
|
||||
if (WARN_ON(!pgsize || (pgsize & cfg->pgsize_bitmap) != pgsize || !pgcount))
|
||||
return 0;
|
||||
|
||||
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
|
||||
iaext = ~iaext;
|
||||
if (WARN_ON(iaext))
|
||||
return 0;
|
||||
|
||||
return __arm_lpae_unmap(data, gather, iova, pgsize, pgcount,
|
||||
data->start_level, ptep);
|
||||
}
|
||||
|
||||
struct io_pgtable_walk_data {
|
||||
struct io_pgtable *iop;
|
||||
void *data;
|
||||
int (*visit)(struct io_pgtable_walk_data *walk_data, int lvl,
|
||||
arm_lpae_iopte *ptep, size_t size);
|
||||
unsigned long flags;
|
||||
u64 addr;
|
||||
const u64 end;
|
||||
};
|
||||
|
||||
static int __arm_lpae_iopte_walk(struct arm_lpae_io_pgtable *data,
|
||||
struct io_pgtable_walk_data *walk_data,
|
||||
arm_lpae_iopte *ptep,
|
||||
int lvl);
|
||||
|
||||
struct iova_to_phys_data {
|
||||
arm_lpae_iopte pte;
|
||||
int lvl;
|
||||
};
|
||||
|
||||
static int visit_iova_to_phys(struct io_pgtable_walk_data *walk_data, int lvl,
|
||||
arm_lpae_iopte *ptep, size_t size)
|
||||
{
|
||||
struct iova_to_phys_data *data = walk_data->data;
|
||||
data->pte = *ptep;
|
||||
data->lvl = lvl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
|
||||
unsigned long iova)
|
||||
{
|
||||
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
||||
struct iova_to_phys_data d;
|
||||
struct io_pgtable_walk_data walk_data = {
|
||||
.data = &d,
|
||||
.visit = visit_iova_to_phys,
|
||||
.addr = iova,
|
||||
.end = iova + 1,
|
||||
};
|
||||
int ret;
|
||||
|
||||
ret = __arm_lpae_iopte_walk(data, &walk_data, data->pgd, data->start_level);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
iova &= (ARM_LPAE_BLOCK_SIZE(d.lvl, data) - 1);
|
||||
return iopte_to_paddr(d.pte, data) | iova;
|
||||
}
|
||||
|
||||
static int visit_pgtable_walk(struct io_pgtable_walk_data *walk_data, int lvl,
|
||||
arm_lpae_iopte *ptep, size_t size)
|
||||
{
|
||||
struct arm_lpae_io_pgtable_walk_data *data = walk_data->data;
|
||||
data->ptes[data->level++] = *ptep;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int arm_lpae_pgtable_walk(struct io_pgtable_ops *ops, unsigned long iova,
|
||||
void *wd)
|
||||
{
|
||||
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
||||
struct io_pgtable_walk_data walk_data = {
|
||||
.data = wd,
|
||||
.visit = visit_pgtable_walk,
|
||||
.addr = iova,
|
||||
.end = iova + 1,
|
||||
};
|
||||
|
||||
((struct arm_lpae_io_pgtable_walk_data *)wd)->level = 0;
|
||||
|
||||
return __arm_lpae_iopte_walk(data, &walk_data, data->pgd, data->start_level);
|
||||
}
|
||||
|
||||
static int io_pgtable_visit(struct arm_lpae_io_pgtable *data,
|
||||
struct io_pgtable_walk_data *walk_data,
|
||||
arm_lpae_iopte *ptep, int lvl)
|
||||
{
|
||||
struct io_pgtable *iop = &data->iop;
|
||||
arm_lpae_iopte pte = READ_ONCE(*ptep);
|
||||
|
||||
size_t size = ARM_LPAE_BLOCK_SIZE(lvl, data);
|
||||
int ret = walk_data->visit(walk_data, lvl, ptep, size);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (iopte_leaf(pte, lvl, iop->fmt)) {
|
||||
walk_data->addr += size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!iopte_table(pte, lvl)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ptep = iopte_deref(pte, data);
|
||||
return __arm_lpae_iopte_walk(data, walk_data, ptep, lvl + 1);
|
||||
}
|
||||
|
||||
static int __arm_lpae_iopte_walk(struct arm_lpae_io_pgtable *data,
|
||||
struct io_pgtable_walk_data *walk_data,
|
||||
arm_lpae_iopte *ptep,
|
||||
int lvl)
|
||||
{
|
||||
u32 idx;
|
||||
int max_entries, ret;
|
||||
|
||||
if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
|
||||
return -EINVAL;
|
||||
|
||||
if (lvl == data->start_level)
|
||||
max_entries = ARM_LPAE_PGD_SIZE(data) / sizeof(arm_lpae_iopte);
|
||||
else
|
||||
max_entries = ARM_LPAE_PTES_PER_TABLE(data);
|
||||
|
||||
for (idx = ARM_LPAE_LVL_IDX(walk_data->addr, lvl, data);
|
||||
(idx < max_entries) && (walk_data->addr < walk_data->end); ++idx) {
|
||||
ret = io_pgtable_visit(data, walk_data, ptep + idx, lvl);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int visit_dirty(struct io_pgtable_walk_data *walk_data, int lvl,
|
||||
arm_lpae_iopte *ptep, size_t size)
|
||||
{
|
||||
@@ -866,10 +138,10 @@ static int visit_dirty(struct io_pgtable_walk_data *walk_data, int lvl,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int arm_lpae_read_and_clear_dirty(struct io_pgtable_ops *ops,
|
||||
unsigned long iova, size_t size,
|
||||
unsigned long flags,
|
||||
struct iommu_dirty_bitmap *dirty)
|
||||
int arm_lpae_read_and_clear_dirty(struct io_pgtable_ops *ops,
|
||||
unsigned long iova, size_t size,
|
||||
unsigned long flags,
|
||||
struct iommu_dirty_bitmap *dirty)
|
||||
{
|
||||
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
||||
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
||||
|
||||
@@ -1,30 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
#ifndef IO_PGTABLE_ARM_H_
|
||||
#define IO_PGTABLE_ARM_H_
|
||||
|
||||
#define ARM_LPAE_TCR_TG0_4K 0
|
||||
#define ARM_LPAE_TCR_TG0_64K 1
|
||||
#define ARM_LPAE_TCR_TG0_16K 2
|
||||
|
||||
#define ARM_LPAE_TCR_TG1_16K 1
|
||||
#define ARM_LPAE_TCR_TG1_4K 2
|
||||
#define ARM_LPAE_TCR_TG1_64K 3
|
||||
|
||||
#define ARM_LPAE_TCR_SH_NS 0
|
||||
#define ARM_LPAE_TCR_SH_OS 2
|
||||
#define ARM_LPAE_TCR_SH_IS 3
|
||||
|
||||
#define ARM_LPAE_TCR_RGN_NC 0
|
||||
#define ARM_LPAE_TCR_RGN_WBWA 1
|
||||
#define ARM_LPAE_TCR_RGN_WT 2
|
||||
#define ARM_LPAE_TCR_RGN_WB 3
|
||||
|
||||
#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
|
||||
#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
|
||||
#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
|
||||
#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
|
||||
#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
|
||||
#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
|
||||
#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
|
||||
|
||||
#endif /* IO_PGTABLE_ARM_H_ */
|
||||
@@ -0,0 +1,227 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
#ifndef IO_PGTABLE_H_
|
||||
#define IO_PGTABLE_H_
|
||||
|
||||
#include <linux/io-pgtable.h>
|
||||
|
||||
typedef u64 arm_lpae_iopte;
|
||||
|
||||
struct arm_lpae_io_pgtable {
|
||||
struct io_pgtable iop;
|
||||
|
||||
int pgd_bits;
|
||||
int start_level;
|
||||
int bits_per_level;
|
||||
|
||||
void *pgd;
|
||||
};
|
||||
|
||||
struct io_pgtable_walk_data {
|
||||
struct io_pgtable *iop;
|
||||
void *data;
|
||||
int (*visit)(struct io_pgtable_walk_data *walk_data, int lvl,
|
||||
arm_lpae_iopte *ptep, size_t size);
|
||||
unsigned long flags;
|
||||
u64 addr;
|
||||
const u64 end;
|
||||
};
|
||||
|
||||
/* Struct accessors */
|
||||
#define io_pgtable_to_data(x) \
|
||||
container_of((x), struct arm_lpae_io_pgtable, iop)
|
||||
|
||||
#define io_pgtable_ops_to_data(x) \
|
||||
io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
|
||||
|
||||
/*
|
||||
* Calculate the right shift amount to get to the portion describing level l
|
||||
* in a virtual address mapped by the pagetable in d.
|
||||
*/
|
||||
#define ARM_LPAE_LVL_SHIFT(l,d) \
|
||||
(((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level) + \
|
||||
ilog2(sizeof(arm_lpae_iopte)))
|
||||
|
||||
#define ARM_LPAE_GRANULE(d) \
|
||||
(sizeof(arm_lpae_iopte) << (d)->bits_per_level)
|
||||
#define ARM_LPAE_PGD_SIZE(d) \
|
||||
(sizeof(arm_lpae_iopte) << (d)->pgd_bits)
|
||||
|
||||
#define ARM_LPAE_PTES_PER_TABLE(d) \
|
||||
(ARM_LPAE_GRANULE(d) >> ilog2(sizeof(arm_lpae_iopte)))
|
||||
|
||||
/*
|
||||
* Calculate the index at level l used to map virtual address a using the
|
||||
* pagetable in d.
|
||||
*/
|
||||
#define ARM_LPAE_PGD_IDX(l,d) \
|
||||
((l) == (d)->start_level ? (d)->pgd_bits - (d)->bits_per_level : 0)
|
||||
|
||||
#define ARM_LPAE_LVL_IDX(a,l,d) \
|
||||
(((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
|
||||
((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
|
||||
|
||||
/* Calculate the block/page mapping size at level l for pagetable in d. */
|
||||
#define ARM_LPAE_BLOCK_SIZE(l,d) (1ULL << ARM_LPAE_LVL_SHIFT(l,d))
|
||||
|
||||
/* Page table bits */
|
||||
#define ARM_LPAE_PTE_TYPE_SHIFT 0
|
||||
#define ARM_LPAE_PTE_TYPE_MASK 0x3
|
||||
|
||||
#define ARM_LPAE_PTE_TYPE_BLOCK 1
|
||||
#define ARM_LPAE_PTE_TYPE_TABLE 3
|
||||
#define ARM_LPAE_PTE_TYPE_PAGE 3
|
||||
|
||||
#define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12)
|
||||
|
||||
#define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
|
||||
#define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
|
||||
#define ARM_LPAE_PTE_DBM (((arm_lpae_iopte)1) << 51)
|
||||
#define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
|
||||
#define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
|
||||
#define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
|
||||
#define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
|
||||
#define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
|
||||
#define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
|
||||
|
||||
#define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
|
||||
/* Ignore the contiguous bit for block splitting */
|
||||
#define ARM_LPAE_PTE_ATTR_HI_MASK (ARM_LPAE_PTE_XN | ARM_LPAE_PTE_DBM)
|
||||
#define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
|
||||
ARM_LPAE_PTE_ATTR_HI_MASK)
|
||||
/* Software bit for solving coherency races */
|
||||
#define ARM_LPAE_PTE_SW_SYNC (((arm_lpae_iopte)1) << 55)
|
||||
|
||||
/* Stage-1 PTE */
|
||||
#define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
|
||||
#define ARM_LPAE_PTE_AP_RDONLY_BIT 7
|
||||
#define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)1) << \
|
||||
ARM_LPAE_PTE_AP_RDONLY_BIT)
|
||||
#define ARM_LPAE_PTE_AP_WR_CLEAN_MASK (ARM_LPAE_PTE_AP_RDONLY | \
|
||||
ARM_LPAE_PTE_DBM)
|
||||
#define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
|
||||
#define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
|
||||
|
||||
/* Stage-2 PTE */
|
||||
#define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
|
||||
#define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
|
||||
#define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
|
||||
#define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
|
||||
#define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
|
||||
#define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
|
||||
|
||||
/* Register bits */
|
||||
#define ARM_LPAE_VTCR_SL0_MASK 0x3
|
||||
|
||||
#define ARM_LPAE_TCR_T0SZ_SHIFT 0
|
||||
|
||||
#define ARM_LPAE_VTCR_PS_SHIFT 16
|
||||
#define ARM_LPAE_VTCR_PS_MASK 0x7
|
||||
|
||||
#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
|
||||
#define ARM_LPAE_MAIR_ATTR_MASK 0xff
|
||||
#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
|
||||
#define ARM_LPAE_MAIR_ATTR_NC 0x44
|
||||
#define ARM_LPAE_MAIR_ATTR_INC_OWBRWA 0xf4
|
||||
#define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
|
||||
#define ARM_LPAE_MAIR_ATTR_IDX_NC 0
|
||||
#define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
|
||||
#define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
|
||||
#define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE 3
|
||||
|
||||
#define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0)
|
||||
#define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2)
|
||||
#define ARM_MALI_LPAE_TTBR_SHARE_OUTER BIT(4)
|
||||
|
||||
#define ARM_MALI_LPAE_MEMATTR_IMP_DEF 0x88ULL
|
||||
#define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL
|
||||
|
||||
#define ARM_LPAE_MAX_LEVELS 4
|
||||
|
||||
#define ARM_LPAE_TCR_TG0_4K 0
|
||||
#define ARM_LPAE_TCR_TG0_64K 1
|
||||
#define ARM_LPAE_TCR_TG0_16K 2
|
||||
|
||||
#define ARM_LPAE_TCR_TG1_16K 1
|
||||
#define ARM_LPAE_TCR_TG1_4K 2
|
||||
#define ARM_LPAE_TCR_TG1_64K 3
|
||||
|
||||
#define ARM_LPAE_TCR_SH_NS 0
|
||||
#define ARM_LPAE_TCR_SH_OS 2
|
||||
#define ARM_LPAE_TCR_SH_IS 3
|
||||
|
||||
#define ARM_LPAE_TCR_RGN_NC 0
|
||||
#define ARM_LPAE_TCR_RGN_WBWA 1
|
||||
#define ARM_LPAE_TCR_RGN_WT 2
|
||||
#define ARM_LPAE_TCR_RGN_WB 3
|
||||
|
||||
#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
|
||||
#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
|
||||
#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
|
||||
#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
|
||||
#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
|
||||
#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
|
||||
#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
|
||||
|
||||
/* IOPTE accessors */
|
||||
#define iopte_type(pte) \
|
||||
(((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
|
||||
|
||||
#define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
|
||||
|
||||
#define iopte_writeable_dirty(pte) \
|
||||
(((pte) & ARM_LPAE_PTE_AP_WR_CLEAN_MASK) == ARM_LPAE_PTE_DBM)
|
||||
|
||||
#define iopte_set_writeable_clean(ptep) \
|
||||
set_bit(ARM_LPAE_PTE_AP_RDONLY_BIT, (unsigned long *)(ptep))
|
||||
|
||||
|
||||
static inline bool iopte_leaf(arm_lpae_iopte pte, int lvl,
|
||||
enum io_pgtable_fmt fmt)
|
||||
{
|
||||
if (lvl == (ARM_LPAE_MAX_LEVELS - 1) && fmt != ARM_MALI_LPAE)
|
||||
return iopte_type(pte) == ARM_LPAE_PTE_TYPE_PAGE;
|
||||
|
||||
return iopte_type(pte) == ARM_LPAE_PTE_TYPE_BLOCK;
|
||||
}
|
||||
|
||||
static inline bool iopte_table(arm_lpae_iopte pte, int lvl)
|
||||
{
|
||||
if (lvl == (ARM_LPAE_MAX_LEVELS - 1))
|
||||
return false;
|
||||
return iopte_type(pte) == ARM_LPAE_PTE_TYPE_TABLE;
|
||||
}
|
||||
|
||||
#define __arm_lpae_virt_to_phys __pa
|
||||
#define __arm_lpae_phys_to_virt __va
|
||||
|
||||
/* Generic functions */
|
||||
int arm_lpae_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
|
||||
phys_addr_t paddr, size_t pgsize, size_t pgcount,
|
||||
int iommu_prot, gfp_t gfp, size_t *mapped);
|
||||
size_t arm_lpae_unmap_pages(struct io_pgtable_ops *ops, unsigned long iova,
|
||||
size_t pgsize, size_t pgcount,
|
||||
struct iommu_iotlb_gather *gather);
|
||||
phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
|
||||
unsigned long iova);
|
||||
void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
|
||||
arm_lpae_iopte *ptep);
|
||||
|
||||
int arm_lpae_read_and_clear_dirty(struct io_pgtable_ops *ops,
|
||||
unsigned long iova, size_t size,
|
||||
unsigned long flags,
|
||||
struct iommu_dirty_bitmap *dirty);
|
||||
|
||||
int arm_lpae_pgtable_walk(struct io_pgtable_ops *ops, unsigned long iova, void *wd);
|
||||
|
||||
int __arm_lpae_iopte_walk(struct arm_lpae_io_pgtable *data,
|
||||
struct io_pgtable_walk_data *walk_data,
|
||||
arm_lpae_iopte *ptep,
|
||||
int lvl);
|
||||
/* Host/hyp-specific functions */
|
||||
void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp, struct io_pgtable_cfg *cfg, void *cookie);
|
||||
void __arm_lpae_free_pages(void *pages, size_t size, struct io_pgtable_cfg *cfg, void *cookie);
|
||||
void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, int num_entries,
|
||||
struct io_pgtable_cfg *cfg);
|
||||
int arm_lpae_map_exists(void);
|
||||
int arm_lpae_unmap_empty(void);
|
||||
#endif /* IO_PGTABLE_H_ */
|
||||
Reference in New Issue
Block a user