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drm/xe/guc: Use valid scratch register for posting read

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There are only 4 scratch registers VF_SW_FLAG(0..3) on each GuC.
We shouldn't use non-existing register VF_SW_FLAG(4) for posting
read.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Michal Wajdeczko
2023-11-16 16:12:42 +01:00
committed by Rodrigo Vivi
parent 1d087cb7d8
commit cac74742fa
1 changed files with 1 additions and 1 deletions
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drivers/gpu/drm/xe/xe_guc.c
+1 -1
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@@ -615,7 +615,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
u32 header, reply;
struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?
MED_VF_SW_FLAG(0) : VF_SW_FLAG(0);
const u32 LAST_INDEX = VF_SW_FLAG_COUNT;
const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1;
int ret;
int i;