dt-bindings: net: dsa: lantiq,gswip: convert to YAML schema
Convert the lantiq,gswip bindings to YAML format. Also add this new file to the MAINTAINERS file. Furthermore, the CPU port has to specify a phy-mode and either a phy or a fixed-link. Since GSWIP is connected using a SoC internal protocol there's no PHY involved. Add phy-mode = "internal" and a fixed-link to the example code to describe the communication between the PMAC (Ethernet controller) and GSWIP switch. Signed-off-by: Martin Schiller <ms@dev.tdt.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20240611135434.3180973-2-ms@dev.tdt.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Martin Schiller
committed by
Jakub Kicinski
Jakub Kicinski
parent
cf157f33f4
commit
c7f7595421
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Lantiq GSWIP Ethernet switches
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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maintainers:
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- Hauke Mehrtens <hauke@hauke-m.de>
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properties:
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compatible:
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enum:
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- lantiq,xrx200-gswip
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- lantiq,xrx300-gswip
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- lantiq,xrx330-gswip
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reg:
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minItems: 3
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maxItems: 3
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reg-names:
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items:
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- const: switch
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- const: mdio
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- const: mii
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mdio:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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properties:
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compatible:
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const: lantiq,xrx200-mdio
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required:
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- compatible
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gphy-fw:
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type: object
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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compatible:
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items:
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- enum:
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- lantiq,xrx200-gphy-fw
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- lantiq,xrx300-gphy-fw
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- lantiq,xrx330-gphy-fw
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- const: lantiq,gphy-fw
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lantiq,rcu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the RCU syscon
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patternProperties:
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"^gphy@[0-9a-f]{1,2}$":
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type: object
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additionalProperties: false
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properties:
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reg:
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minimum: 0
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maximum: 255
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description:
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Offset of the GPHY firmware register in the RCU register range
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resets:
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items:
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- description: GPHY reset line
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reset-names:
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items:
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- const: gphy
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required:
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- reg
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required:
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- compatible
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- lantiq,rcu
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additionalProperties: false
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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switch@e108000 {
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compatible = "lantiq,xrx200-gswip";
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reg = <0xe108000 0x3100>, /* switch */
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<0xe10b100 0xd8>, /* mdio */
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<0xe10b1d8 0x130>; /* mii */
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dsa,member = <0 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan3";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&phy11>;
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&phy13>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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};
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port@6 {
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reg = <0x6>;
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phy-mode = "internal";
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ethernet = <ð0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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phy5: ethernet-phy@5 {
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reg = <0x5>;
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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};
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};
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gphy-fw {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
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lantiq,rcu = <&rcu0>;
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gphy@20 {
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reg = <0x20>;
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resets = <&reset0 31 30>;
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reset-names = "gphy";
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};
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gphy@68 {
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reg = <0x68>;
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resets = <&reset0 29 28>;
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reset-names = "gphy";
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};
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};
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};
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@@ -1,146 +0,0 @@
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Lantiq GSWIP Ethernet switches
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==================================
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Required properties for GSWIP core:
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- compatible : "lantiq,xrx200-gswip" for the embedded GSWIP in the
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xRX200 SoC
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"lantiq,xrx300-gswip" for the embedded GSWIP in the
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xRX300 SoC
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"lantiq,xrx330-gswip" for the embedded GSWIP in the
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xRX330 SoC
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- reg : memory range of the GSWIP core registers
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: memory range of the GSWIP MDIO registers
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: memory range of the GSWIP MII registers
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See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
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additional required and optional properties.
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Required properties for MDIO bus:
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- compatible : "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
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core of the xRX200 SoC and the PHYs connected to it.
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See Documentation/devicetree/bindings/net/mdio.txt for a list of additional
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required and optional properties.
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Required properties for GPHY firmware loading:
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- compatible : "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
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"lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
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"lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
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for the loading of the firmware into the embedded
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GPHY core of the SoC.
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- lantiq,rcu : reference to the rcu syscon
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The GPHY firmware loader has a list of GPHY entries, one for each
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embedded GPHY
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- reg : Offset of the GPHY firmware register in the RCU
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register range
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- resets : list of resets of the embedded GPHY
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- reset-names : list of names of the resets
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Example:
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Ethernet switch on the VRX200 SoC:
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switch@e108000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-gswip";
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reg = < 0xe108000 0x3100 /* switch */
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0xe10b100 0xd8 /* mdio */
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0xe10b1d8 0x130 /* mii */
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>;
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dsa,member = <0 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan3";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&phy11>;
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&phy13>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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};
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port@6 {
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reg = <0x6>;
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ethernet = <ð0>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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reg = <0>;
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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phy5: ethernet-phy@5 {
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reg = <0x5>;
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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};
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};
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gphy-fw {
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compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
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lantiq,rcu = <&rcu0>;
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#address-cells = <1>;
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#size-cells = <0>;
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gphy@20 {
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reg = <0x20>;
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resets = <&reset0 31 30>;
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reset-names = "gphy";
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};
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gphy@68 {
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reg = <0x68>;
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resets = <&reset0 29 28>;
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reset-names = "gphy";
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};
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};
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};
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@@ -12449,6 +12449,7 @@ LANTIQ / INTEL Ethernet drivers
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M: Hauke Mehrtens <hauke@hauke-m.de>
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L: netdev@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
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F: drivers/net/dsa/lantiq_gswip.c
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F: drivers/net/dsa/lantiq_pce.h
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F: drivers/net/ethernet/lantiq_xrx200.c
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