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drm/amd/display: Send PQ bit in AMD VSIF

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[WHY & HOW]
PB9 bit 5 was added to signal PQ EOTF in AMD vendor specific infoframe.
This change sets it when appropriate.

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Krunoslav Kovac <krunoslav.kovac@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Krunoslav Kovac
2023-11-01 15:59:56 -04:00
committed by Alex Deucher
parent cc6201b773
commit c21a764a98
1 changed files with 4 additions and 2 deletions
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drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+4 -2
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@@ -693,10 +693,12 @@ static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
if (app_tf != TRANSFER_FUNC_UNKNOWN) {
infopacket->valid = true;
if (app_tf != TRANSFER_FUNC_PQ2084) {
if (app_tf == TRANSFER_FUNC_PQ2084)
infopacket->sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active]
else {
infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active]
if (app_tf == TRANSFER_FUNC_GAMMA_22)
infopacket->sb[9] |= 0x04; // PB6 = [Bit 2 = Gamma 2.2 EOTF Active]
infopacket->sb[9] |= 0x04; // PB9 = [Bit 2 = Gamma 2.2 EOTF Active]
}
}
}