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xusb: bulk commit to split

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This commit is contained in:
Thomas Makin
2025-11-08 03:19:00 +00:00
parent 3c44c277e3
commit b86244cb58
5 changed files with 46 additions and 9 deletions
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1
drivers/pci/controller/pci-tegra.c
View File

@@ -3003,7 +3003,6 @@ static int tegra_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct pci_host_bridge *host;
struct tegra_pcie_port *port;
struct tegra_pcie *pcie;
int err;

36
drivers/phy/tegra/xusb-tegra210.c
View File

@@ -489,6 +489,32 @@ static int t210b01_compatible(struct tegra_xusb_padctl *padctl)
return 0;
}
static bool plle_hw_sequence_is_enabled(struct tegra_xusb_padctl *padctl) {
if (t210b01_compatible(padctl))
return tegra210b01_plle_hw_sequence_is_enabled();
return tegra210_plle_hw_sequence_is_enabled();
}
static int plle_hw_sequence_start(struct tegra_xusb_padctl *padctl) {
if (t210b01_compatible(padctl))
return tegra210b01_plle_hw_sequence_start();
return tegra210_plle_hw_sequence_start();
}
static void xusb_pll_hw_control_enable(struct tegra_xusb_padctl *padctl) {
if (t210b01_compatible(padctl))
tegra210b01_xusb_pll_hw_control_enable();
else
return tegra210_xusb_pll_hw_control_enable();
}
static void xusb_pll_hw_sequence_start(struct tegra_xusb_padctl *padctl) {
if (t210b01_compatible(padctl))
tegra210b01_xusb_pll_hw_sequence_start();
else
tegra210_xusb_pll_hw_sequence_start();
}
static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane)
{
const struct tegra_xusb_lane_map *map;
@@ -529,7 +555,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
return err;
}
if (tegra210_plle_hw_sequence_is_enabled())
if (plle_hw_sequence_is_enabled(padctl))
goto skip_pll_init;
err = reset_control_deassert(pcie->rst);
@@ -708,7 +734,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
tegra210_xusb_pll_hw_control_enable();
xusb_pll_hw_control_enable(padctl);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
@@ -724,7 +750,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
usleep_range(10, 20);
tegra210_xusb_pll_hw_sequence_start();
xusb_pll_hw_sequence_start(padctl);
skip_pll_init:
pcie->enable = true;
@@ -1077,8 +1103,8 @@ static int tegra210_uphy_init(struct tegra_xusb_padctl *padctl)
if (padctl->sata)
tegra210_sata_uphy_enable(padctl);
if (!tegra210_plle_hw_sequence_is_enabled())
tegra210_plle_hw_sequence_start();
if (!plle_hw_sequence_is_enabled(padctl))
plle_hw_sequence_start(padctl);
else
dev_dbg(padctl->dev, "PLLE is already in HW control\n");

1
drivers/phy/tegra/xusb.h
View File

@@ -244,6 +244,7 @@ struct tegra_xusb_pcie_pad {
struct reset_control *rst;
struct clk *pll;
struct clk *uphy_mgmt_clk;
bool enable;
};

13
drivers/usb/host/xhci-tegra.c
View File

@@ -2546,27 +2546,34 @@ static const struct tegra_xusb_soc tegra210_soc = {
};
MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
static const struct tegra_xusb_phy_type tegra210b01_phy_types[] = {
{ .name = "usb3", .num = 4, },
{ .name = "usb2", .num = 4, },
};
static const struct tegra_xusb_soc tegra210b01_soc = {
.firmware = "nvidia/tegra210b01/xusb.bin",
.supply_names = tegra210_supply_names,
.num_supplies = ARRAY_SIZE(tegra210_supply_names),
.phy_types = tegra210_phy_types,
.num_types = ARRAY_SIZE(tegra210_phy_types),
.phy_types = tegra210b01_phy_types,
.num_types = ARRAY_SIZE(tegra210b01_phy_types),
.context = &tegra124_xusb_context,
.ports = {
.usb2 = { .offset = 4, .count = 4, },
.hsic = { .offset = 8, .count = 1, },
.usb3 = { .offset = 0, .count = 4, },
},
.scale_ss_clock = false,
.has_ipfs = true,
.otg_reset_sspi = true,
.ops = &tegra124_ops,
.mbox = {
.cmd = 0xe4,
.data_in = 0xe8,
.data_out = 0xec,
.owner = 0xf0,
.smi_intr = XUSB_CFG_ARU_SMI_INTR,
},
.lpm_support = false,
};
MODULE_FIRMWARE("nvidia/tegra210b01/xusb.bin");

4
include/linux/clk/tegra.h
View File

@@ -208,9 +208,13 @@ tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
#ifdef CONFIG_ARCH_TEGRA_210_SOC
int tegra210_plle_hw_sequence_start(void);
int tegra210b01_plle_hw_sequence_start(void);
bool tegra210_plle_hw_sequence_is_enabled(void);
bool tegra210b01_plle_hw_sequence_is_enabled(void);
void tegra210_xusb_pll_hw_control_enable(void);
void tegra210b01_xusb_pll_hw_control_enable(void);
void tegra210_xusb_pll_hw_sequence_start(void);
void tegra210b01_xusb_pll_hw_sequence_start(void);
void tegra210_sata_pll_hw_control_enable(void);
void tegra210_sata_pll_hw_sequence_start(void);
void tegra210_set_sata_pll_seq_sw(bool state);