diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 0433072b6d01..d8d6c233741c 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -3003,7 +3003,6 @@ static int tegra_pcie_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct pci_host_bridge *host;
-	struct tegra_pcie_port *port;
 	struct tegra_pcie *pcie;
 	int err;
 
diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index 8ff995171225..92b708fc5b52 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -489,6 +489,32 @@ static int t210b01_compatible(struct tegra_xusb_padctl *padctl)
 	return 0;
 }
 
+static bool plle_hw_sequence_is_enabled(struct tegra_xusb_padctl *padctl) {
+	if (t210b01_compatible(padctl))
+		return tegra210b01_plle_hw_sequence_is_enabled();
+	return tegra210_plle_hw_sequence_is_enabled();
+}
+
+static int plle_hw_sequence_start(struct tegra_xusb_padctl *padctl) {
+	if (t210b01_compatible(padctl))
+		return tegra210b01_plle_hw_sequence_start();
+	return tegra210_plle_hw_sequence_start();
+}
+
+static void xusb_pll_hw_control_enable(struct tegra_xusb_padctl *padctl) {
+	if (t210b01_compatible(padctl))
+		tegra210b01_xusb_pll_hw_control_enable();
+	else
+		return tegra210_xusb_pll_hw_control_enable();
+}
+
+static void xusb_pll_hw_sequence_start(struct tegra_xusb_padctl *padctl) {
+	if (t210b01_compatible(padctl))
+		tegra210b01_xusb_pll_hw_sequence_start();
+	else
+		tegra210_xusb_pll_hw_sequence_start();
+}
+
 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane)
 {
 	const struct tegra_xusb_lane_map *map;
@@ -529,7 +555,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 			return err;
 	}
 
-	if (tegra210_plle_hw_sequence_is_enabled())
+	if (plle_hw_sequence_is_enabled(padctl))
 		goto skip_pll_init;
 
 	err = reset_control_deassert(pcie->rst);
@@ -708,7 +734,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 	value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 
-	tegra210_xusb_pll_hw_control_enable();
+	xusb_pll_hw_control_enable(padctl);
 
 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 	value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
@@ -724,7 +750,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 
 	usleep_range(10, 20);
 
-	tegra210_xusb_pll_hw_sequence_start();
+	xusb_pll_hw_sequence_start(padctl);
 
 skip_pll_init:
 	pcie->enable = true;
@@ -1077,8 +1103,8 @@ static int tegra210_uphy_init(struct tegra_xusb_padctl *padctl)
 	if (padctl->sata)
 		tegra210_sata_uphy_enable(padctl);
 
-	if (!tegra210_plle_hw_sequence_is_enabled())
-		tegra210_plle_hw_sequence_start();
+	if (!plle_hw_sequence_is_enabled(padctl))
+		plle_hw_sequence_start(padctl);
 	else
 		dev_dbg(padctl->dev, "PLLE is already in HW control\n");
 
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index a2074dd37704..a3a11133561f 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -244,6 +244,7 @@ struct tegra_xusb_pcie_pad {
 
 	struct reset_control *rst;
 	struct clk *pll;
+	struct clk *uphy_mgmt_clk;
 
 	bool enable;
 };
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
index a0bd51a757a6..92ee483b1898 100644
--- a/drivers/usb/host/xhci-tegra.c
+++ b/drivers/usb/host/xhci-tegra.c
@@ -2546,27 +2546,34 @@ static const struct tegra_xusb_soc tegra210_soc = {
 };
 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
 
+static const struct tegra_xusb_phy_type tegra210b01_phy_types[] = {
+	{ .name = "usb3", .num = 4, },
+	{ .name = "usb2", .num = 4, },
+};
+
 static const struct tegra_xusb_soc tegra210b01_soc = {
 	.firmware = "nvidia/tegra210b01/xusb.bin",
 	.supply_names = tegra210_supply_names,
 	.num_supplies = ARRAY_SIZE(tegra210_supply_names),
-	.phy_types = tegra210_phy_types,
-	.num_types = ARRAY_SIZE(tegra210_phy_types),
+	.phy_types = tegra210b01_phy_types,
+	.num_types = ARRAY_SIZE(tegra210b01_phy_types),
 	.context = &tegra124_xusb_context,
 	.ports = {
 		.usb2 = { .offset = 4, .count = 4, },
-		.hsic = { .offset = 8, .count = 1, },
 		.usb3 = { .offset = 0, .count = 4, },
 	},
 	.scale_ss_clock = false,
 	.has_ipfs = true,
 	.otg_reset_sspi = true,
+	.ops = &tegra124_ops,
 	.mbox = {
 		.cmd = 0xe4,
 		.data_in = 0xe8,
 		.data_out = 0xec,
 		.owner = 0xf0,
+		.smi_intr = XUSB_CFG_ARU_SMI_INTR,
 	},
+	.lpm_support = false,
 };
 MODULE_FIRMWARE("nvidia/tegra210b01/xusb.bin");
 
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 3650e926e93f..d169c5a0d8ec 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -208,9 +208,13 @@ tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
 
 #ifdef CONFIG_ARCH_TEGRA_210_SOC
 int tegra210_plle_hw_sequence_start(void);
+int tegra210b01_plle_hw_sequence_start(void);
 bool tegra210_plle_hw_sequence_is_enabled(void);
+bool tegra210b01_plle_hw_sequence_is_enabled(void);
 void tegra210_xusb_pll_hw_control_enable(void);
+void tegra210b01_xusb_pll_hw_control_enable(void);
 void tegra210_xusb_pll_hw_sequence_start(void);
+void tegra210b01_xusb_pll_hw_sequence_start(void);
 void tegra210_sata_pll_hw_control_enable(void);
 void tegra210_sata_pll_hw_sequence_start(void);
 void tegra210_set_sata_pll_seq_sw(bool state);