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@@ -57,6 +57,8 @@
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#define RMB_PMI_META_DATA_REG 0x10
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#define RMB_PMI_CODE_START_REG 0x14
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#define RMB_PMI_CODE_LENGTH_REG 0x18
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#define RMB_MBA_MSS_STATUS 0x40
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#define RMB_MBA_ALT_RESET 0x44
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#define RMB_CMD_META_DATA_READY 0x1
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#define RMB_CMD_LOAD_READY 0x2
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@@ -104,6 +106,13 @@
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#define QDSP6SS_XO_CBCR 0x0038
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#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
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/* QDSP6v65 parameters */
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#define QDSP6SS_SLEEP 0x3C
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#define QDSP6SS_BOOT_CORE_START 0x400
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#define QDSP6SS_BOOT_CMD 0x404
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#define SLEEP_CHECK_MAX_LOOPS 200
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#define BOOT_FSM_TIMEOUT 10000
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struct reg_info {
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struct regulator *reg;
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int uV;
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@@ -121,9 +130,11 @@ struct rproc_hexagon_res {
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struct qcom_mss_reg_res *proxy_supply;
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struct qcom_mss_reg_res *active_supply;
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char **proxy_clk_names;
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char **reset_clk_names;
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char **active_clk_names;
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int version;
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bool need_mem_protection;
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bool has_alt_reset;
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};
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struct q6v5 {
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@@ -143,9 +154,15 @@ struct q6v5 {
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struct qcom_smem_state *state;
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unsigned stop_bit;
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int handover_irq;
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bool proxy_unvoted;
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struct clk *active_clks[8];
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struct clk *reset_clks[4];
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struct clk *proxy_clks[4];
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int active_clk_count;
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int reset_clk_count;
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int proxy_clk_count;
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struct reg_info active_regs[1];
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@@ -166,10 +183,12 @@ struct q6v5 {
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void *mpss_region;
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size_t mpss_size;
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struct qcom_rproc_glink glink_subdev;
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struct qcom_rproc_subdev smd_subdev;
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struct qcom_rproc_ssr ssr_subdev;
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struct qcom_sysmon *sysmon;
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bool need_mem_protection;
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bool has_alt_reset;
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int mpss_perm;
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int mba_perm;
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int version;
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@@ -179,6 +198,7 @@ enum {
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MSS_MSM8916,
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MSS_MSM8974,
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MSS_MSM8996,
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MSS_SDM845,
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};
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static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
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@@ -333,6 +353,29 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
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return 0;
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}
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static int q6v5_reset_assert(struct q6v5 *qproc)
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{
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if (qproc->has_alt_reset)
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return reset_control_reset(qproc->mss_restart);
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else
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return reset_control_assert(qproc->mss_restart);
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}
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static int q6v5_reset_deassert(struct q6v5 *qproc)
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{
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int ret;
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if (qproc->has_alt_reset) {
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writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
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ret = reset_control_reset(qproc->mss_restart);
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writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
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} else {
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ret = reset_control_deassert(qproc->mss_restart);
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}
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return ret;
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}
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static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
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{
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unsigned long timeout;
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@@ -385,8 +428,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
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int ret;
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int i;
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if (qproc->version == MSS_SDM845) {
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val = readl(qproc->reg_base + QDSP6SS_SLEEP);
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val |= 0x1;
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writel(val, qproc->reg_base + QDSP6SS_SLEEP);
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if (qproc->version == MSS_MSM8996) {
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ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
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val, !(val & BIT(31)), 1,
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SLEEP_CHECK_MAX_LOOPS);
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if (ret) {
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dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
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return -ETIMEDOUT;
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}
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/* De-assert QDSP6 stop core */
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writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
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/* Trigger boot FSM */
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writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
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ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
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val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
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if (ret) {
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dev_err(qproc->dev, "Boot FSM failed to complete.\n");
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/* Reset the modem so that boot FSM is in reset state */
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q6v5_reset_deassert(qproc);
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return ret;
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}
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goto pbl_wait;
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} else if (qproc->version == MSS_MSM8996) {
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/* Override the ACC value if required */
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writel(QDSP6SS_ACC_OVERRIDE_VAL,
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qproc->reg_base + QDSP6SS_STRAP_ACC);
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@@ -494,6 +564,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
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val &= ~Q6SS_STOP_CORE;
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writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
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pbl_wait:
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/* Wait for PBL status */
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ret = q6v5_rmb_pbl_wait(qproc, 1000);
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if (ret == -ETIMEDOUT) {
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@@ -727,11 +798,15 @@ static int q6v5_start(struct rproc *rproc)
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int xfermemop_ret;
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int ret;
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qproc->proxy_unvoted = false;
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enable_irq(qproc->handover_irq);
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ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
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qproc->proxy_reg_count);
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if (ret) {
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dev_err(qproc->dev, "failed to enable proxy supplies\n");
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return ret;
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goto disable_irqs;
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}
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ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
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@@ -747,10 +822,18 @@ static int q6v5_start(struct rproc *rproc)
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dev_err(qproc->dev, "failed to enable supplies\n");
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goto disable_proxy_clk;
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}
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ret = reset_control_deassert(qproc->mss_restart);
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ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
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qproc->reset_clk_count);
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if (ret) {
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dev_err(qproc->dev, "failed to enable reset clocks\n");
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goto disable_vdd;
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}
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ret = q6v5_reset_deassert(qproc);
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if (ret) {
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dev_err(qproc->dev, "failed to deassert mss restart\n");
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goto disable_vdd;
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goto disable_reset_clks;
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}
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ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
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@@ -761,13 +844,11 @@ static int q6v5_start(struct rproc *rproc)
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}
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/* Assign MBA image access in DDR to q6 */
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xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
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qproc->mba_phys,
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qproc->mba_size);
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if (xfermemop_ret) {
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ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
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qproc->mba_phys, qproc->mba_size);
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if (ret) {
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dev_err(qproc->dev,
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"assigning Q6 access to mba memory failed: %d\n",
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xfermemop_ret);
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"assigning Q6 access to mba memory failed: %d\n", ret);
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goto disable_active_clks;
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}
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@@ -810,11 +891,6 @@ static int q6v5_start(struct rproc *rproc)
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"Failed to reclaim mba buffer system may become unstable\n");
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qproc->running = true;
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q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
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qproc->proxy_clk_count);
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q6v5_regulator_disable(qproc, qproc->proxy_regs,
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qproc->proxy_reg_count);
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return 0;
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reclaim_mpss:
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@@ -842,7 +918,10 @@ disable_active_clks:
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qproc->active_clk_count);
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assert_reset:
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reset_control_assert(qproc->mss_restart);
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q6v5_reset_assert(qproc);
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disable_reset_clks:
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q6v5_clk_disable(qproc->dev, qproc->reset_clks,
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qproc->reset_clk_count);
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disable_vdd:
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q6v5_regulator_disable(qproc, qproc->active_regs,
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qproc->active_reg_count);
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@@ -853,6 +932,9 @@ disable_proxy_reg:
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q6v5_regulator_disable(qproc, qproc->proxy_regs,
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qproc->proxy_reg_count);
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disable_irqs:
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disable_irq(qproc->handover_irq);
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return ret;
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}
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@@ -892,7 +974,19 @@ static int q6v5_stop(struct rproc *rproc)
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qproc->mpss_phys, qproc->mpss_size);
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WARN_ON(ret);
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reset_control_assert(qproc->mss_restart);
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q6v5_reset_assert(qproc);
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disable_irq(qproc->handover_irq);
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if (!qproc->proxy_unvoted) {
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q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
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qproc->proxy_clk_count);
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q6v5_regulator_disable(qproc, qproc->proxy_regs,
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qproc->proxy_reg_count);
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}
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q6v5_clk_disable(qproc->dev, qproc->reset_clks,
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qproc->reset_clk_count);
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q6v5_clk_disable(qproc->dev, qproc->active_clks,
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qproc->active_clk_count);
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q6v5_regulator_disable(qproc, qproc->active_regs,
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@@ -960,7 +1054,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
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return IRQ_HANDLED;
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}
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static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
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static irqreturn_t q6v5_ready_interrupt(int irq, void *dev)
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{
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struct q6v5 *qproc = dev;
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@@ -968,6 +1062,20 @@ static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
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return IRQ_HANDLED;
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}
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static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
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{
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struct q6v5 *qproc = dev;
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q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
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qproc->proxy_clk_count);
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q6v5_regulator_disable(qproc, qproc->proxy_regs,
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qproc->proxy_reg_count);
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qproc->proxy_unvoted = true;
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return IRQ_HANDLED;
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}
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static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev)
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{
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struct q6v5 *qproc = dev;
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@@ -1051,22 +1159,23 @@ static int q6v5_request_irq(struct q6v5 *qproc,
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const char *name,
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irq_handler_t thread_fn)
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{
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int irq;
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int ret;
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ret = platform_get_irq_byname(pdev, name);
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if (ret < 0) {
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irq = platform_get_irq_byname(pdev, name);
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if (irq < 0) {
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dev_err(&pdev->dev, "no %s IRQ defined\n", name);
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return ret;
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return irq;
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}
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ret = devm_request_threaded_irq(&pdev->dev, ret,
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ret = devm_request_threaded_irq(&pdev->dev, irq,
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NULL, thread_fn,
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IRQF_TRIGGER_RISING | IRQF_ONESHOT,
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"q6v5", qproc);
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|
|
if (ret)
|
|
|
|
|
dev_err(&pdev->dev, "request %s IRQ failed\n", name);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
return ret ? : irq;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int q6v5_alloc_memory_region(struct q6v5 *qproc)
|
|
|
|
@@ -1157,6 +1266,14 @@ static int q6v5_probe(struct platform_device *pdev)
|
|
|
|
|
}
|
|
|
|
|
qproc->proxy_clk_count = ret;
|
|
|
|
|
|
|
|
|
|
ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
|
|
|
|
|
desc->reset_clk_names);
|
|
|
|
|
if (ret < 0) {
|
|
|
|
|
dev_err(&pdev->dev, "Failed to get reset clocks.\n");
|
|
|
|
|
goto free_rproc;
|
|
|
|
|
}
|
|
|
|
|
qproc->reset_clk_count = ret;
|
|
|
|
|
|
|
|
|
|
ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
|
|
|
|
|
desc->active_clk_names);
|
|
|
|
|
if (ret < 0) {
|
|
|
|
@@ -1186,6 +1303,7 @@ static int q6v5_probe(struct platform_device *pdev)
|
|
|
|
|
goto free_rproc;
|
|
|
|
|
|
|
|
|
|
qproc->version = desc->version;
|
|
|
|
|
qproc->has_alt_reset = desc->has_alt_reset;
|
|
|
|
|
qproc->need_mem_protection = desc->need_mem_protection;
|
|
|
|
|
ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
|
|
|
|
|
if (ret < 0)
|
|
|
|
@@ -1195,9 +1313,15 @@ static int q6v5_probe(struct platform_device *pdev)
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
goto free_rproc;
|
|
|
|
|
|
|
|
|
|
ret = q6v5_request_irq(qproc, pdev, "ready", q6v5_ready_interrupt);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
goto free_rproc;
|
|
|
|
|
|
|
|
|
|
ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
goto free_rproc;
|
|
|
|
|
qproc->handover_irq = ret;
|
|
|
|
|
disable_irq(qproc->handover_irq);
|
|
|
|
|
|
|
|
|
|
ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt);
|
|
|
|
|
if (ret < 0)
|
|
|
|
@@ -1210,6 +1334,7 @@ static int q6v5_probe(struct platform_device *pdev)
|
|
|
|
|
}
|
|
|
|
|
qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
|
|
|
|
|
qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
|
|
|
|
|
qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
|
|
|
|
|
qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
|
|
|
|
|
qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
|
|
|
|
|
qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
|
|
|
|
@@ -1233,6 +1358,7 @@ static int q6v5_remove(struct platform_device *pdev)
|
|
|
|
|
rproc_del(qproc->rproc);
|
|
|
|
|
|
|
|
|
|
qcom_remove_sysmon_subdev(qproc->sysmon);
|
|
|
|
|
qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
|
|
|
|
|
qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
|
|
|
|
|
qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
|
|
|
|
|
rproc_free(qproc->rproc);
|
|
|
|
@@ -1240,6 +1366,31 @@ static int q6v5_remove(struct platform_device *pdev)
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct rproc_hexagon_res sdm845_mss = {
|
|
|
|
|
.hexagon_mba_image = "mba.mbn",
|
|
|
|
|
.proxy_clk_names = (char*[]){
|
|
|
|
|
"xo",
|
|
|
|
|
"axis2",
|
|
|
|
|
"prng",
|
|
|
|
|
NULL
|
|
|
|
|
},
|
|
|
|
|
.reset_clk_names = (char*[]){
|
|
|
|
|
"iface",
|
|
|
|
|
"snoc_axi",
|
|
|
|
|
NULL
|
|
|
|
|
},
|
|
|
|
|
.active_clk_names = (char*[]){
|
|
|
|
|
"bus",
|
|
|
|
|
"mem",
|
|
|
|
|
"gpll0_mss",
|
|
|
|
|
"mnoc_axi",
|
|
|
|
|
NULL
|
|
|
|
|
},
|
|
|
|
|
.need_mem_protection = true,
|
|
|
|
|
.has_alt_reset = true,
|
|
|
|
|
.version = MSS_SDM845,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct rproc_hexagon_res msm8996_mss = {
|
|
|
|
|
.hexagon_mba_image = "mba.mbn",
|
|
|
|
|
.proxy_clk_names = (char*[]){
|
|
|
|
@@ -1255,6 +1406,7 @@ static const struct rproc_hexagon_res msm8996_mss = {
|
|
|
|
|
NULL
|
|
|
|
|
},
|
|
|
|
|
.need_mem_protection = true,
|
|
|
|
|
.has_alt_reset = false,
|
|
|
|
|
.version = MSS_MSM8996,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
@@ -1286,6 +1438,7 @@ static const struct rproc_hexagon_res msm8916_mss = {
|
|
|
|
|
NULL
|
|
|
|
|
},
|
|
|
|
|
.need_mem_protection = false,
|
|
|
|
|
.has_alt_reset = false,
|
|
|
|
|
.version = MSS_MSM8916,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
@@ -1325,6 +1478,7 @@ static const struct rproc_hexagon_res msm8974_mss = {
|
|
|
|
|
NULL
|
|
|
|
|
},
|
|
|
|
|
.need_mem_protection = false,
|
|
|
|
|
.has_alt_reset = false,
|
|
|
|
|
.version = MSS_MSM8974,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
@@ -1333,6 +1487,7 @@ static const struct of_device_id q6v5_of_match[] = {
|
|
|
|
|
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
|
|
|
|
|
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
|
|
|
|
|
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
|
|
|
|
|
{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
|
|
|
|
|
{ },
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(of, q6v5_of_match);
|
|
|
|
|