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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

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This commit is contained in:
Larry Finger
2010-08-29 10:33:29 -05:00
parent 0a2f38193d 29cfcddc0e
commit a3656d897d
152 changed files with 902 additions and 1437 deletions
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Documentation/lguest/Makefile
+2 -1
View File
@@ -1,5 +1,6 @@
# This creates the demonstration utility "lguest" which runs a Linux guest.
CFLAGS:=-m32 -Wall -Wmissing-declarations -Wmissing-prototypes -O3 -I../../include -I../../arch/x86/include -U_FORTIFY_SOURCE
# Missing headers? Add "-I../../include -I../../arch/x86/include"
CFLAGS:=-m32 -Wall -Wmissing-declarations -Wmissing-prototypes -O3 -U_FORTIFY_SOURCE
all: lguest
Documentation/lguest/lguest.c
+12 -11
View File
@@ -39,14 +39,14 @@
#include <limits.h>
#include <stddef.h>
#include <signal.h>
#include "linux/lguest_launcher.h"
#include "linux/virtio_config.h"
#include "linux/virtio_net.h"
#include "linux/virtio_blk.h"
#include "linux/virtio_console.h"
#include "linux/virtio_rng.h"
#include "linux/virtio_ring.h"
#include "asm/bootparam.h"
#include <linux/virtio_config.h>
#include <linux/virtio_net.h>
#include <linux/virtio_blk.h>
#include <linux/virtio_console.h>
#include <linux/virtio_rng.h>
#include <linux/virtio_ring.h>
#include <asm/bootparam.h>
#include "../../include/linux/lguest_launcher.h"
/*L:110
* We can ignore the 42 include files we need for this program, but I do want
* to draw attention to the use of kernel-style types.
@@ -1447,14 +1447,15 @@ static void add_to_bridge(int fd, const char *if_name, const char *br_name)
static void configure_device(int fd, const char *tapif, u32 ipaddr)
{
struct ifreq ifr;
struct sockaddr_in *sin = (struct sockaddr_in *)&ifr.ifr_addr;
struct sockaddr_in sin;
memset(&ifr, 0, sizeof(ifr));
strcpy(ifr.ifr_name, tapif);
/* Don't read these incantations. Just cut & paste them like I did! */
sin->sin_family = AF_INET;
sin->sin_addr.s_addr = htonl(ipaddr);
sin.sin_family = AF_INET;
sin.sin_addr.s_addr = htonl(ipaddr);
memcpy(&ifr.ifr_addr, &sin, sizeof(sin));
if (ioctl(fd, SIOCSIFADDR, &ifr) != 0)
err(1, "Setting %s interface address", tapif);
ifr.ifr_flags = IFF_UP;
MAINTAINERS
+7 -1
View File
@@ -2296,6 +2296,12 @@ S: Maintained
F: Documentation/hwmon/f71805f
F: drivers/hwmon/f71805f.c
FANOTIFY
M: Eric Paris <eparis@redhat.com>
S: Maintained
F: fs/notify/fanotify/
F: include/linux/fanotify.h
FARSYNC SYNCHRONOUS DRIVER
M: Kevin Curtis <kevin.curtis@farsite.co.uk>
W: http://www.farsite.co.uk/
@@ -3488,7 +3494,7 @@ LGUEST
M: Rusty Russell <rusty@rustcorp.com.au>
L: lguest@lists.ozlabs.org
W: http://lguest.ozlabs.org/
S: Maintained
S: Odd Fixes
F: Documentation/lguest/
F: arch/x86/lguest/
F: drivers/lguest/
arch/alpha/kernel/osf_sys.c
+1 -1
View File
@@ -252,7 +252,7 @@ SYSCALL_DEFINE3(osf_statfs, const char __user *, pathname,
retval = user_path(pathname, &path);
if (!retval) {
retval = do_osf_statfs(&path buffer, bufsiz);
retval = do_osf_statfs(&path, buffer, bufsiz);
path_put(&path);
}
return retval;
arch/arm/Kconfig
+2 -1
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@@ -1622,7 +1622,8 @@ config ZRELADDR
default 0x40008000 if ARCH_STMP378X ||\
ARCH_STMP37XX ||\
ARCH_SH7372 ||\
ARCH_SH7377
ARCH_SH7377 ||\
ARCH_S5PV310
default 0x50008000 if ARCH_S3C64XX ||\
ARCH_SH7367
default 0x60008000 if ARCH_VEXPRESS
arch/arm/configs/omap_4430sdp_defconfig
+3
View File
@@ -13,6 +13,9 @@ CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_OMAP4=y
# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
# CONFIG_ARCH_OMAP2 is not set
# CONFIG_ARCH_OMAP3 is not set
# CONFIG_OMAP_MUX is not set
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP_DM_TIMER=y
arch/arm/kernel/etm.c
+1 -1
View File
@@ -230,7 +230,7 @@ static void etm_dump(void)
etb_lock(t);
}
static void sysrq_etm_dump(int key, struct tty_struct *tty)
static void sysrq_etm_dump(int key)
{
dev_dbg(tracer.dev, "Dumping ETB buffer\n");
etm_dump();
arch/arm/mach-omap2/Makefile
+1
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@@ -25,6 +25,7 @@ obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o
obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a
AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a
# Functions loaded to SRAM
arch/arm/mach-omap2/clock3xxx_data.c
+7 -7
View File
@@ -3417,7 +3417,13 @@ int __init omap3xxx_clk_init(void)
struct omap_clk *c;
u32 cpu_clkflg = CK_3XXX;
if (cpu_is_omap34xx()) {
if (cpu_is_omap3517()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3517;
} else if (cpu_is_omap3505()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3505;
} else if (cpu_is_omap34xx()) {
cpu_mask = RATE_IN_3XXX;
cpu_clkflg |= CK_343X;
@@ -3432,12 +3438,6 @@ int __init omap3xxx_clk_init(void)
cpu_mask |= RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3430ES2;
}
} else if (cpu_is_omap3517()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3517;
} else if (cpu_is_omap3505()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3505;
}
if (omap3_has_192mhz_clk())
arch/arm/mach-omap2/id.c
+1 -1
View File
@@ -284,8 +284,8 @@ static void __init omap3_check_revision(void)
default:
omap_revision = OMAP3630_REV_ES1_2;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
break;
}
break;
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP3630_REV_ES1_2;
arch/arm/mach-omap2/include/mach/entry-macro.S
+4 -2
View File
@@ -177,7 +177,10 @@ omap_irq_base: .word 0
cmpne \irqnr, \tmp
cmpcs \irqnr, \irqnr
.endm
#endif
#endif /* MULTI_OMAP2 */
#ifdef CONFIG_SMP
/* We assume that irqstat (the raw value of the IRQ acknowledge
* register) is preserved from the macro above.
* If there is an IPI, we immediately signal end of interrupt
@@ -205,8 +208,7 @@ omap_irq_base: .word 0
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm
#endif
#endif /* MULTI_OMAP2 */
#endif /* CONFIG_SMP */
.macro irq_prio_table
.endm
arch/arm/mach-omap2/omap-smp.c
+1 -2
View File
@@ -102,8 +102,7 @@ static void __init wakeup_secondary(void)
* Send a 'sev' to wake the secondary core from WFE.
* Drain the outstanding writes to memory
*/
dsb();
set_event();
dsb_sev();
mb();
}
arch/arm/mach-omap2/pm34xx.c
+3 -1
View File
@@ -480,7 +480,9 @@ void omap_sram_idle(void)
}
/* Disable IO-PAD and IO-CHAIN wakeup */
if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) {
if (omap3_has_io_wakeup() &&
(per_next_state < PWRDM_POWER_ON ||
core_next_state < PWRDM_POWER_ON)) {
prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
omap3_disable_io_chain();
}
arch/arm/mach-s3c2410/include/mach/vmalloc.h
+1 -1
View File
@@ -15,6 +15,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
arch/arm/mach-s3c64xx/include/mach/vmalloc.h
+1 -1
View File
@@ -15,6 +15,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
arch/arm/mach-s5p6440/include/mach/vmalloc.h
+1 -1
View File
@@ -12,6 +12,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
arch/arm/mach-s5p6442/include/mach/vmalloc.h
+1 -1
View File
@@ -12,6 +12,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
arch/arm/mach-s5pv210/include/mach/vmalloc.h
+1 -1
View File
@@ -17,6 +17,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H __FILE__
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END (0xE0000000UL)
#endif /* __ASM_ARCH_VMALLOC_H */
arch/arm/mach-s5pv310/clock.c
+63 -19
View File
@@ -30,6 +30,16 @@ static struct clk clk_sclk_hdmi27m = {
.rate = 27000000,
};
static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
}
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
}
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@@ -39,6 +49,14 @@ static struct clksrc_clk clk_mout_apll = {
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
};
static struct clksrc_clk clk_sclk_apll = {
.clk = {
.name = "sclk_apll",
.id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
};
@@ -61,7 +79,7 @@ static struct clksrc_clk clk_mout_mpll = {
};
static struct clk *clkset_moutcore_list[] = {
[0] = &clk_mout_apll.clk,
[0] = &clk_sclk_apll.clk,
[1] = &clk_mout_mpll.clk,
};
@@ -154,7 +172,7 @@ static struct clksrc_clk clk_pclk_dbg = {
static struct clk *clkset_corebus_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_mout_apll.clk,
[1] = &clk_sclk_apll.clk,
};
static struct clksrc_sources clkset_mout_corebus = {
@@ -220,7 +238,7 @@ static struct clksrc_clk clk_pclk_acp = {
static struct clk *clkset_aclk_top_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_mout_apll.clk,
[1] = &clk_sclk_apll.clk,
};
static struct clksrc_sources clkset_aclk_200 = {
@@ -321,11 +339,6 @@ static struct clksrc_clk clk_sclk_vpll = {
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
};
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
}
static struct clk init_clocks_disable[] = {
{
.name = "timers",
@@ -337,7 +350,37 @@ static struct clk init_clocks_disable[] = {
};
static struct clk init_clocks[] = {
/* Nothing here yet */
{
.name = "uart",
.id = 0,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
.id = 1,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 2,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 3,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.id = 4,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
.id = 5,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5),
}
};
static struct clk *clkset_group_list[] = {
@@ -359,8 +402,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 0,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
.enable = s5pv310_clk_ip_peril_ctrl,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
@@ -369,8 +412,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 1,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
@@ -379,8 +422,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 2,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
@@ -389,8 +432,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 3,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
@@ -399,7 +442,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_pwm",
.id = -1,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_group,
@@ -411,6 +454,7 @@ static struct clksrc_clk clksrcs[] = {
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
&clk_sclk_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_moutcore,
@@ -470,11 +514,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
__raw_readl(S5P_EPLL_CON1), pll_4500);
__raw_readl(S5P_EPLL_CON1), pll_4600);
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
__raw_readl(S5P_VPLL_CON1), pll_4502);
__raw_readl(S5P_VPLL_CON1), pll_4650);
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
arch/arm/mach-s5pv310/cpu.c
+10
View File
@@ -45,6 +45,16 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(S5PV310_PA_CMU),
.length = SZ_128K,
.type = MT_DEVICE,
},
};
arch/arm/mach-s5pv310/include/mach/irqs.h
+7 -4
View File
@@ -15,12 +15,14 @@
#include <plat/irqs.h>
/* Private Peripheral Interrupt */
/* PPI: Private Peripheral Interrupt */
#define IRQ_PPI(x) S5P_IRQ(x+16)
#define IRQ_LOCALTIMER IRQ_PPI(13)
/* Shared Peripheral Interrupt */
/* SPI: Shared Peripheral Interrupt */
#define IRQ_SPI(x) S5P_IRQ(x+32)
#define IRQ_EINT0 IRQ_SPI(40)
@@ -36,7 +38,7 @@
#define IRQ_PCIE IRQ_SPI(50)
#define IRQ_SYSTEM_TIMER IRQ_SPI(51)
#define IRQ_MFC IRQ_SPI(52)
#define IRQ_WTD IRQ_SPI(53)
#define IRQ_WDT IRQ_SPI(53)
#define IRQ_AUDIO_SS IRQ_SPI(54)
#define IRQ_AC97 IRQ_SPI(55)
#define IRQ_SPDIF IRQ_SPI(56)
@@ -67,8 +69,9 @@
#define IRQ_IIC COMBINER_IRQ(27, 0)
/* Set the default NR_IRQS */
#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
#define MAX_COMBINER_NR 39
#endif /* ASM_ARCH_IRQS_H */
#endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach-s5pv310/include/mach/map.h
+14 -2
View File
@@ -23,12 +23,16 @@
#include <plat/map-s5p.h>
#define S5PV310_PA_SYSRAM (0x02025000)
#define S5PV310_PA_CHIPID (0x10000000)
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
#define S5PV310_PA_SYSCON (0x10020000)
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
#define S5PV310_PA_CMU (0x10030000)
#define S5PV310_PA_WATCHDOG (0x10060000)
#define S5PV310_PA_COMBINER (0x10448000)
@@ -39,8 +43,12 @@
#define S5PV310_PA_GIC_DIST (0x10501000)
#define S5PV310_PA_L2CC (0x10502000)
#define S5PV310_PA_GPIO (0x11000000)
#define S5P_PA_GPIO S5PV310_PA_GPIO
#define S5PV310_PA_GPIO1 (0x11400000)
#define S5PV310_PA_GPIO2 (0x11000000)
#define S5PV310_PA_GPIO3 (0x03860000)
#define S5P_PA_GPIO S5PV310_PA_GPIO1
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define S5PV310_PA_UART (0x13800000)
@@ -63,6 +71,10 @@
/* compatibiltiy defines. */
#define S3C_PA_UART S5PV310_PA_UART
#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
#define S3C_PA_IIC S5PV310_PA_IIC0
#define S3C_PA_WDT S5PV310_PA_WATCHDOG
arch/arm/mach-s5pv310/include/mach/regs-clock.h
+30 -29
View File
@@ -15,48 +15,49 @@
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
#define S5P_INFORM0 S5P_CLKREG(0x800)
#define S5P_EPLL_CON0 S5P_CLKREG(0x1C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x1C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x1C120)
#define S5P_VPLL_CON1 S5P_CLKREG(0x1C124)
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x1C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x1C214)
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x1C250)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x1C510)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x1C550)
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x1C554)
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x1C558)
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x1C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x1C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x1C564)
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x1C950)
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
#define S5P_CLKSRC_CORE S5P_CLKREG(0x20200)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x20500)
#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
#define S5P_APLL_LOCK S5P_CLKREG(0x24000)
#define S5P_MPLL_LOCK S5P_CLKREG(0x24004)
#define S5P_APLL_CON0 S5P_CLKREG(0x24100)
#define S5P_APLL_CON1 S5P_CLKREG(0x24104)
#define S5P_MPLL_CON0 S5P_CLKREG(0x24108)
#define S5P_MPLL_CON1 S5P_CLKREG(0x2410C)
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
#define S5P_CLKSRC_CPU S5P_CLKREG(0x24200)
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x24400)
#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
#define S5P_CLKDIV_CPU S5P_CLKREG(0x24500)
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x24600)
#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x24800)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
#endif /* __ASM_ARCH_REGS_CLOCK_H */
arch/arm/mach-s5pv310/include/mach/vmalloc.h
+1 -1
View File
@@ -17,6 +17,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H __FILE__
#define VMALLOC_END (0xF0000000)
#define VMALLOC_END (0xF0000000UL)
#endif /* __ASM_ARCH_VMALLOC_H */
arch/arm/mach-s5pv310/platsmp.c
+1 -1
View File
@@ -187,6 +187,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_INFORM0);
__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
}
}
arch/arm/mach-tegra/board-harmony.c
-2
View File
@@ -91,10 +91,8 @@ static void __init tegra_harmony_fixup(struct machine_desc *desc,
{
mi->nr_banks = 2;
mi->bank[0].start = PHYS_OFFSET;
mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
mi->bank[0].size = 448 * SZ_1M;
mi->bank[1].start = SZ_512M;
mi->bank[1].node = PHYS_TO_NID(SZ_512M);
mi->bank[1].size = SZ_512M;
}
arch/arm/mach-tegra/include/mach/vmalloc.h
+1 -1
View File
@@ -23,6 +23,6 @@
#include <asm/sizes.h>
#define VMALLOC_END 0xFE000000
#define VMALLOC_END 0xFE000000UL
#endif
arch/arm/plat-omap/include/plat/smp.h
-7
View File
@@ -19,13 +19,6 @@
#include <asm/hardware/gic.h>
/*
* set_event() is used to wake up secondary core from wfe using sev. ROM
* code puts the second core into wfe(standby).
*
*/
#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
/* Needed for secondary core boot */
extern void omap_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
arch/arm/plat-s5p/include/plat/map-s5p.h
+2
View File
@@ -17,6 +17,7 @@
#define S5P_VA_GPIO S3C_ADDR(0x00500000)
#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000)
#define S5P_VA_SROMC S3C_ADDR(0x01100000)
#define S5P_VA_SYSRAM S3C_ADDR(0x01180000)
#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000)
#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
@@ -29,6 +30,7 @@
#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
#define S5P_VA_L2CC S3C_ADDR(0x00900000)
#define S5P_VA_CMU S3C_ADDR(0x00920000)
#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_VA_UART0 S5P_VA_UART(0)
arch/blackfin/include/asm/bfin_sport.h
-6
View File
@@ -115,12 +115,6 @@ struct sport_register {
#endif
/* Workaround defBF*.h SPORT MMRs till they get cleansed */
#undef DTYPE_NORM
#undef SLEN
#undef SP_WOFF
#undef SP_WSIZE
/* SPORT_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
-82
View File
@@ -913,88 +913,6 @@
#define PH6 0x0040
#define PH7 0x0080
/* ******************* SERIAL PORT MASKS **************************************/
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
#define TXF 0x0008 /* Transmit FIFO Full Status */
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */
arch/blackfin/mach-bf527/boards/cm_bf527.c
-1
View File
@@ -145,7 +145,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),
arch/blackfin/mach-bf527/boards/ezbrd.c
-1
View File
@@ -149,7 +149,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),
arch/blackfin/mach-bf527/boards/ezkit.c
-1
View File
@@ -234,7 +234,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
-82
View File
@@ -922,88 +922,6 @@
#define PH14 0x4000
#define PH15 0x8000
/* ******************* SERIAL PORT MASKS **************************************/
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
#define TXF 0x0008 /* Transmit FIFO Full Status */
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */
arch/blackfin/mach-bf533/include/mach/defBF532.h
-92
View File
@@ -509,98 +509,6 @@
#define IREN_P 0x01
#define UCEN_P 0x00
/* ********** SERIAL PORT MASKS ********************** */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_TCR2 Masks */
#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
defined(__ADSPBF533__)
# define SLEN 0x001F /*TX Word Length */
#else
# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#endif
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* no companding */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
/* SLEN defined above */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
/*SPORTx_STAT Masks */
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
#define RUVF 0x0002 /*RX Underflow Status */
#define ROVF 0x0004 /*RX Overflow Status */
#define TXF 0x0008 /*TX FIFO Full Status */
#define TUVF 0x0010 /*TX Underflow Status */
#define TOVF 0x0020 /*TX Overflow Status */
#define TXHRE 0x0040 /*TX Hold Register Empty */
/*SPORTx_MCMC1 Masks */
#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
/* SPORTx_MCMC1 Macros */
#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0x0000F000 /*Multichannel Frame Delay */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
/* PPI_CONTROL Masks */
arch/blackfin/mach-bf537/include/mach/defBF534.h
-80
View File
@@ -1241,86 +1241,6 @@
#define PH14 0x4000
#define PH15 0x8000
/* ******************* SERIAL PORT MASKS **************************************/
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
#define TXF 0x0008 /* Transmit FIFO Full Status */
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */
arch/blackfin/mach-bf538/include/mach/defBF539.h
-107
View File
@@ -1610,113 +1610,6 @@
#define UCEN_P 0x00
/* ********** SERIAL PORT MASKS ********************** */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_RCR1 Deprecated Masks */
#define TULAW DTYPE_ULAW /* Compand Using u-Law */
#define TALAW DTYPE_ALAW /* Compand Using A-Law */
/* SPORTx_TCR2 Masks */
#ifdef _MISRA_RULES
#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
#else
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#endif /* _MISRA_RULES */
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* no companding */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR1 Deprecated Masks */
#define RULAW DTYPE_ULAW /* Compand Using u-Law */
#define RALAW DTYPE_ALAW /* Compand Using A-Law */
/* SPORTx_RCR2 Masks */
#ifdef _MISRA_RULES
#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
#else
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#endif /* _MISRA_RULES */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
/*SPORTx_STAT Masks */
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
#define RUVF 0x0002 /*RX Underflow Status */
#define ROVF 0x0004 /*RX Overflow Status */
#define TXF 0x0008 /*TX FIFO Full Status */
#define TUVF 0x0010 /*TX Underflow Status */
#define TOVF 0x0020 /*TX Overflow Status */
#define TXHRE 0x0040 /*TX Hold Register Empty */
/*SPORTx_MCMC1 Masks */
#define WOFF 0x000003FF /*Multichannel Window Offset Field */
/* SPORTx_MCMC1 Macros */
#ifdef _MISRA_RULES
#define SET_WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
#else
#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
#endif /* _MISRA_RULES */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /*Multichannel Frame Mode Enable */
#define FSDR 0x0080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0xF000 /*Multichannel Frame Delay */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
/* PPI_CONTROL Masks */
#define PORT_EN 0x0001 /* PPI Port Enable */
arch/blackfin/mach-bf548/boards/cm_bf548.c
-1
View File
@@ -706,7 +706,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),
arch/blackfin/mach-bf548/boards/ezkit.c
-1
View File
@@ -849,7 +849,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
-67
View File
@@ -2221,73 +2221,6 @@
#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
/* Bit masks for SPORTx_TCR1 */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
#define TFSR 0x400 /* Transmit Frame Sync Required Select */
#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
#define TLSBIT 0x10 /* Transmit Bit Order */
#define TDTYPE 0xc /* Data Formatting Type Select */
#define ITCLK 0x2 /* Internal Transmit Clock Select */
#define TSPEN 0x1 /* Transmit Enable */
/* Bit masks for SPORTx_TCR2 */
#define TRFST 0x400 /* Left/Right Order */
#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
#define TXSE 0x100 /* TxSEC Enable */
#define SLEN_T 0x1f /* SPORT Word Length */
/* Bit masks for SPORTx_RCR1 */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
#define LARFS 0x2000 /* Late Receive Frame Sync */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define RFSR 0x400 /* Receive Frame Sync Required Select */
#define IRFS 0x200 /* Internal Receive Frame Sync Select */
#define RLSBIT 0x10 /* Receive Bit Order */
#define RDTYPE 0xc /* Data Formatting Type Select */
#define IRCLK 0x2 /* Internal Receive Clock Select */
#define RSPEN 0x1 /* Receive Enable */
/* Bit masks for SPORTx_RCR2 */
#define RRFST 0x400 /* Left/Right Order */
#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
#define RXSE 0x100 /* RxSEC Enable */
#define SLEN_R 0x1f /* SPORT Word Length */
/* Bit masks for SPORTx_STAT */
#define TXHRE 0x40 /* Transmit Hold Register Empty */
#define TOVF 0x20 /* Sticky Transmit Overflow Status */
#define TUVF 0x10 /* Sticky Transmit Underflow Status */
#define TXF 0x8 /* Transmit FIFO Full Status */
#define ROVF 0x4 /* Sticky Receive Overflow Status */
#define RUVF 0x2 /* Sticky Receive Underflow Status */
#define RXNE 0x1 /* Receive FIFO Not Empty Status */
/* Bit masks for SPORTx_MCMC1 */
#define SP_WSIZE 0xf000 /* Window Size */
#define SP_WOFF 0x3ff /* Windows Offset */
/* Bit masks for SPORTx_MCMC2 */
#define MFD 0xf000 /* Multi channel Frame Delay */
#define FSDR 0x80 /* Frame Sync to Data Relationship */
#define MCMEN 0x10 /* Multi channel Frame Mode Enable */
#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
#define MCCRM 0x3 /* 2X Clock Recovery Mode */
/* Bit masks for SPORTx_CHNL */
#define CUR_CHNL 0x3ff /* Current Channel Indicator */
/* Bit masks for UARTx_LCR */
#if 0
arch/blackfin/mach-bf561/include/mach/defBF561.h
-60
View File
@@ -1007,66 +1007,6 @@
#define IREN_P 0x01
#define UCEN_P 0x00
/* ********** SERIAL PORT MASKS ********************** */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_TCR2 Masks */
#define SLEN 0x001F /*TX Word Length */
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define RULAW 0x0008 /* u-Law enable */
#define RALAW 0x000C /* A-Law enable */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN 0x001F /*RX Word Length */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
/*SPORTx_STAT Masks */
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
#define RUVF 0x0002 /*RX Underflow Status */
#define ROVF 0x0004 /*RX Overflow Status */
#define TXF 0x0008 /*TX FIFO Full Status */
#define TUVF 0x0010 /*TX Underflow Status */
#define TOVF 0x0020 /*TX Overflow Status */
#define TXHRE 0x0040 /*TX Hold Register Empty */
/*SPORTx_MCMC1 Masks */
#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0x0000F000 /*Multichannel Frame Delay */
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
/* PPI_CONTROL Masks */
arch/ia64/hp/sim/simserial.c
+1 -1
View File
@@ -149,7 +149,7 @@ static void receive_chars(struct tty_struct *tty)
ch = ia64_ssc(0, 0, 0, 0,
SSC_GETCHAR);
while (!ch);
handle_sysrq(ch, NULL);
handle_sysrq(ch);
}
#endif
seen_esc = 0;
arch/powerpc/xmon/xmon.c
+2 -3
View File
@@ -2880,15 +2880,14 @@ static void xmon_init(int enable)
}
#ifdef CONFIG_MAGIC_SYSRQ
static void sysrq_handle_xmon(int key, struct tty_struct *tty)
static void sysrq_handle_xmon(int key)
{
/* ensure xmon is enabled */
xmon_init(1);
debugger(get_irq_regs());
}
static struct sysrq_key_op sysrq_xmon_op =
{
static struct sysrq_key_op sysrq_xmon_op = {
.handler = sysrq_handle_xmon,
.help_msg = "Xmon",
.action_msg = "Entering xmon",
arch/sparc/kernel/process_64.c
+1 -1
View File
@@ -303,7 +303,7 @@ void arch_trigger_all_cpu_backtrace(void)
#ifdef CONFIG_MAGIC_SYSRQ
static void sysrq_handle_globreg(int key, struct tty_struct *tty)
static void sysrq_handle_globreg(int key)
{
arch_trigger_all_cpu_backtrace();
}
arch/um/drivers/mconsole_kern.c
+1 -1
View File
@@ -690,7 +690,7 @@ static void with_console(struct mc_request *req, void (*proc)(void *),
static void sysrq_proc(void *arg)
{
char *op = arg;
handle_sysrq(*op, NULL);
handle_sysrq(*op);
}
void mconsole_sysrq(struct mc_request *req)
drivers/ata/Kconfig
+1
View File
@@ -828,6 +828,7 @@ config PATA_SAMSUNG_CF
config PATA_WINBOND_VLB
tristate "Winbond W83759A VLB PATA support (Experimental)"
depends on ISA && EXPERIMENTAL
select PATA_LEGACY
help
Support for the Winbond W83759A controller on Vesa Local Bus
systems.
drivers/ata/Makefile
-1
View File
@@ -89,7 +89,6 @@ obj-$(CONFIG_PATA_QDI) += pata_qdi.o
obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o
obj-$(CONFIG_PATA_WINBOND_VLB) += pata_winbond.o
obj-$(CONFIG_PATA_PXA) += pata_pxa.o
drivers/ata/ahci.c
+11
View File
@@ -60,6 +60,7 @@ enum board_ids {
board_ahci,
board_ahci_ign_iferr,
board_ahci_nosntf,
board_ahci_yes_fbs,
/* board IDs for specific chipsets in alphabetical order */
board_ahci_mcp65,
@@ -132,6 +133,14 @@ static const struct ata_port_info ahci_port_info[] = {
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
[board_ahci_yes_fbs] =
{
AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
/* by chipsets */
[board_ahci_mcp65] =
{
@@ -362,6 +371,8 @@ static const struct pci_device_id ahci_pci_tbl[] = {
/* Marvell */
{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
{ PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
{ PCI_DEVICE(0x1b4b, 0x9123),
.driver_data = board_ahci_yes_fbs }, /* 88se9128 */
/* Promise */
{ PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
drivers/ata/ahci.h
+1
View File
@@ -209,6 +209,7 @@ enum {
link offline */
AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */
AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */
/* ap->flags bits */
drivers/ata/libahci.c
+14 -2
View File
@@ -430,6 +430,12 @@ void ahci_save_initial_config(struct device *dev,
cap &= ~HOST_CAP_SNTF;
}
if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
dev_printk(KERN_INFO, dev,
"controller can do FBS, turning on CAP_FBS\n");
cap |= HOST_CAP_FBS;
}
if (force_port_map && port_map != force_port_map) {
dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
port_map, force_port_map);
@@ -2036,9 +2042,15 @@ static int ahci_port_start(struct ata_port *ap)
u32 cmd = readl(port_mmio + PORT_CMD);
if (cmd & PORT_CMD_FBSCP)
pp->fbs_supported = true;
else
else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
dev_printk(KERN_INFO, dev,
"port %d can do FBS, forcing FBSCP\n",
ap->port_no);
pp->fbs_supported = true;
} else
dev_printk(KERN_WARNING, dev,
"The port is not capable of FBS\n");
"port %d is not capable of FBS\n",
ap->port_no);
}
if (pp->fbs_supported) {
drivers/ata/libata-core.c
+7 -4
View File
@@ -5111,15 +5111,18 @@ void ata_qc_issue(struct ata_queued_cmd *qc)
qc->flags |= ATA_QCFLAG_ACTIVE;
ap->qc_active |= 1 << qc->tag;
/* We guarantee to LLDs that they will have at least one
/*
* We guarantee to LLDs that they will have at least one
* non-zero sg if the command is a data command.
*/
BUG_ON(ata_is_data(prot) && (!qc->sg || !qc->n_elem || !qc->nbytes));
if (WARN_ON_ONCE(ata_is_data(prot) &&
(!qc->sg || !qc->n_elem || !qc->nbytes)))
goto sys_err;
if (ata_is_dma(prot) || (ata_is_pio(prot) &&
(ap->flags & ATA_FLAG_PIO_DMA)))
if (ata_sg_setup(qc))
goto sg_err;
goto sys_err;
/* if device is sleeping, schedule reset and abort the link */
if (unlikely(qc->dev->flags & ATA_DFLAG_SLEEPING)) {
@@ -5136,7 +5139,7 @@ void ata_qc_issue(struct ata_queued_cmd *qc)
goto err;
return;
sg_err:
sys_err:
qc->err_mask |= AC_ERR_SYSTEM;
err:
ata_qc_complete(qc);
drivers/ata/libata-sff.c
-4
View File
@@ -2735,10 +2735,6 @@ unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
/* see ata_dma_blacklisted() */
BUG_ON((ap->flags & ATA_FLAG_PIO_POLLING) &&
qc->tf.protocol == ATAPI_PROT_DMA);
/* defer PIO handling to sff_qc_issue */
if (!ata_is_dma(qc->tf.protocol))
return ata_sff_qc_issue(qc);
drivers/ata/pata_cmd64x.c
-6
View File
@@ -121,14 +121,8 @@ static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 m
if (pair) {
struct ata_timing tp;
ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
if (pair->dma_mode) {
ata_timing_compute(pair, pair->dma_mode,
&tp, T, 0);
ata_timing_merge(&tp, &t, &t, ATA_TIMING_SETUP);
}
}
}
drivers/ata/pata_legacy.c
+13 -2
View File
@@ -44,6 +44,9 @@
* Specific support is included for the ht6560a/ht6560b/opti82c611a/
* opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
*
* Support for the Winbond 83759A when operating in advanced mode.
* Multichip mode is not currently supported.
*
* Use the autospeed and pio_mask options with:
* Appian ADI/2 aka CLPD7220 or AIC25VL01.
* Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
@@ -135,12 +138,18 @@ static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
static int qdi; /* Set to probe QDI controllers */
static int winbond; /* Set to probe Winbond controllers,
give I/O port if non standard */
static int autospeed; /* Chip present which snoops speed changes */
static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
#ifdef PATA_WINBOND_VLB_MODULE
static int winbond = 1; /* Set to probe Winbond controllers,
give I/O port if non standard */
#else
static int winbond; /* Set to probe Winbond controllers,
give I/O port if non standard */
#endif
/**
* legacy_probe_add - Add interface to probe list
* @port: Controller port
@@ -1297,6 +1306,7 @@ MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for legacy ATA");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
MODULE_ALIAS("pata_winbond");
module_param(probe_all, int, 0);
module_param(autospeed, int, 0);
@@ -1305,6 +1315,7 @@ module_param(ht6560b, int, 0);
module_param(opti82c611a, int, 0);
module_param(opti82c46x, int, 0);
module_param(qdi, int, 0);
module_param(winbond, int, 0);
module_param(pio_mask, int, 0);
module_param(iordy_mask, int, 0);
drivers/ata/pata_winbond.c
-282
View File
@@ -1,282 +0,0 @@
/*
* pata_winbond.c - Winbond VLB ATA controllers
* (C) 2006 Red Hat
*
* Support for the Winbond 83759A when operating in advanced mode.
* Multichip mode is not currently supported.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/platform_device.h>
#define DRV_NAME "pata_winbond"
#define DRV_VERSION "0.0.3"
#define NR_HOST 4 /* Two winbond controllers, two channels each */
struct winbond_data {
unsigned long config;
struct platform_device *platform_dev;
};
static struct ata_host *winbond_host[NR_HOST];
static struct winbond_data winbond_data[NR_HOST];
static int nr_winbond_host;
#ifdef MODULE
static int probe_winbond = 1;
#else
static int probe_winbond;
#endif
static DEFINE_SPINLOCK(winbond_lock);
static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
{
unsigned long flags;
spin_lock_irqsave(&winbond_lock, flags);
outb(reg, port + 0x01);
outb(val, port + 0x02);
spin_unlock_irqrestore(&winbond_lock, flags);
}
static u8 winbond_readcfg(unsigned long port, u8 reg)
{
u8 val;
unsigned long flags;
spin_lock_irqsave(&winbond_lock, flags);
outb(reg, port + 0x01);
val = inb(port + 0x02);
spin_unlock_irqrestore(&winbond_lock, flags);
return val;
}
static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
struct ata_timing t;
struct winbond_data *winbond = ap->host->private_data;
int active, recovery;
u8 reg;
int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
reg = winbond_readcfg(winbond->config, 0x81);
/* Get the timing data in cycles */
if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
else
ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
timing = (active << 4) | recovery;
winbond_writecfg(winbond->config, timing, reg);
/* Load the setup timing */
reg = 0x35;
if (adev->class != ATA_DEV_ATA)
reg |= 0x08; /* FIFO off */
if (!ata_pio_need_iordy(adev))
reg |= 0x02; /* IORDY off */
reg |= (clamp_val(t.setup, 0, 3) << 6);
winbond_writecfg(winbond->config, timing + 1, reg);
}
static unsigned int winbond_data_xfer(struct ata_device *dev,
unsigned char *buf, unsigned int buflen, int rw)
{
struct ata_port *ap = dev->link->ap;
int slop = buflen & 3;
if (ata_id_has_dword_io(dev->id)) {
if (rw == READ)
ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
else
iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
if (unlikely(slop)) {
__le32 pad;
if (rw == READ) {
pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
memcpy(buf + buflen - slop, &pad, slop);
} else {
memcpy(&pad, buf + buflen - slop, slop);
iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
}
buflen += 4 - slop;
}
} else
buflen = ata_sff_data_xfer(dev, buf, buflen, rw);
return buflen;
}
static struct scsi_host_template winbond_sht = {
ATA_PIO_SHT(DRV_NAME),
};
static struct ata_port_operations winbond_port_ops = {
.inherits = &ata_sff_port_ops,
.sff_data_xfer = winbond_data_xfer,
.cable_detect = ata_cable_40wire,
.set_piomode = winbond_set_piomode,
};
/**
* winbond_init_one - attach a winbond interface
* @type: Type to display
* @io: I/O port start
* @irq: interrupt line
* @fast: True if on a > 33Mhz VLB
*
* Register a VLB bus IDE interface. Such interfaces are PIO and we
* assume do not support IRQ sharing.
*/
static __init int winbond_init_one(unsigned long port)
{
struct platform_device *pdev;
u8 reg;
int i, rc;
reg = winbond_readcfg(port, 0x81);
reg |= 0x80; /* jumpered mode off */
winbond_writecfg(port, 0x81, reg);
reg = winbond_readcfg(port, 0x83);
reg |= 0xF0; /* local control */
winbond_writecfg(port, 0x83, reg);
reg = winbond_readcfg(port, 0x85);
reg |= 0xF0; /* programmable timing */
winbond_writecfg(port, 0x85, reg);
reg = winbond_readcfg(port, 0x81);
if (!(reg & 0x03)) /* Disabled */
return -ENODEV;
for (i = 0; i < 2 ; i ++) {
unsigned long cmd_port = 0x1F0 - (0x80 * i);
unsigned long ctl_port = cmd_port + 0x206;
struct ata_host *host;
struct ata_port *ap;
void __iomem *cmd_addr, *ctl_addr;
if (!(reg & (1 << i)))
continue;
pdev = platform_device_register_simple(DRV_NAME, nr_winbond_host, NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
rc = -ENOMEM;
host = ata_host_alloc(&pdev->dev, 1);
if (!host)
goto err_unregister;
ap = host->ports[0];
rc = -ENOMEM;
cmd_addr = devm_ioport_map(&pdev->dev, cmd_port, 8);
ctl_addr = devm_ioport_map(&pdev->dev, ctl_port, 1);
if (!cmd_addr || !ctl_addr)
goto err_unregister;
ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", cmd_port, ctl_port);
ap->ops = &winbond_port_ops;
ap->pio_mask = ATA_PIO4;
ap->flags |= ATA_FLAG_SLAVE_POSS;
ap->ioaddr.cmd_addr = cmd_addr;
ap->ioaddr.altstatus_addr = ctl_addr;
ap->ioaddr.ctl_addr = ctl_addr;
ata_sff_std_ports(&ap->ioaddr);
/* hook in a private data structure per channel */
host->private_data = &winbond_data[nr_winbond_host];
winbond_data[nr_winbond_host].config = port;
winbond_data[nr_winbond_host].platform_dev = pdev;
/* activate */
rc = ata_host_activate(host, 14 + i, ata_sff_interrupt, 0,
&winbond_sht);
if (rc)
goto err_unregister;
winbond_host[nr_winbond_host++] = dev_get_drvdata(&pdev->dev);
}
return 0;
err_unregister:
platform_device_unregister(pdev);
return rc;
}
/**
* winbond_init - attach winbond interfaces
*
* Attach winbond IDE interfaces by scanning the ports it may occupy.
*/
static __init int winbond_init(void)
{
static const unsigned long config[2] = { 0x130, 0x1B0 };
int ct = 0;
int i;
if (probe_winbond == 0)
return -ENODEV;
/*
* Check both base addresses
*/
for (i = 0; i < 2; i++) {
if (probe_winbond & (1<<i)) {
int ret = 0;
unsigned long port = config[i];
if (request_region(port, 2, "pata_winbond")) {
ret = winbond_init_one(port);
if (ret <= 0)
release_region(port, 2);
else ct+= ret;
}
}
}
if (ct != 0)
return 0;
return -ENODEV;
}
static __exit void winbond_exit(void)
{
int i;
for (i = 0; i < nr_winbond_host; i++) {
ata_host_detach(winbond_host[i]);
release_region(winbond_data[i].config, 2);
platform_device_unregister(winbond_data[i].platform_dev);
}
}
MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Winbond VL ATA");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
module_init(winbond_init);
module_exit(winbond_exit);
module_param(probe_winbond, int, 0);
drivers/ata/sata_dwc_460ex.c
+1 -1
View File
@@ -1459,7 +1459,7 @@ static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
{
struct scatterlist *sg = qc->sg;
struct ata_port *ap = qc->ap;
u32 dma_chan;
int dma_chan;
struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
int err;
drivers/ata/sata_mv.c
+37 -7
View File
@@ -1898,19 +1898,25 @@ static void mv_bmdma_start(struct ata_queued_cmd *qc)
* LOCKING:
* Inherited from caller.
*/
static void mv_bmdma_stop(struct ata_queued_cmd *qc)
static void mv_bmdma_stop_ap(struct ata_port *ap)
{
struct ata_port *ap = qc->ap;
void __iomem *port_mmio = mv_ap_base(ap);
u32 cmd;
/* clear start/stop bit */
cmd = readl(port_mmio + BMDMA_CMD);
cmd &= ~ATA_DMA_START;
writelfl(cmd, port_mmio + BMDMA_CMD);
if (cmd & ATA_DMA_START) {
cmd &= ~ATA_DMA_START;
writelfl(cmd, port_mmio + BMDMA_CMD);
/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
ata_sff_dma_pause(ap);
/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
ata_sff_dma_pause(ap);
}
}
static void mv_bmdma_stop(struct ata_queued_cmd *qc)
{
mv_bmdma_stop_ap(qc->ap);
}
/**
@@ -1934,8 +1940,21 @@ static u8 mv_bmdma_status(struct ata_port *ap)
reg = readl(port_mmio + BMDMA_STATUS);
if (reg & ATA_DMA_ACTIVE)
status = ATA_DMA_ACTIVE;
else
else if (reg & ATA_DMA_ERR)
status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
else {
/*
* Just because DMA_ACTIVE is 0 (DMA completed),
* this does _not_ mean the device is "done".
* So we should not yet be signalling ATA_DMA_INTR
* in some cases. Eg. DSM/TRIM, and perhaps others.
*/
mv_bmdma_stop_ap(ap);
if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
status = 0;
else
status = ATA_DMA_INTR;
}
return status;
}
@@ -1995,6 +2014,9 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
switch (tf->protocol) {
case ATA_PROT_DMA:
if (tf->command == ATA_CMD_DSM)
return;
/* fall-thru */
case ATA_PROT_NCQ:
break; /* continue below */
case ATA_PROT_PIO:
@@ -2094,6 +2116,8 @@ static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
if ((tf->protocol != ATA_PROT_DMA) &&
(tf->protocol != ATA_PROT_NCQ))
return;
if (tf->command == ATA_CMD_DSM)
return; /* use bmdma for this */
/* Fill in Gen IIE command request block */
if (!(tf->flags & ATA_TFLAG_WRITE))
@@ -2289,6 +2313,12 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
switch (qc->tf.protocol) {
case ATA_PROT_DMA:
if (qc->tf.command == ATA_CMD_DSM) {
if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
return AC_ERR_OTHER;
break; /* use bmdma for this */
}
/* fall thru */
case ATA_PROT_NCQ:
mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
drivers/char/hangcheck-timer.c
+1 -1
View File
@@ -159,7 +159,7 @@ static void hangcheck_fire(unsigned long data)
if (hangcheck_dump_tasks) {
printk(KERN_CRIT "Hangcheck: Task state:\n");
#ifdef CONFIG_MAGIC_SYSRQ
handle_sysrq('t', NULL);
handle_sysrq('t');
#endif /* CONFIG_MAGIC_SYSRQ */
}
if (hangcheck_reboot) {
drivers/char/hvc_console.c
+1 -1
View File
@@ -651,7 +651,7 @@ int hvc_poll(struct hvc_struct *hp)
if (sysrq_pressed)
continue;
} else if (sysrq_pressed) {
handle_sysrq(buf[i], tty);
handle_sysrq(buf[i]);
sysrq_pressed = 0;
continue;
}
drivers/char/hvsi.c
+1 -1
View File
@@ -403,7 +403,7 @@ static void hvsi_insert_chars(struct hvsi_struct *hp, const char *buf, int len)
hp->sysrq = 1;
continue;
} else if (hp->sysrq) {
handle_sysrq(c, hp->tty);
handle_sysrq(c);
hp->sysrq = 0;
continue;
}
drivers/char/sysrq.c
+26 -27
View File
@@ -18,7 +18,6 @@
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/fs.h>
#include <linux/tty.h>
#include <linux/mount.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
@@ -76,7 +75,7 @@ static int __init sysrq_always_enabled_setup(char *str)
__setup("sysrq_always_enabled", sysrq_always_enabled_setup);
static void sysrq_handle_loglevel(int key, struct tty_struct *tty)
static void sysrq_handle_loglevel(int key)
{
int i;
@@ -93,7 +92,7 @@ static struct sysrq_key_op sysrq_loglevel_op = {
};
#ifdef CONFIG_VT
static void sysrq_handle_SAK(int key, struct tty_struct *tty)
static void sysrq_handle_SAK(int key)
{
struct work_struct *SAK_work = &vc_cons[fg_console].SAK_work;
schedule_work(SAK_work);
@@ -109,7 +108,7 @@ static struct sysrq_key_op sysrq_SAK_op = {
#endif
#ifdef CONFIG_VT
static void sysrq_handle_unraw(int key, struct tty_struct *tty)
static void sysrq_handle_unraw(int key)
{
struct kbd_struct *kbd = &kbd_table[fg_console];
@@ -126,7 +125,7 @@ static struct sysrq_key_op sysrq_unraw_op = {
#define sysrq_unraw_op (*(struct sysrq_key_op *)NULL)
#endif /* CONFIG_VT */
static void sysrq_handle_crash(int key, struct tty_struct *tty)
static void sysrq_handle_crash(int key)
{
char *killer = NULL;
@@ -141,7 +140,7 @@ static struct sysrq_key_op sysrq_crash_op = {
.enable_mask = SYSRQ_ENABLE_DUMP,
};
static void sysrq_handle_reboot(int key, struct tty_struct *tty)
static void sysrq_handle_reboot(int key)
{
lockdep_off();
local_irq_enable();
@@ -154,7 +153,7 @@ static struct sysrq_key_op sysrq_reboot_op = {
.enable_mask = SYSRQ_ENABLE_BOOT,
};
static void sysrq_handle_sync(int key, struct tty_struct *tty)
static void sysrq_handle_sync(int key)
{
emergency_sync();
}
@@ -165,7 +164,7 @@ static struct sysrq_key_op sysrq_sync_op = {
.enable_mask = SYSRQ_ENABLE_SYNC,
};
static void sysrq_handle_show_timers(int key, struct tty_struct *tty)
static void sysrq_handle_show_timers(int key)
{
sysrq_timer_list_show();
}
@@ -176,7 +175,7 @@ static struct sysrq_key_op sysrq_show_timers_op = {
.action_msg = "Show clockevent devices & pending hrtimers (no others)",
};
static void sysrq_handle_mountro(int key, struct tty_struct *tty)
static void sysrq_handle_mountro(int key)
{
emergency_remount();
}
@@ -188,7 +187,7 @@ static struct sysrq_key_op sysrq_mountro_op = {
};
#ifdef CONFIG_LOCKDEP
static void sysrq_handle_showlocks(int key, struct tty_struct *tty)
static void sysrq_handle_showlocks(int key)
{
debug_show_all_locks();
}
@@ -226,7 +225,7 @@ static void sysrq_showregs_othercpus(struct work_struct *dummy)
static DECLARE_WORK(sysrq_showallcpus, sysrq_showregs_othercpus);
static void sysrq_handle_showallcpus(int key, struct tty_struct *tty)
static void sysrq_handle_showallcpus(int key)
{
/*
* Fall back to the workqueue based printing if the
@@ -252,7 +251,7 @@ static struct sysrq_key_op sysrq_showallcpus_op = {
};
#endif
static void sysrq_handle_showregs(int key, struct tty_struct *tty)
static void sysrq_handle_showregs(int key)
{
struct pt_regs *regs = get_irq_regs();
if (regs)
@@ -266,7 +265,7 @@ static struct sysrq_key_op sysrq_showregs_op = {
.enable_mask = SYSRQ_ENABLE_DUMP,
};
static void sysrq_handle_showstate(int key, struct tty_struct *tty)
static void sysrq_handle_showstate(int key)
{
show_state();
}
@@ -277,7 +276,7 @@ static struct sysrq_key_op sysrq_showstate_op = {
.enable_mask = SYSRQ_ENABLE_DUMP,
};
static void sysrq_handle_showstate_blocked(int key, struct tty_struct *tty)
static void sysrq_handle_showstate_blocked(int key)
{
show_state_filter(TASK_UNINTERRUPTIBLE);
}
@@ -291,7 +290,7 @@ static struct sysrq_key_op sysrq_showstate_blocked_op = {
#ifdef CONFIG_TRACING
#include <linux/ftrace.h>
static void sysrq_ftrace_dump(int key, struct tty_struct *tty)
static void sysrq_ftrace_dump(int key)
{
ftrace_dump(DUMP_ALL);
}
@@ -305,7 +304,7 @@ static struct sysrq_key_op sysrq_ftrace_dump_op = {
#define sysrq_ftrace_dump_op (*(struct sysrq_key_op *)NULL)
#endif
static void sysrq_handle_showmem(int key, struct tty_struct *tty)
static void sysrq_handle_showmem(int key)
{
show_mem();
}
@@ -330,7 +329,7 @@ static void send_sig_all(int sig)
}
}
static void sysrq_handle_term(int key, struct tty_struct *tty)
static void sysrq_handle_term(int key)
{
send_sig_all(SIGTERM);
console_loglevel = 8;
@@ -349,7 +348,7 @@ static void moom_callback(struct work_struct *ignored)
static DECLARE_WORK(moom_work, moom_callback);
static void sysrq_handle_moom(int key, struct tty_struct *tty)
static void sysrq_handle_moom(int key)
{
schedule_work(&moom_work);
}
@@ -361,7 +360,7 @@ static struct sysrq_key_op sysrq_moom_op = {
};
#ifdef CONFIG_BLOCK
static void sysrq_handle_thaw(int key, struct tty_struct *tty)
static void sysrq_handle_thaw(int key)
{
emergency_thaw_all();
}
@@ -373,7 +372,7 @@ static struct sysrq_key_op sysrq_thaw_op = {
};
#endif
static void sysrq_handle_kill(int key, struct tty_struct *tty)
static void sysrq_handle_kill(int key)
{
send_sig_all(SIGKILL);
console_loglevel = 8;
@@ -385,7 +384,7 @@ static struct sysrq_key_op sysrq_kill_op = {
.enable_mask = SYSRQ_ENABLE_SIGNAL,
};
static void sysrq_handle_unrt(int key, struct tty_struct *tty)
static void sysrq_handle_unrt(int key)
{
normalize_rt_tasks();
}
@@ -493,7 +492,7 @@ static void __sysrq_put_key_op(int key, struct sysrq_key_op *op_p)
sysrq_key_table[i] = op_p;
}
void __handle_sysrq(int key, struct tty_struct *tty, int check_mask)
void __handle_sysrq(int key, bool check_mask)
{
struct sysrq_key_op *op_p;
int orig_log_level;
@@ -520,7 +519,7 @@ void __handle_sysrq(int key, struct tty_struct *tty, int check_mask)
if (!check_mask || sysrq_on_mask(op_p->enable_mask)) {
printk("%s\n", op_p->action_msg);
console_loglevel = orig_log_level;
op_p->handler(key, tty);
op_p->handler(key);
} else {
printk("This sysrq operation is disabled.\n");
}
@@ -545,10 +544,10 @@ void __handle_sysrq(int key, struct tty_struct *tty, int check_mask)
spin_unlock_irqrestore(&sysrq_key_table_lock, flags);
}
void handle_sysrq(int key, struct tty_struct *tty)
void handle_sysrq(int key)
{
if (sysrq_on())
__handle_sysrq(key, tty, 1);
__handle_sysrq(key, true);
}
EXPORT_SYMBOL(handle_sysrq);
@@ -597,7 +596,7 @@ static bool sysrq_filter(struct input_handle *handle, unsigned int type,
default:
if (sysrq_down && value && value != 2)
__handle_sysrq(sysrq_xlate[code], NULL, 1);
__handle_sysrq(sysrq_xlate[code], true);
break;
}
@@ -765,7 +764,7 @@ static ssize_t write_sysrq_trigger(struct file *file, const char __user *buf,
if (get_user(c, buf))
return -EFAULT;
__handle_sysrq(c, NULL, 0);
__handle_sysrq(c, false);
}
return count;
drivers/edac/amd64_edac.c
-10
View File
@@ -2071,16 +2071,6 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
amd64_handle_ce(mci, info);
else if (ecc_type == 1)
amd64_handle_ue(mci, info);
/*
* If main error is CE then overflow must be CE. If main error is UE
* then overflow is unknown. We'll call the overflow a CE - if
* panic_on_ue is set then we're already panic'ed and won't arrive
* here. Else, then apparently someone doesn't think that UE's are
* catastrophic.
*/
if (info->nbsh & K8_NBSH_OVERFLOW)
edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR " Error Overflow");
}
void amd64_decode_bus_error(int node_id, struct err_regs *regs)
drivers/edac/edac_mce_amd.c
+10 -7
View File
@@ -365,11 +365,10 @@ static int amd_decode_mce(struct notifier_block *nb, unsigned long val,
pr_emerg("MC%d_STATUS: ", m->bank);
pr_cont("%sorrected error, report: %s, MiscV: %svalid, "
pr_cont("%sorrected error, other errors lost: %s, "
"CPU context corrupt: %s",
((m->status & MCI_STATUS_UC) ? "Unc" : "C"),
((m->status & MCI_STATUS_EN) ? "yes" : "no"),
((m->status & MCI_STATUS_MISCV) ? "" : "in"),
((m->status & MCI_STATUS_OVER) ? "yes" : "no"),
((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
/* do the two bits[14:13] together */
@@ -426,11 +425,15 @@ static struct notifier_block amd_mce_dec_nb = {
static int __init mce_amd_init(void)
{
/*
* We can decode MCEs for Opteron and later CPUs:
* We can decode MCEs for K8, F10h and F11h CPUs:
*/
if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
(boot_cpu_data.x86 >= 0xf))
atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
return 0;
if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11)
return 0;
atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);
return 0;
}
drivers/gpu/drm/drm_fb_helper.c
+1 -1
View File
@@ -370,7 +370,7 @@ static void drm_fb_helper_restore_work_fn(struct work_struct *ignored)
}
static DECLARE_WORK(drm_fb_helper_restore_work, drm_fb_helper_restore_work_fn);
static void drm_fb_helper_sysrq(int dummy1, struct tty_struct *dummy3)
static void drm_fb_helper_sysrq(int dummy1)
{
schedule_work(&drm_fb_helper_restore_work);
}
drivers/gpu/drm/drm_fops.c
+1
View File
@@ -41,6 +41,7 @@
/* from BKL pushdown: note that nothing else serializes idr_find() */
DEFINE_MUTEX(drm_global_mutex);
EXPORT_SYMBOL(drm_global_mutex);
static int drm_open_helper(struct inode *inode, struct file *filp,
struct drm_device * dev);
drivers/gpu/drm/drm_lock.c
+2
View File
@@ -92,7 +92,9 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
}
/* Contention */
mutex_unlock(&drm_global_mutex);
schedule();
mutex_lock(&drm_global_mutex);
if (signal_pending(current)) {
ret = -EINTR;
break;
drivers/gpu/drm/drm_mm.c
+14 -10
View File
@@ -285,21 +285,21 @@ void drm_mm_put_block(struct drm_mm_node *cur)
EXPORT_SYMBOL(drm_mm_put_block);
static int check_free_mm_node(struct drm_mm_node *entry, unsigned long size,
unsigned alignment)
static int check_free_hole(unsigned long start, unsigned long end,
unsigned long size, unsigned alignment)
{
unsigned wasted = 0;
if (entry->size < size)
if (end - start < size)
return 0;
if (alignment) {
register unsigned tmp = entry->start % alignment;
unsigned tmp = start % alignment;
if (tmp)
wasted = alignment - tmp;
}
if (entry->size >= size + wasted) {
if (end >= start + size + wasted) {
return 1;
}
@@ -320,7 +320,8 @@ struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm,
best_size = ~0UL;
list_for_each_entry(entry, &mm->free_stack, free_stack) {
if (!check_free_mm_node(entry, size, alignment))
if (!check_free_hole(entry->start, entry->start + entry->size,
size, alignment))
continue;
if (!best_match)
@@ -353,10 +354,12 @@ struct drm_mm_node *drm_mm_search_free_in_range(const struct drm_mm *mm,
best_size = ~0UL;
list_for_each_entry(entry, &mm->free_stack, free_stack) {
if (entry->start > end || (entry->start+entry->size) < start)
continue;
unsigned long adj_start = entry->start < start ?
start : entry->start;
unsigned long adj_end = entry->start + entry->size > end ?
end : entry->start + entry->size;
if (!check_free_mm_node(entry, size, alignment))
if (!check_free_hole(adj_start, adj_end, size, alignment))
continue;
if (!best_match)
@@ -449,7 +452,8 @@ int drm_mm_scan_add_block(struct drm_mm_node *node)
node->free_stack.prev = prev_free;
node->free_stack.next = next_free;
if (check_free_mm_node(node, mm->scan_size, mm->scan_alignment)) {
if (check_free_hole(node->start, node->start + node->size,
mm->scan_size, mm->scan_alignment)) {
mm->scan_hit_start = node->start;
mm->scan_hit_size = node->size;
drivers/gpu/drm/drm_modes.c
+4 -1
View File
@@ -251,7 +251,10 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK;
/* Fill in HSync values */
drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2;
drm_mode->hsync_start = drm_mode->hsync_end = CVT_RB_H_SYNC;
drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC;
/* Fill in VSync values */
drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH;
drm_mode->vsync_end = drm_mode->vsync_start + vsync;
}
/* 15/13. Find pixel clock frequency (kHz for xf86) */
drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod;
drivers/gpu/drm/nouveau/nouveau_bios.c
+15 -49
View File
@@ -3869,27 +3869,10 @@ static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entr
}
#ifdef __powerpc__
/* Powerbook specific quirks */
if ((dev->pci_device & 0xffff) == 0x0179 ||
(dev->pci_device & 0xffff) == 0x0189 ||
(dev->pci_device & 0xffff) == 0x0329) {
if (script == LVDS_RESET) {
nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
} else if (script == LVDS_PANEL_ON) {
bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
| (1 << 31));
bios_wr32(bios, NV_PCRTC_GPIO_EXT,
bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
} else if (script == LVDS_PANEL_OFF) {
bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
& ~(1 << 31));
bios_wr32(bios, NV_PCRTC_GPIO_EXT,
bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
}
}
if (script == LVDS_RESET &&
(dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
dev->pci_device == 0x0329))
nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
#endif
return 0;
@@ -4381,11 +4364,8 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
*
* For the moment, a quirk will do :)
*/
if ((dev->pdev->device == 0x01d7) &&
(dev->pdev->subsystem_vendor == 0x1028) &&
(dev->pdev->subsystem_device == 0x01c2)) {
if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
bios->fp.duallink_transition_clk = 80000;
}
/* set dual_link flag for EDID case */
if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
@@ -5814,9 +5794,7 @@ parse_dcb_gpio_table(struct nvbios *bios)
*/
/* Apple iMac G4 NV18 */
if (dev->pdev->device == 0x0189 &&
dev->pdev->subsystem_vendor == 0x10de &&
dev->pdev->subsystem_device == 0x0010) {
if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) {
struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
gpio->tag = DCB_GPIO_TVDAC0;
@@ -5898,9 +5876,7 @@ apply_dcb_connector_quirks(struct nvbios *bios, int idx)
struct drm_device *dev = bios->dev;
/* Gigabyte NX85T */
if ((dev->pdev->device == 0x0421) &&
(dev->pdev->subsystem_vendor == 0x1458) &&
(dev->pdev->subsystem_device == 0x344c)) {
if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) {
if (cte->type == DCB_CONNECTOR_HDMI_1)
cte->type = DCB_CONNECTOR_DVI_I;
}
@@ -6153,7 +6129,7 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
break;
case 0xe:
case OUTPUT_EOL:
/* weird g80 mobile type that "nv" treats as a terminator */
dcb->entries--;
return false;
@@ -6190,23 +6166,15 @@ parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
entry->type = OUTPUT_TV;
break;
case 2:
case 4:
if (conn & 0x10)
entry->type = OUTPUT_LVDS;
else
entry->type = OUTPUT_TMDS;
break;
case 3:
entry->type = OUTPUT_LVDS;
break;
case 4:
switch ((conn & 0x000000f0) >> 4) {
case 0:
entry->type = OUTPUT_TMDS;
break;
case 1:
entry->type = OUTPUT_LVDS;
break;
default:
NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
(conn & 0x000000f0) >> 4);
return false;
}
break;
default:
NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
return false;
@@ -6321,9 +6289,7 @@ apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
* nasty problems until this is sorted (assuming it's not a
* VBIOS bug).
*/
if ((dev->pdev->device == 0x040d) &&
(dev->pdev->subsystem_vendor == 0x1028) &&
(dev->pdev->subsystem_device == 0x019b)) {
if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
if (*conn == 0x02026312 && *conf == 0x00000020)
return false;
}
drivers/gpu/drm/nouveau/nouveau_bios.h
+1
View File
@@ -95,6 +95,7 @@ enum dcb_type {
OUTPUT_TMDS = 2,
OUTPUT_LVDS = 3,
OUTPUT_DP = 6,
OUTPUT_EOL = 14, /* DCB 4.0+, appears to be end-of-list */
OUTPUT_ANY = -1
};
drivers/gpu/drm/nouveau/nouveau_drv.h
+9
View File
@@ -1389,6 +1389,15 @@ nv_two_reg_pll(struct drm_device *dev)
return false;
}
static inline bool
nv_match_device(struct drm_device *dev, unsigned device,
unsigned sub_vendor, unsigned sub_device)
{
return dev->pdev->device == device &&
dev->pdev->subsystem_vendor == sub_vendor &&
dev->pdev->subsystem_device == sub_device;
}
#define NV_SW 0x0000506e
#define NV_SW_DMA_SEMAPHORE 0x00000060
#define NV_SW_SEMAPHORE_OFFSET 0x00000064
drivers/gpu/drm/nouveau/nouveau_gem.c
+4 -2
View File
@@ -337,7 +337,9 @@ retry:
return -EINVAL;
}
mutex_unlock(&drm_global_mutex);
ret = ttm_bo_wait_cpu(&nvbo->bo, false);
mutex_lock(&drm_global_mutex);
if (ret) {
NV_ERROR(dev, "fail wait_cpu\n");
return ret;
@@ -663,7 +665,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
push[i].length);
}
} else
if (dev_priv->card_type >= NV_20) {
if (dev_priv->chipset >= 0x25) {
ret = RING_SPACE(chan, req->nr_push * 2);
if (ret) {
NV_ERROR(dev, "cal_space: %d\n", ret);
@@ -738,7 +740,7 @@ out_next:
req->suffix0 = 0x00000000;
req->suffix1 = 0x00000000;
} else
if (dev_priv->card_type >= NV_20) {
if (dev_priv->chipset >= 0x25) {
req->suffix0 = 0x00020000;
req->suffix1 = 0x00000000;
} else {
drivers/gpu/drm/nouveau/nv04_dfp.c
+28 -3
View File
@@ -444,6 +444,7 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct dcb_entry *dcbe = nv_encoder->dcb;
int head = nouveau_crtc(encoder->crtc)->index;
struct drm_encoder *slave_encoder;
if (dcbe->type == OUTPUT_TMDS)
run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
@@ -462,9 +463,10 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
/* Init external transmitters */
if (get_tmds_slave(encoder))
get_slave_funcs(get_tmds_slave(encoder))->mode_set(
encoder, &nv_encoder->mode, &nv_encoder->mode);
slave_encoder = get_tmds_slave(encoder);
if (slave_encoder)
get_slave_funcs(slave_encoder)->mode_set(
slave_encoder, &nv_encoder->mode, &nv_encoder->mode);
helper->dpms(encoder, DRM_MODE_DPMS_ON);
@@ -473,6 +475,27 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
}
static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
{
#ifdef __powerpc__
struct drm_device *dev = encoder->dev;
/* BIOS scripts usually take care of the backlight, thanks
* Apple for your consistency.
*/
if (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
dev->pci_device == 0x0329) {
if (mode == DRM_MODE_DPMS_ON) {
nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 0, 1 << 31);
nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 1);
} else {
nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 0);
}
}
#endif
}
static inline bool is_powersaving_dpms(int mode)
{
return (mode != DRM_MODE_DPMS_ON);
@@ -520,6 +543,7 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
LVDS_PANEL_OFF, 0);
}
nv04_dfp_update_backlight(encoder, mode);
nv04_dfp_update_fp_control(encoder, mode);
if (mode == DRM_MODE_DPMS_ON)
@@ -543,6 +567,7 @@ static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n",
mode, nv_encoder->dcb->index);
nv04_dfp_update_backlight(encoder, mode);
nv04_dfp_update_fp_control(encoder, mode);
}
drivers/gpu/drm/nouveau/nv17_tv.c
+3 -7
View File
@@ -121,18 +121,14 @@ static bool
get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
{
/* Zotac FX5200 */
if (dev->pdev->device == 0x0322 &&
dev->pdev->subsystem_vendor == 0x19da &&
(dev->pdev->subsystem_device == 0x1035 ||
dev->pdev->subsystem_device == 0x2035)) {
if (nv_match_device(dev, 0x0322, 0x19da, 0x1035) ||
nv_match_device(dev, 0x0322, 0x19da, 0x2035)) {
*pin_mask = 0xc;
return false;
}
/* MSI nForce2 IGP */
if (dev->pdev->device == 0x01f0 &&
dev->pdev->subsystem_vendor == 0x1462 &&
dev->pdev->subsystem_device == 0x5710) {
if (nv_match_device(dev, 0x01f0, 0x1462, 0x5710)) {
*pin_mask = 0xc;
return false;
}
drivers/gpu/drm/radeon/radeon_connectors.c
+1
View File
@@ -999,6 +999,7 @@ static enum drm_connector_status radeon_dp_detect(struct drm_connector *connecto
}
}
radeon_connector_update_scratch_regs(connector, ret);
return ret;
}
drivers/gpu/drm/radeon/radeon_pm.c
-2
View File
@@ -637,8 +637,6 @@ void radeon_pm_fini(struct radeon_device *rdev)
}
radeon_hwmon_fini(rdev);
if (rdev->pm.i2c_bus)
radeon_i2c_destroy(rdev->pm.i2c_bus);
}
void radeon_pm_compute_clocks(struct radeon_device *rdev)
drivers/input/keyboard/hil_kbd.c
+6 -6
View File
@@ -232,13 +232,13 @@ static void hil_dev_handle_ptr_events(struct hil_dev *ptr)
if (absdev) {
val = lo + (hi << 8);
#ifdef TABLET_AUTOADJUST
if (val < input_abs_min(dev, ABS_X + i))
if (val < input_abs_get_min(dev, ABS_X + i))
input_abs_set_min(dev, ABS_X + i, val);
if (val > input_abs_max(dev, ABS_X + i))
if (val > input_abs_get_max(dev, ABS_X + i))
input_abs_set_max(dev, ABS_X + i, val);
#endif
if (i % 3)
val = input_abs_max(dev, ABS_X + i) - val;
val = input_abs_get_max(dev, ABS_X + i) - val;
input_report_abs(dev, ABS_X + i, val);
} else {
val = (int) (((int8_t) lo) | ((int8_t) hi << 8));
@@ -388,11 +388,11 @@ static void hil_dev_pointer_setup(struct hil_dev *ptr)
#ifdef TABLET_AUTOADJUST
for (i = 0; i < ABS_MAX; i++) {
int diff = input_abs_max(input_dev, ABS_X + i) / 10;
int diff = input_abs_get_max(input_dev, ABS_X + i) / 10;
input_abs_set_min(input_dev, ABS_X + i,
input_abs_min(input_dev, ABS_X + i) + diff)
input_abs_get_min(input_dev, ABS_X + i) + diff);
input_abs_set_max(input_dev, ABS_X + i,
input_abs_max(input_dev, ABS_X + i) - diff)
input_abs_get_max(input_dev, ABS_X + i) - diff);
}
#endif
drivers/input/keyboard/pxa27x_keypad.c
-2
View File
@@ -567,8 +567,6 @@ static int __devexit pxa27x_keypad_remove(struct platform_device *pdev)
clk_put(keypad->clk);
input_unregister_device(keypad->input_dev);
input_free_device(keypad->input_dev);
iounmap(keypad->mmio_base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
drivers/input/misc/uinput.c
+2
View File
@@ -811,6 +811,8 @@ static struct miscdevice uinput_misc = {
.minor = UINPUT_MINOR,
.name = UINPUT_NAME,
};
MODULE_ALIAS_MISCDEV(UINPUT_MINOR);
MODULE_ALIAS("devname:" UINPUT_NAME);
static int __init uinput_init(void)
{
drivers/input/mousedev.c
+4 -4
View File
@@ -138,8 +138,8 @@ static void mousedev_touchpad_event(struct input_dev *dev,
fx(0) = value;
if (mousedev->touch && mousedev->pkt_count >= 2) {
size = input_abs_get_min(dev, ABS_X) -
input_abs_get_max(dev, ABS_X);
size = input_abs_get_max(dev, ABS_X) -
input_abs_get_min(dev, ABS_X);
if (size == 0)
size = 256 * 2;
@@ -155,8 +155,8 @@ static void mousedev_touchpad_event(struct input_dev *dev,
fy(0) = value;
if (mousedev->touch && mousedev->pkt_count >= 2) {
/* use X size for ABS_Y to keep the same scale */
size = input_abs_get_min(dev, ABS_X) -
input_abs_get_max(dev, ABS_X);
size = input_abs_get_max(dev, ABS_X) -
input_abs_get_min(dev, ABS_X);
if (size == 0)
size = 256 * 2;
drivers/net/3c59x.c
+14 -1
View File
@@ -633,7 +633,8 @@ struct vortex_private {
open:1,
medialock:1,
must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
large_frames:1; /* accept large frames */
large_frames:1, /* accept large frames */
handling_irq:1; /* private in_irq indicator */
int drv_flags;
u16 status_enable;
u16 intr_enable;
@@ -2133,6 +2134,15 @@ boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
dev->name, vp->cur_tx);
}
/*
* We can't allow a recursion from our interrupt handler back into the
* tx routine, as they take the same spin lock, and that causes
* deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
* a bit
*/
if (vp->handling_irq)
return NETDEV_TX_BUSY;
if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
if (vortex_debug > 0)
pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
@@ -2335,11 +2345,13 @@ boomerang_interrupt(int irq, void *dev_id)
ioaddr = vp->ioaddr;
/*
* It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
* and boomerang_start_xmit
*/
spin_lock(&vp->lock);
vp->handling_irq = 1;
status = ioread16(ioaddr + EL3_STATUS);
@@ -2447,6 +2459,7 @@ boomerang_interrupt(int irq, void *dev_id)
pr_debug("%s: exiting interrupt, status %4.4x.\n",
dev->name, status);
handler_exit:
vp->handling_irq = 0;
spin_unlock(&vp->lock);
return IRQ_HANDLED;
}
drivers/net/caif/Kconfig
+1 -1
View File
@@ -15,7 +15,7 @@ config CAIF_TTY
config CAIF_SPI_SLAVE
tristate "CAIF SPI transport driver for slave interface"
depends on CAIF
depends on CAIF && HAS_DMA
default n
---help---
The CAIF Link layer SPI Protocol driver for Slave SPI interface.
drivers/net/ibm_newemac/debug.c
+1 -1
View File
@@ -238,7 +238,7 @@ void emac_dbg_dump_all(void)
}
#if defined(CONFIG_MAGIC_SYSRQ)
static void emac_sysrq_handler(int key, struct tty_struct *tty)
static void emac_sysrq_handler(int key)
{
emac_dbg_dump_all();
}
drivers/net/netxen/netxen_nic_main.c
+8 -1
View File
@@ -2131,9 +2131,16 @@ static int netxen_nic_poll(struct napi_struct *napi, int budget)
#ifdef CONFIG_NET_POLL_CONTROLLER
static void netxen_nic_poll_controller(struct net_device *netdev)
{
int ring;
struct nx_host_sds_ring *sds_ring;
struct netxen_adapter *adapter = netdev_priv(netdev);
struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
disable_irq(adapter->irq);
netxen_intr(adapter->irq, adapter);
for (ring = 0; ring < adapter->max_sds_rings; ring++) {
sds_ring = &recv_ctx->sds_rings[ring];
netxen_intr(adapter->irq, sds_ring);
}
enable_irq(adapter->irq);
}
#endif
drivers/net/phy/phy_device.c
+2
View File
@@ -466,6 +466,8 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
phydev->interface = interface;
phydev->state = PHY_READY;
/* Do initial configuration here, now that
* we have certain key parameters
* (dev_flags and interface) */
drivers/net/pxa168_eth.c
+28 -30
View File
@@ -654,15 +654,15 @@ static void eth_port_start(struct net_device *dev)
/* Assignment of Tx CTRP of given queue */
tx_curr_desc = pep->tx_curr_desc_q;
wrl(pep, ETH_C_TX_DESC_1,
(u32) ((struct tx_desc *)pep->tx_desc_dma + tx_curr_desc));
(u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc)));
/* Assignment of Rx CRDP of given queue */
rx_curr_desc = pep->rx_curr_desc_q;
wrl(pep, ETH_C_RX_DESC_0,
(u32) ((struct rx_desc *)pep->rx_desc_dma + rx_curr_desc));
(u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
wrl(pep, ETH_F_RX_DESC_0,
(u32) ((struct rx_desc *)pep->rx_desc_dma + rx_curr_desc));
(u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
/* Clear all interrupts */
wrl(pep, INT_CAUSE, 0);
@@ -1350,7 +1350,7 @@ static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr,
{
struct pxa168_eth_private *pep = netdev_priv(dev);
if (pep->phy != NULL)
return phy_mii_ioctl(pep->phy, if_mii(ifr), cmd);
return phy_mii_ioctl(pep->phy, ifr, cmd);
return -EOPNOTSUPP;
}
@@ -1414,10 +1414,8 @@ static int ethernet_phy_setup(struct net_device *dev)
{
struct pxa168_eth_private *pep = netdev_priv(dev);
if (pep->pd != NULL) {
if (pep->pd->init)
pep->pd->init();
}
if (pep->pd->init)
pep->pd->init();
pep->phy = phy_scan(pep, pep->pd->phy_addr & 0x1f);
if (pep->phy != NULL)
phy_init(pep, pep->pd->speed, pep->pd->duplex);
@@ -1499,7 +1497,7 @@ static int pxa168_eth_probe(struct platform_device *pdev)
dev = alloc_etherdev(sizeof(struct pxa168_eth_private));
if (!dev) {
err = -ENOMEM;
goto out;
goto err_clk;
}
platform_set_drvdata(pdev, dev);
@@ -1509,12 +1507,12 @@ static int pxa168_eth_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
err = -ENODEV;
goto out;
goto err_netdev;
}
pep->base = ioremap(res->start, res->end - res->start + 1);
if (pep->base == NULL) {
err = -ENOMEM;
goto out;
goto err_netdev;
}
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
BUG_ON(!res);
@@ -1551,7 +1549,7 @@ static int pxa168_eth_probe(struct platform_device *pdev)
pep->smi_bus = mdiobus_alloc();
if (pep->smi_bus == NULL) {
err = -ENOMEM;
goto out;
goto err_base;
}
pep->smi_bus->priv = pep;
pep->smi_bus->name = "pxa168_eth smi";
@@ -1560,31 +1558,31 @@ static int pxa168_eth_probe(struct platform_device *pdev)
snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
pep->smi_bus->parent = &pdev->dev;
pep->smi_bus->phy_mask = 0xffffffff;
if (mdiobus_register(pep->smi_bus) < 0) {
err = -ENOMEM;
goto out;
}
err = mdiobus_register(pep->smi_bus);
if (err)
goto err_free_mdio;
pxa168_init_hw(pep);
err = ethernet_phy_setup(dev);
if (err)
goto out;
goto err_mdiobus;
SET_NETDEV_DEV(dev, &pdev->dev);
err = register_netdev(dev);
if (err)
goto out;
goto err_mdiobus;
return 0;
out:
if (pep->clk) {
clk_disable(pep->clk);
clk_put(pep->clk);
pep->clk = NULL;
}
if (pep->base) {
iounmap(pep->base);
pep->base = NULL;
}
if (dev)
free_netdev(dev);
err_mdiobus:
mdiobus_unregister(pep->smi_bus);
err_free_mdio:
mdiobus_free(pep->smi_bus);
err_base:
iounmap(pep->base);
err_netdev:
free_netdev(dev);
err_clk:
clk_disable(clk);
clk_put(clk);
return err;
}
drivers/net/qlcnic/qlcnic_main.c
+8 -1
View File
@@ -2188,9 +2188,16 @@ static int qlcnic_rx_poll(struct napi_struct *napi, int budget)
#ifdef CONFIG_NET_POLL_CONTROLLER
static void qlcnic_poll_controller(struct net_device *netdev)
{
int ring;
struct qlcnic_host_sds_ring *sds_ring;
struct qlcnic_adapter *adapter = netdev_priv(netdev);
struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
disable_irq(adapter->irq);
qlcnic_intr(adapter->irq, adapter);
for (ring = 0; ring < adapter->max_sds_rings; ring++) {
sds_ring = &recv_ctx->sds_rings[ring];
qlcnic_intr(adapter->irq, sds_ring);
}
enable_irq(adapter->irq);
}
#endif
drivers/net/qlge/qlge_main.c
+2 -2
View File
@@ -3919,12 +3919,12 @@ static int ql_adapter_down(struct ql_adapter *qdev)
for (i = 0; i < qdev->rss_ring_count; i++)
netif_napi_del(&qdev->rx_ring[i].napi);
ql_free_rx_buffers(qdev);
status = ql_adapter_reset(qdev);
if (status)
netif_err(qdev, ifdown, qdev->ndev, "reset(func #%d) FAILED!\n",
qdev->func);
ql_free_rx_buffers(qdev);
return status;
}
drivers/s390/char/ctrlchar.c
+1 -3
View File
@@ -16,12 +16,11 @@
#ifdef CONFIG_MAGIC_SYSRQ
static int ctrlchar_sysrq_key;
static struct tty_struct *sysrq_tty;
static void
ctrlchar_handle_sysrq(struct work_struct *work)
{
handle_sysrq(ctrlchar_sysrq_key, sysrq_tty);
handle_sysrq(ctrlchar_sysrq_key);
}
static DECLARE_WORK(ctrlchar_work, ctrlchar_handle_sysrq);
@@ -54,7 +53,6 @@ ctrlchar_handle(const unsigned char *buf, int len, struct tty_struct *tty)
/* racy */
if (len == 3 && buf[1] == '-') {
ctrlchar_sysrq_key = buf[2];
sysrq_tty = tty;
schedule_work(&ctrlchar_work);
return CTRLCHAR_SYSRQ;
}
drivers/s390/char/keyboard.c
+1 -1
View File
@@ -305,7 +305,7 @@ kbd_keycode(struct kbd_data *kbd, unsigned int keycode)
if (kbd->sysrq) {
if (kbd->sysrq == K(KT_LATIN, '-')) {
kbd->sysrq = 0;
handle_sysrq(value, kbd->tty);
handle_sysrq(value);
return;
}
if (value == '-') {
drivers/serial/sn_console.c
+1 -1
View File
@@ -492,7 +492,7 @@ sn_receive_chars(struct sn_cons_port *port, unsigned long flags)
sysrq_requested = 0;
if (ch && time_before(jiffies, sysrq_timeout)) {
spin_unlock_irqrestore(&port->sc_port.lock, flags);
handle_sysrq(ch, NULL);
handle_sysrq(ch);
spin_lock_irqsave(&port->sc_port.lock, flags);
/* ignore actual sysrq command char */
continue;
drivers/usb/serial/ftdi_sio.c
+1 -1
View File
@@ -1834,7 +1834,7 @@ static int ftdi_process_packet(struct tty_struct *tty,
if (port->port.console && port->sysrq) {
for (i = 0; i < len; i++, ch++) {
if (!usb_serial_handle_sysrq_char(tty, port, *ch))
if (!usb_serial_handle_sysrq_char(port, *ch))
tty_insert_flip_char(tty, *ch, flag);
}
} else {
drivers/usb/serial/generic.c
+4 -6
View File
@@ -343,7 +343,7 @@ void usb_serial_generic_process_read_urb(struct urb *urb)
tty_insert_flip_string(tty, ch, urb->actual_length);
else {
for (i = 0; i < urb->actual_length; i++, ch++) {
if (!usb_serial_handle_sysrq_char(tty, port, *ch))
if (!usb_serial_handle_sysrq_char(port, *ch))
tty_insert_flip_char(tty, *ch, TTY_NORMAL);
}
}
@@ -448,12 +448,11 @@ void usb_serial_generic_unthrottle(struct tty_struct *tty)
EXPORT_SYMBOL_GPL(usb_serial_generic_unthrottle);
#ifdef CONFIG_MAGIC_SYSRQ
int usb_serial_handle_sysrq_char(struct tty_struct *tty,
struct usb_serial_port *port, unsigned int ch)
int usb_serial_handle_sysrq_char(struct usb_serial_port *port, unsigned int ch)
{
if (port->sysrq && port->port.console) {
if (ch && time_before(jiffies, port->sysrq)) {
handle_sysrq(ch, tty);
handle_sysrq(ch);
port->sysrq = 0;
return 1;
}
@@ -462,8 +461,7 @@ int usb_serial_handle_sysrq_char(struct tty_struct *tty,
return 0;
}
#else
int usb_serial_handle_sysrq_char(struct tty_struct *tty,
struct usb_serial_port *port, unsigned int ch)
int usb_serial_handle_sysrq_char(struct usb_serial_port *port, unsigned int ch)
{
return 0;
}
drivers/usb/serial/pl2303.c
+1 -1
View File
@@ -789,7 +789,7 @@ static void pl2303_process_read_urb(struct urb *urb)
if (port->port.console && port->sysrq) {
for (i = 0; i < urb->actual_length; ++i)
if (!usb_serial_handle_sysrq_char(tty, port, data[i]))
if (!usb_serial_handle_sysrq_char(port, data[i]))
tty_insert_flip_char(tty, data[i], tty_flag);
} else {
tty_insert_flip_string_fixed_flag(tty, data, tty_flag,
drivers/usb/serial/ssu100.c
+1 -1
View File
@@ -672,7 +672,7 @@ static int ssu100_process_packet(struct tty_struct *tty,
if (port->port.console && port->sysrq) {
for (i = 0; i < len; i++, ch++) {
if (!usb_serial_handle_sysrq_char(tty, port, *ch))
if (!usb_serial_handle_sysrq_char(port, *ch))
tty_insert_flip_char(tty, *ch, flag);
}
} else
drivers/xen/manage.c
+1 -1
View File
@@ -237,7 +237,7 @@ static void sysrq_handler(struct xenbus_watch *watch, const char **vec,
goto again;
if (sysrq_key != '\0')
handle_sysrq(sysrq_key, NULL);
handle_sysrq(sysrq_key);
}
static struct xenbus_watch sysrq_watch = {
fs/ceph/addr.c
+3 -9
View File
@@ -87,7 +87,7 @@ static int ceph_set_page_dirty(struct page *page)
/* dirty the head */
spin_lock(&inode->i_lock);
if (ci->i_wrbuffer_ref_head == 0)
if (ci->i_head_snapc == NULL)
ci->i_head_snapc = ceph_get_snap_context(snapc);
++ci->i_wrbuffer_ref_head;
if (ci->i_wrbuffer_ref == 0)
@@ -105,13 +105,7 @@ static int ceph_set_page_dirty(struct page *page)
spin_lock_irq(&mapping->tree_lock);
if (page->mapping) { /* Race with truncate? */
WARN_ON_ONCE(!PageUptodate(page));
if (mapping_cap_account_dirty(mapping)) {
__inc_zone_page_state(page, NR_FILE_DIRTY);
__inc_bdi_stat(mapping->backing_dev_info,
BDI_RECLAIMABLE);
task_io_account_write(PAGE_CACHE_SIZE);
}
account_page_dirtied(page, page->mapping);
radix_tree_tag_set(&mapping->page_tree,
page_index(page), PAGECACHE_TAG_DIRTY);
@@ -352,7 +346,7 @@ static struct ceph_snap_context *get_oldest_context(struct inode *inode,
break;
}
}
if (!snapc && ci->i_head_snapc) {
if (!snapc && ci->i_wrbuffer_ref_head) {
snapc = ceph_get_snap_context(ci->i_head_snapc);
dout(" head snapc %p has %d dirty pages\n",
snapc, ci->i_wrbuffer_ref_head);
fs/ceph/auth_x.c
+9 -6
View File
@@ -376,7 +376,7 @@ static void ceph_x_validate_tickets(struct ceph_auth_client *ac, int *pneed)
th = get_ticket_handler(ac, service);
if (!th) {
if (IS_ERR(th)) {
*pneed |= service;
continue;
}
@@ -399,6 +399,9 @@ static int ceph_x_build_request(struct ceph_auth_client *ac,
struct ceph_x_ticket_handler *th =
get_ticket_handler(ac, CEPH_ENTITY_TYPE_AUTH);
if (IS_ERR(th))
return PTR_ERR(th);
ceph_x_validate_tickets(ac, &need);
dout("build_request want %x have %x need %x\n",
@@ -450,7 +453,6 @@ static int ceph_x_build_request(struct ceph_auth_client *ac,
return -ERANGE;
head->op = cpu_to_le16(CEPHX_GET_PRINCIPAL_SESSION_KEY);
BUG_ON(!th);
ret = ceph_x_build_authorizer(ac, th, &xi->auth_authorizer);
if (ret)
return ret;
@@ -505,7 +507,8 @@ static int ceph_x_handle_reply(struct ceph_auth_client *ac, int result,
case CEPHX_GET_PRINCIPAL_SESSION_KEY:
th = get_ticket_handler(ac, CEPH_ENTITY_TYPE_AUTH);
BUG_ON(!th);
if (IS_ERR(th))
return PTR_ERR(th);
ret = ceph_x_proc_ticket_reply(ac, &th->session_key,
buf + sizeof(*head), end);
break;
@@ -563,8 +566,8 @@ static int ceph_x_verify_authorizer_reply(struct ceph_auth_client *ac,
void *end = p + sizeof(au->reply_buf);
th = get_ticket_handler(ac, au->service);
if (!th)
return -EIO; /* hrm! */
if (IS_ERR(th))
return PTR_ERR(th);
ret = ceph_x_decrypt(&th->session_key, &p, end, &reply, sizeof(reply));
if (ret < 0)
return ret;
@@ -626,7 +629,7 @@ static void ceph_x_invalidate_authorizer(struct ceph_auth_client *ac,
struct ceph_x_ticket_handler *th;
th = get_ticket_handler(ac, peer_type);
if (th && !IS_ERR(th))
if (!IS_ERR(th))
remove_ticket_handler(ac, th);
}
fs/ceph/caps.c
+23 -9
View File
@@ -1082,6 +1082,7 @@ static int __send_cap(struct ceph_mds_client *mdsc, struct ceph_cap *cap,
gid_t gid;
struct ceph_mds_session *session;
u64 xattr_version = 0;
struct ceph_buffer *xattr_blob = NULL;
int delayed = 0;
u64 flush_tid = 0;
int i;
@@ -1142,6 +1143,10 @@ static int __send_cap(struct ceph_mds_client *mdsc, struct ceph_cap *cap,
for (i = 0; i < CEPH_CAP_BITS; i++)
if (flushing & (1 << i))
ci->i_cap_flush_tid[i] = flush_tid;
follows = ci->i_head_snapc->seq;
} else {
follows = 0;
}
keep = cap->implemented;
@@ -1155,14 +1160,14 @@ static int __send_cap(struct ceph_mds_client *mdsc, struct ceph_cap *cap,
mtime = inode->i_mtime;
atime = inode->i_atime;
time_warp_seq = ci->i_time_warp_seq;
follows = ci->i_snap_realm->cached_context->seq;
uid = inode->i_uid;
gid = inode->i_gid;
mode = inode->i_mode;
if (dropping & CEPH_CAP_XATTR_EXCL) {
if (flushing & CEPH_CAP_XATTR_EXCL) {
__ceph_build_xattrs_blob(ci);
xattr_version = ci->i_xattrs.version + 1;
xattr_blob = ci->i_xattrs.blob;
xattr_version = ci->i_xattrs.version;
}
spin_unlock(&inode->i_lock);
@@ -1170,9 +1175,7 @@ static int __send_cap(struct ceph_mds_client *mdsc, struct ceph_cap *cap,
ret = send_cap_msg(session, ceph_vino(inode).ino, cap_id,
op, keep, want, flushing, seq, flush_tid, issue_seq, mseq,
size, max_size, &mtime, &atime, time_warp_seq,
uid, gid, mode,
xattr_version,
(flushing & CEPH_CAP_XATTR_EXCL) ? ci->i_xattrs.blob : NULL,
uid, gid, mode, xattr_version, xattr_blob,
follows);
if (ret < 0) {
dout("error sending cap msg, must requeue %p\n", inode);
@@ -1282,7 +1285,7 @@ retry:
&capsnap->mtime, &capsnap->atime,
capsnap->time_warp_seq,
capsnap->uid, capsnap->gid, capsnap->mode,
0, NULL,
capsnap->xattr_version, capsnap->xattr_blob,
capsnap->follows);
next_follows = capsnap->follows + 1;
@@ -1332,7 +1335,11 @@ void __ceph_mark_dirty_caps(struct ceph_inode_info *ci, int mask)
ceph_cap_string(was | mask));
ci->i_dirty_caps |= mask;
if (was == 0) {
dout(" inode %p now dirty\n", &ci->vfs_inode);
if (!ci->i_head_snapc)
ci->i_head_snapc = ceph_get_snap_context(
ci->i_snap_realm->cached_context);
dout(" inode %p now dirty snapc %p\n", &ci->vfs_inode,
ci->i_head_snapc);
BUG_ON(!list_empty(&ci->i_dirty_item));
spin_lock(&mdsc->cap_dirty_lock);
list_add(&ci->i_dirty_item, &mdsc->cap_dirty);
@@ -2190,7 +2197,9 @@ void ceph_put_wrbuffer_cap_refs(struct ceph_inode_info *ci, int nr,
if (ci->i_head_snapc == snapc) {
ci->i_wrbuffer_ref_head -= nr;
if (!ci->i_wrbuffer_ref_head) {
if (ci->i_wrbuffer_ref_head == 0 &&
ci->i_dirty_caps == 0 && ci->i_flushing_caps == 0) {
BUG_ON(!ci->i_head_snapc);
ceph_put_snap_context(ci->i_head_snapc);
ci->i_head_snapc = NULL;
}
@@ -2483,6 +2492,11 @@ static void handle_cap_flush_ack(struct inode *inode, u64 flush_tid,
dout(" inode %p now clean\n", inode);
BUG_ON(!list_empty(&ci->i_dirty_item));
drop = 1;
if (ci->i_wrbuffer_ref_head == 0) {
BUG_ON(!ci->i_head_snapc);
ceph_put_snap_context(ci->i_head_snapc);
ci->i_head_snapc = NULL;
}
} else {
BUG_ON(list_empty(&ci->i_dirty_item));
}

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