iio: adc: ti-ads8688: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 3e87e78383 ("iio: adc: Add TI ADS8688")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-39-jic23@kernel.org
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@@ -71,7 +71,7 @@ struct ads8688_state {
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union {
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__be32 d32;
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u8 d8[4];
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} data[2] ____cacheline_aligned;
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} data[2] __aligned(IIO_DMA_MINALIGN);
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};
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enum ads8688_id {
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