tmakin/ack-tegra
1
0 Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge tag 'pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Browse Source 
Pull pin control updates from Linus Walleij:
 "The technical details below. For me the CIX Semi and Axis
  Communications ARTPEC-9 SoCs were the most interesting new drivers in
  this merge window.

  Core changes:

   - Handle per-direction skew control in the generic pin config

   - Drop the pointless subsystem boilerplate banner message during
     boot. Less noise in the console. It's available as debug message if
     someone really want it

  New drivers:

   - Samsung Exynos 8890 SoC support

   - Samsung Exynos derived Axis Communications ARTPEC-9 SoC support.
     These guys literally live next door to me, ARTPEC spells out "Axis
     Real-Time Picture Encoding Chip" and is tailored for camera image
     streams and is something they have evolved for a quarter of a
     century

   - Mediatek MT6878 SoC support

   - Qualcomm Glymur PMIC support (mostly just compatible strings)

   - Qualcomm Kaanapali SoC TLMM support

   - Microchip pic64gx "gpio2" SoC support

   - Microchip Polarfire "iomux0" SoC support

   - CIX Semiconductors SKY1 SoC support

   - Rockchip RK3506 SoC support

   - Airhoa AN7583 chip support

  Improvements:

   - Improvements for ST Microelectronics STM32 handling of skew
     settings so input and output can have different skew settings

   - A whole bunch of device tree binding cleanups: Marvell Armada and
     Berlin, Actions Semiconductor S700 and S900, Broadcom Northstar 2
     (NS2), Bitmain BM1880 and Spreadtrum SC9860 are moved over to
     schema"

* tag 'pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
  pinctrl: add CONFIG_OF dependencies for microchip drivers
  pinctrl: starfive: use dynamic GPIO base allocation
  pinctrl: single: Fix incorrect type for error return variable
  MAINTAINERS: Change Linus Walleij mail address
  pinctrl: cix: Fix obscure dependency
  dt-bindings: pinctrl: cix,sky1-pinctrl: Drop duplicate newline
  dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group
  pinctrl: airoha: Fix AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data
  pinctrl: airoha: fix pinctrl function mismatch issue
  pinctrl: cherryview: Convert to use intel_gpio_add_pin_ranges()
  pinctrl: intel: Export intel_gpio_add_pin_ranges()
  pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling
  pinctrl: airoha: convert comma to semicolon
  pinctrl: elkhartlake: Switch to INTEL_GPP() macro
  pinctrl: cherryview: Switch to INTEL_GPP() macro
  pinctrl: emmitsburg: Switch to INTEL_GPP() macro
  pinctrl: denverton: Switch to INTEL_GPP() macro
  pinctrl: cedarfork: Switch to INTEL_GPP() macro
  pinctrl: airoha: add support for Airoha AN7583 PINs
  dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller
  ...
This commit is contained in:
Linus Torvalds committed 2025-12-09 06:45:00 +09:00
2 parents 990fa99821 666065caa3
commit a110f94267
116 files changed
+12444 -3006
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
-29
View File
@@ -1,29 +0,0 @@
* Xtal Clock bindings for Marvell Armada 37xx SoCs
Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
reading the gpio latch register.
This node must be a subnode of the node exposing the register address
of the GPIO block where the gpio latch is located.
See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
Required properties:
- compatible : shall be one of the following:
"marvell,armada-3700-xtal-clock"
- #clock-cells : from common clock binding; shall be set to 0
Optional properties:
- clock-output-names : from common clock binding; allows overwrite default clock
output names ("xtal")
Example:
pinctrl_nb: pinctrl-nb@13800 {
compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
reg = <0x13800 0x100>, <0x13C00 0x20>;
xtalclk: xtal-clk {
compatible = "marvell,armada-3700-xtal-clock";
clock-output-names = "xtal";
#clock-cells = <0>;
};
};
Documentation/devicetree/bindings/mfd/syscon-common.yaml
-3
View File
@@ -35,9 +35,6 @@ properties:
minItems: 2
maxItems: 5 # Should be enough
reg:
maxItems: 1
reg-io-width:
description:
The size (in bytes) of the IO accesses that should be performed
Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt
-170
View File
@@ -1,170 +0,0 @@
Actions Semi S700 Pin Controller
This binding describes the pin controller found in the S700 SoC.
Required Properties:
- compatible: Should be "actions,s700-pinctrl"
- reg: Should contain the register base address and size of
the pin controller.
- clocks: phandle of the clock feeding the pin controller
- gpio-controller: Marks the device node as a GPIO controller.
- gpio-ranges: Specifies the mapping between gpio controller and
pin-controller pins.
- #gpio-cells: Should be two. The first cell is the gpio pin number
and the second cell is used for optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt. Shall be set to 2. The first cell
defines the interrupt number, the second encodes
the trigger flags described in
bindings/interrupt-controller/interrupts.txt
- interrupts: The interrupt outputs from the controller. There is one GPIO
interrupt per GPIO bank. The number of interrupts listed depends
on the number of GPIO banks on the SoC. The interrupts must be
ordered by bank, starting with bank 0.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
Pinmux functions are available only for the pin groups while pinconf
parameters are available for both pin groups and individual pins.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
Required Properties:
- pins: An array of strings, each string containing the name of a pin.
These pins are used for selecting the pull control and schmitt
trigger parameters. The following are the list of pins
available:
eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer,
eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk,
eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2,
ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp,
lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap,
lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18,
lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn,
dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2,
sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk,
sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx,
uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,
uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk,
i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1,
csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2,
dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb,
dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0,
dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2,
dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3
- groups: An array of strings, each string containing the name of a pin
group. These pin groups are used for selecting the pinmux
functions.
rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp,
rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp,
rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp,
i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp,
i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp,
ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp,
lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp,
dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp,
uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp,
sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp,
i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp,
pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp,
nand_ceb2_mfp, nand_ceb3_mfp
These pin groups are used for selecting the drive strength
parameters.
sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv,
rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv,
smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv,
pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv,
dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv,
uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv,
sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv
- function: An array of strings, each string containing the name of the
pinmux functions. These functions can only be selected by
the corresponding pin groups. The following are the list of
pinmux functions available:
nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1,
uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0,
sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30,
clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0
Optional Properties:
- bias-pull-down: No arguments. The specified pins should be configured as
pull down.
- bias-pull-up: No arguments. The specified pins should be configured as
pull up.
- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
pins
- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
pins
- drive-strength: Integer. Selects the drive strength for the specified
pins in mA.
Valid values are:
<2>
<4>
<8>
<12>
Example:
pinctrl: pinctrl@e01b0000 {
compatible = "actions,s700-pinctrl";
reg = <0x0 0xe01b0000 0x0 0x1000>;
clocks = <&cmu CLK_GPIO>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 136>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
uart3-default: uart3-default {
pinmux {
groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp";
function = "uart3";
};
pinconf {
groups = "uart3_all_drv";
drive-strength = <2>;
};
};
};
Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.yaml
+204
View File
@@ -0,0 +1,204 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/actions,s700-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Actions Semi S700 Pin Controller
maintainers:
- Manivannan Sadhasivam <mani@kernel.org>
properties:
compatible:
const: actions,s700-pinctrl
reg:
maxItems: 1
clocks:
maxItems: 1
gpio-controller: true
gpio-line-names:
maxItems: 136
gpio-ranges: true
'#gpio-cells':
const: 2
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
maxItems: 5
description:
The interrupt outputs from the controller. There is one GPIO interrupt per
GPIO bank. The interrupts must be ordered by bank, starting with
bank 0.
additionalProperties:
type: object
description: Pin configuration subnode
additionalProperties: false
properties:
pinmux:
description: Configure pin multiplexing.
type: object
$ref: /schemas/pinctrl/pinmux-node.yaml#
additionalProperties: false
properties:
groups:
items:
enum: [
rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp,
rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp,
rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp,
i2c1_dummy, i2c2_dummy, i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp,
i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp,
ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp,
lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp,
dsi_dnp1_cp_d2_mfp, dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp,
dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp,
uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp,
pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp,
dnand_acle_ce0_mfp, nand_ceb2_mfp, nand_ceb3_mfp
]
function:
items:
enum: [
nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1,
uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, pcm1,
pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, sd0, sd1,
sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, clko_25m, mipi_csi,
nand, spdif, sirq0, sirq1, sirq2, bt, lcd0
]
required:
- groups
- function
pinconf:
description: Configure pin-specific parameters.
type: object
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml#
- $ref: /schemas/pinctrl/pinmux-node.yaml#
additionalProperties: false
properties:
groups:
items:
enum: [
sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv,
rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv,
smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv,
pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv,
dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv,
spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv,
i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv, sens0_ckout_drv,
uart3_all_drv
]
pins:
items:
enum: [
eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer,
eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk,
eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2,
ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp,
lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap,
lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18,
lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn,
dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2,
sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd,
sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, uart2_rx,
uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb,
uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata,
i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, csi_cn, csi_cp,
csi_dn2, csi_dp2, csi_dn3, csi_dp3, sensor0_pclk, sensor0_ckout,
dnand_d0, dnand_d1, dnand_d2, dnand_d3, dnand_d4, dnand_d5,
dnand_d6, dnand_d7, dnand_wrb, dnand_rdb, dnand_rdbn, dnand_dqs,
dnand_dqsn, dnand_rb0, dnand_ale, dnand_cle, dnand_ceb0,
dnand_ceb1, dnand_ceb2, dnand_ceb3, porb, clko_25m, bsel, pkg0,
pkg1, pkg2, pkg3
]
bias-pull-down:
type: boolean
bias-pull-up:
type: boolean
drive-strength:
description: Selects the drive strength for the specified pins in mA.
enum: [2, 4, 8, 12]
input-schmitt-enable: true
input-schmitt-disable: true
oneOf:
- required:
- groups
- required:
- pins
anyOf:
- required: [ pinmux ]
- required: [ pinconf ]
required:
- compatible
- reg
- clocks
- gpio-controller
- gpio-ranges
- '#gpio-cells'
- interrupt-controller
- '#interrupt-cells'
- interrupts
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl: pinctrl@e01b0000 {
compatible = "actions,s700-pinctrl";
reg = <0xe01b0000 0x1000>;
clocks = <&cmu 1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 136>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
uart3-default {
pinmux {
groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp";
function = "uart3";
};
pinconf {
groups = "uart3_all_drv";
drive-strength = <2>;
};
};
};
Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
-204
View File
@@ -1,204 +0,0 @@
Actions Semi S900 Pin Controller
This binding describes the pin controller found in the S900 SoC.
Required Properties:
- compatible: Should be "actions,s900-pinctrl"
- reg: Should contain the register base address and size of
the pin controller.
- clocks: phandle of the clock feeding the pin controller
- gpio-controller: Marks the device node as a GPIO controller.
- gpio-ranges: Specifies the mapping between gpio controller and
pin-controller pins.
- #gpio-cells: Should be two. The first cell is the gpio pin number
and the second cell is used for optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt. Shall be set to 2. The first cell
defines the interrupt number, the second encodes
the trigger flags described in
bindings/interrupt-controller/interrupts.txt
- interrupts: The interrupt outputs from the controller. There is one GPIO
interrupt per GPIO bank. The number of interrupts listed depends
on the number of GPIO banks on the SoC. The interrupts must be
ordered by bank, starting with bank 0.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
Pinmux functions are available only for the pin groups while pinconf
parameters are available for both pin groups and individual pins.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
Required Properties:
- pins: An array of strings, each string containing the name of a pin.
These pins are used for selecting the pull control and schmitt
trigger parameters. The following are the list of pins
available:
eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv,
eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio,
sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0,
i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5,
eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan,
lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean,
sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1,
sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb,
uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx,
uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata,
i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1,
csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3,
csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3,
nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs,
nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1,
nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2,
nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs,
nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1,
nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3
- groups: An array of strings, each string containing the name of a pin
group. These pin groups are used for selecting the pinmux
functions.
lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp,
pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp,
eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp,
eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp,
lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp,
spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp,
uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp,
csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp,
dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
csi1_dn0_dp0_mfp, uart4_rx_tx_mfp
These pin groups are used for selecting the drive strength
parameters.
sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv,
rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv,
rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv,
sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv,
i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv,
lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv,
sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv,
spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv,
uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv
These pin groups are used for selecting the slew rate
parameters.
sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
sensor0_sr
- function: An array of strings, each string containing the name of the
pinmux functions. These functions can only be selected by
the corresponding pin groups. The following are the list of
pinmux functions available:
eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
nand1, spdif, sirq0, sirq1, sirq2
Optional Properties:
- bias-bus-hold: No arguments. The specified pins should retain the previous
state value.
- bias-high-impedance: No arguments. The specified pins should be configured
as high impedance.
- bias-pull-down: No arguments. The specified pins should be configured as
pull down.
- bias-pull-up: No arguments. The specified pins should be configured as
pull up.
- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
pins
- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
pins
- slew-rate: Integer. Sets slew rate for the specified pins.
Valid values are:
<0> - Slow
<1> - Fast
- drive-strength: Integer. Selects the drive strength for the specified
pins in mA.
Valid values are:
<2>
<4>
<8>
<12>
Example:
pinctrl: pinctrl@e01b0000 {
compatible = "actions,s900-pinctrl";
reg = <0x0 0xe01b0000 0x0 0x1000>;
clocks = <&cmu CLK_GPIO>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 146>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
uart2-default: uart2-default {
pinmux {
groups = "lvds_oep_odn_mfp";
function = "uart2";
};
pinconf {
groups = "lvds_oep_odn_drv";
drive-strength = <12>;
};
};
};
Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.yaml
+219
View File
@@ -0,0 +1,219 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/actions,s900-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Actions Semi S900 Pin Controller
maintainers:
- Manivannan Sadhasivam <mani@kernel.org>
properties:
compatible:
const: actions,s900-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 6
description: The interrupt outputs from the controller. There is one GPIO
interrupt per GPIO bank. The number of interrupts listed depends on the
number of GPIO banks on the SoC. The interrupts must be ordered by bank,
starting with bank 0.
interrupt-controller: true
"#interrupt-cells":
const: 2
clocks:
maxItems: 1
gpio-controller: true
gpio-line-names:
maxItems: 146
gpio-ranges: true
"#gpio-cells":
const: 2
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
- clocks
- gpio-controller
- gpio-ranges
- "#gpio-cells"
additionalProperties:
type: object
description: Pin configuration subnode
additionalProperties: false
properties:
pinmux:
type: object
description: Pin mux configuration
$ref: /schemas/pinctrl/pinmux-node.yaml#
additionalProperties: false
properties:
groups:
items:
enum: [
lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, pcm1_clk_mfp,
pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, eram_a7_mfp, eram_a8_mfp,
eram_a9_mfp, eram_a10_mfp, eram_a11_mfp, lvds_oep_odn_mfp,
lvds_ocp_obn_mfp, lvds_oap_oan_mfp, lvds_e_mfp,
spi0_sclk_mosi_mfp, spi0_ss_mfp, spi0_miso_mfp, uart2_rtsb_mfp,
uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp,
sd0_d1_mfp, sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp,
sd0_clk_mfp, sd1_cmd_clk_mfp, uart0_rx_mfp, nand0_d0_ceb3_mfp,
uart0_tx_mfp, i2c0_mfp, csi0_cn_cp_mfp, csi0_dn0_dp3_mfp,
csi1_dn0_cp_mfp, dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
csi1_dn0_dp0_mfp, uart4_rx_tx_mfp
]
function:
items:
enum: [
eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
nand1, spdif, sirq0, sirq1, sirq2
]
required:
- groups
- function
pinconf:
type: object
description: Pin configuration parameters
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml#
- $ref: /schemas/pinctrl/pinmux-node.yaml#
additionalProperties: false
properties:
groups:
items:
enum: [
# pin groups for drive strength
sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, rmii_tx_d0_d1_drv,
rmii_txen_rxer_drv, rmii_crs_dv_drv, rmii_rx_d1_d0_drv,
rmii_ref_clk_drv, rmii_mdc_mdio_drv, sirq_0_1_drv, sirq2_drv,
i2s_d0_d1_drv, i2s_lr_m_clk0_drv, i2s_blk1_mclk1_drv,
pcm1_in_out_drv, lvds_oap_oan_drv, lvds_oep_odn_drv,
lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, sd1_d3_d0_drv,
sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, spi0_ss_miso_drv,
uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, uart3_drv, i2c0_drv,
i2c1_drv, i2c2_drv, sensor0_drv,
# pin groups for slew rate
sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
sensor0_sr
]
pins:
items:
enum: [
eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, eth_rxd1,
eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, sirq0, sirq1, sirq2,
i2s_d0, i2s_bclk0, i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1,
i2s_lrclk1, i2s_mclk1, pcm1_in, pcm1_clk, pcm1_sync, pcm1_out,
eram_a5, eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, lvds_ocn,
lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep, lvds_een,
lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp, lvds_ebn,
lvds_eap, lvds_ean, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0,
sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, uart0_tx,
uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,
uart3_rtsb, uart3_ctsb, uart4_rx, uart4_tx, i2c0_sclk, i2c0_sdata,
i2c1_sclk, i2c1_sdata, i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0,
csi0_dn1, csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2,
csi0_dn3, csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
csi1_dn0, csi1_dp0, csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, nand0_d4,
nand0_d5, nand0_d6, nand0_d7, nand0_dqs, nand0_dqsn, nand0_ale,
nand0_cle, nand0_ceb0, nand0_ceb1, nand0_ceb2, nand0_ceb3,
nand1_d0, nand1_d1, nand1_d2, nand1_d3, nand1_d4, nand1_d5,
nand1_d6, nand1_d7, nand1_dqs, nand1_dqsn, nand1_ale, nand1_cle,
nand1_ceb0, nand1_ceb1, nand1_ceb2, nand1_ceb3, sgpio0, sgpio1,
sgpio2, sgpio3
]
bias-bus-hold: true
bias-high-impedance: true
bias-pull-down:
type: boolean
bias-pull-up:
type: boolean
input-schmitt-enable: true
input-schmitt-disable: true
slew-rate: true
drive-strength: true
oneOf:
- required:
- groups
- required:
- pins
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl: pinctrl@e01b0000 {
compatible = "actions,s900-pinctrl";
reg = <0xe01b0000 0x1000>;
clocks = <&cmu 1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 146>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
uart2-default {
pinmux {
groups = "lvds_oep_odn_mfp";
function = "uart2";
};
pinconf {
groups = "lvds_oep_odn_drv";
drive-strength = <12>;
};
};
};
Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
+402
View File
@@ -0,0 +1,402 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/airoha,an7583-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Airoha AN7583 Pin Controller
maintainers:
- Lorenzo Bianconi <lorenzo@kernel.org>
description:
The Airoha's AN7583 Pin controller is used to control SoC pins.
properties:
compatible:
const: airoha,an7583-pinctrl
interrupts:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- interrupts
- gpio-controller
- "#gpio-cells"
- interrupt-controller
- "#interrupt-cells"
patternProperties:
'-pins$':
type: object
patternProperties:
'^mux(-|$)':
type: object
description:
pinmux configuration nodes.
$ref: /schemas/pinctrl/pinmux-node.yaml
properties:
function:
description:
A string containing the name of the function to mux to the group.
enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0,
phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
phy3_led1, phy4_led1]
groups:
description:
An array of strings. Each string contains the name of a group.
required:
- function
- groups
allOf:
- if:
properties:
function:
const: pon
then:
properties:
groups:
enum: [pon]
- if:
properties:
function:
const: tod_1pps
then:
properties:
groups:
enum: [pon_tod_1pps, gsw_tod_1pps]
- if:
properties:
function:
const: sipo
then:
properties:
groups:
enum: [sipo, sipo_rclk]
- if:
properties:
function:
const: mdio
then:
properties:
groups:
enum: [mdio]
- if:
properties:
function:
const: uart
then:
properties:
groups:
items:
enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts,
uart4, uart5]
maxItems: 2
- if:
properties:
function:
const: i2c
then:
properties:
groups:
enum: [i2c1]
- if:
properties:
function:
const: jtag
then:
properties:
groups:
enum: [jtag_udi, jtag_dfd]
- if:
properties:
function:
const: pcm
then:
properties:
groups:
enum: [pcm1, pcm2]
- if:
properties:
function:
const: spi
then:
properties:
groups:
items:
enum: [spi_quad, spi_cs1]
maxItems: 2
- if:
properties:
function:
const: pcm_spi
then:
properties:
groups:
items:
enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4]
maxItems: 7
- if:
properties:
function:
const: i2c
then:
properties:
groups:
enum: [i2s]
- if:
properties:
function:
const: emmc
then:
properties:
groups:
enum: [emmc]
- if:
properties:
function:
const: pnand
then:
properties:
groups:
enum: [pnand]
- if:
properties:
function:
const: pcie_reset
then:
properties:
groups:
enum: [pcie_reset0, pcie_reset1]
- if:
properties:
function:
const: pwm
then:
properties:
groups:
enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6,
gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13,
gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]
- if:
properties:
function:
const: phy1_led0
then:
properties:
groups:
enum: [gpio1, gpio2, gpio3, gpio4]
- if:
properties:
function:
const: phy2_led0
then:
properties:
groups:
enum: [gpio1, gpio2, gpio3, gpio4]
- if:
properties:
function:
const: phy3_led0
then:
properties:
groups:
enum: [gpio1, gpio2, gpio3, gpio4]
- if:
properties:
function:
const: phy4_led0
then:
properties:
groups:
enum: [gpio1, gpio2, gpio3, gpio4]
- if:
properties:
function:
const: phy1_led1
then:
properties:
groups:
enum: [gpio8, gpio9, gpio10, gpio11]
- if:
properties:
function:
const: phy2_led1
then:
properties:
groups:
enum: [gpio8, gpio9, gpio10, gpio11]
- if:
properties:
function:
const: phy3_led1
then:
properties:
groups:
enum: [gpio8, gpio9, gpio10, gpio11]
- if:
properties:
function:
const: phy4_led1
then:
properties:
groups:
enum: [gpio8, gpio9, gpio10, gpio11]
additionalProperties: false
'^conf(-|$)':
type: object
description:
pinconf configuration nodes.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pins:
description:
An array of strings. Each string contains the name of a pin.
items:
enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk,
spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4,
gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12,
gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26,
gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33,
gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40,
gpio41, gpio42, gpio43, gpio44, gpio45, gpio46,
pcie_reset0, pcie_reset1, pcie_reset2]
minItems: 1
maxItems: 58
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-enable: true
output-enable: true
output-low: true
output-high: true
drive-open-drain: true
drive-strength:
description:
Selects the drive strength for MIO pins, in mA.
enum: [2, 4, 6, 8]
required:
- pins
additionalProperties: false
additionalProperties: false
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl {
compatible = "airoha,an7583-pinctrl";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
pcie1-rst-pins {
conf {
pins = "pcie_reset1";
drive-open-drain = <1>;
};
};
pwm-pins {
mux {
function = "pwm";
groups = "gpio18";
};
};
spi-pins {
mux {
function = "spi";
groups = "spi_quad", "spi_cs1";
};
};
uart2-pins {
mux {
function = "uart";
groups = "uart2", "uart2_cts_rts";
};
};
uar5-pins {
mux {
function = "uart";
groups = "uart5";
};
};
mmc-pins {
mux {
function = "emmc";
groups = "emmc";
};
};
mdio-pins {
mux {
function = "mdio";
groups = "mdio";
};
conf {
pins = "gpio2";
output-enable;
};
};
};
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
+2
View File
@@ -141,6 +141,7 @@ additionalProperties:
- NRTS3
- NRTS4
- OSCCLK
- PCIERC1
- PEWAKE
- PWM0
- PWM1
@@ -369,6 +370,7 @@ additionalProperties:
- NRTS3
- NRTS4
- OSCCLK
- PCIERC1
- PEWAKE
- PWM0
- PWM1
Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt
-47
View File
@@ -1,47 +0,0 @@
* Pin-controller driver for the Marvell Berlin SoCs
Pin control registers are part of both chip controller and system
controller register sets. Pin controller nodes should be a sub-node of
either the chip controller or system controller node. The pins
controlled are organized in groups, so no actual pin information is
needed.
A pin-controller node should contain subnodes representing the pin group
configurations, one per function. Each subnode has the group name and
the muxing function used.
Be aware the Marvell Berlin datasheets use the keyword 'mode' for what
is called a 'function' in the pin-controller subsystem.
Required properties:
- compatible: should be one of:
"marvell,berlin2-soc-pinctrl",
"marvell,berlin2-system-pinctrl",
"marvell,berlin2cd-soc-pinctrl",
"marvell,berlin2cd-system-pinctrl",
"marvell,berlin2q-soc-pinctrl",
"marvell,berlin2q-system-pinctrl",
"marvell,berlin4ct-avio-pinctrl",
"marvell,berlin4ct-soc-pinctrl",
"marvell,berlin4ct-system-pinctrl",
"syna,as370-soc-pinctrl"
Required subnode-properties:
- groups: a list of strings describing the group names.
- function: a string describing the function used to mux the groups.
Example:
sys_pinctrl: pin-controller {
compatible = "marvell,berlin2q-system-pinctrl";
uart0_pmux: uart0-pmux {
groups = "GSM12";
function = "uart0";
};
};
&uart0 {
pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";
};
Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt
-126
View File
@@ -1,126 +0,0 @@
Bitmain BM1880 Pin Controller
This binding describes the pin controller found in the BM1880 SoC.
Required Properties:
- compatible: Should be "bitmain,bm1880-pinctrl"
- reg: Offset and length of pinctrl space in SCTRL.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
includes pinmux and various pin configuration parameters, such as pull-up,
slew rate etc...
Each configuration node can consist of multiple nodes describing the pinmux
options. The name of each subnode is not important; all subnodes should be
enumerated and processed purely based on their content.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinmux subnode:
Required Properties:
- pins: An array of strings, each string containing the name of a pin.
Valid values for pins are:
MIO0 - MIO111
- groups: An array of strings, each string containing the name of a pin
group. Valid values for groups are:
nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp,
pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp,
pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp,
pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp,
pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp,
pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp,
pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp,
pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp,
i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp,
uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp,
uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp,
uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp,
gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp,
gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp,
gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp,
gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp,
gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp,
gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp,
gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp,
gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp,
gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp,
gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp,
gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp,
gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp,
gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp,
gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp,
i2s1_grp, i2s1_mclkin_grp, spi0_grp
- function: An array of strings, each string containing the name of the
pinmux functions. The following are the list of pinmux
functions available:
nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4,
pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13,
pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22,
pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31,
pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3,
i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7,
uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15,
gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8,
gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16,
gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23,
gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37,
gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44,
gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51,
gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58,
gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65,
gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin,
spi0
Optional Properties:
- bias-disable: No arguments. Disable pin bias.
- bias-pull-down: No arguments. The specified pins should be configured as
pull down.
- bias-pull-up: No arguments. The specified pins should be configured as
pull up.
- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
pins
- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
pins
- slew-rate: Integer. Sets slew rate for the specified pins.
Valid values are:
<0> - Slow
<1> - Fast
- drive-strength: Integer. Selects the drive strength for the specified
pins in mA.
Valid values are:
<4>
<8>
<12>
<16>
<20>
<24>
<28>
<32>
Example:
pinctrl: pinctrl@400 {
compatible = "bitmain,bm1880-pinctrl";
reg = <0x400 0x120>;
pinctrl_uart0_default: uart0-default {
pinmux {
groups = "uart0_grp";
function = "uart0";
};
};
};
Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.yaml
+132
View File
@@ -0,0 +1,132 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/bitmain,bm1880-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bitmain BM1880 Pin Controller
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
compatible:
const: bitmain,bm1880-pinctrl
reg:
maxItems: 1
additionalProperties:
description: A pin configuration node.
type: object
additionalProperties: false
properties:
pinmux:
type: object
description: Pin multiplexing parameters.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml#
- $ref: /schemas/pinctrl/pinmux-node.yaml#
additionalProperties: false
properties:
pins:
items:
pattern: '^MIO[0-9]+$'
groups:
items:
enum: [
nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp,
pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp,
pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp,
pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp,
pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp,
pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp,
pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp,
pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp,
i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp,
uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp,
uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp,
uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp,
gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp,
gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp,
gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp,
gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp,
gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp,
gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp,
gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp,
gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp,
gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp,
gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp,
gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp,
gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp,
gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp,
gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp,
i2s1_grp, i2s1_mclkin_grp, spi0_grp
]
function:
items:
enum: [
nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4,
pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13,
pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22,
pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31,
pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3,
i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7,
uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15,
gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8,
gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16,
gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23,
gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37,
gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44,
gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51,
gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58,
gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65,
gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin,
spi0
]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
input-schmitt-enable: true
input-schmitt-disable: true
slew-rate:
description: >
Sets slew rate. Valid values: 0 = Slow, 1 = Fast.
enum: [0, 1]
drive-strength:
enum: [4, 8, 12, 16, 20, 24, 28, 32]
oneOf:
- required:
- pins
- required:
- groups
required:
- function
required:
- compatible
- reg
examples:
- |
pinctrl@400 {
compatible = "bitmain,bm1880-pinctrl";
reg = <0x400 0x120>;
uart0-default {
pinmux {
groups = "uart0_grp";
function = "uart0";
};
};
};
Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt
-102
View File
@@ -1,102 +0,0 @@
Broadcom Northstar2 IOMUX Controller
The Northstar2 IOMUX controller supports group based mux configuration. There
are some individual pins that support modifying the pinconf parameters.
Required properties:
- compatible:
Must be "brcm,ns2-pinmux"
- reg:
Define the base and range of the I/O address space that contains the
Northstar2 IOMUX and pin configuration registers.
Properties in sub nodes:
- function:
The mux function to select
- groups:
The list of groups to select with a given function
- pins:
List of pin names to change configuration
The generic properties bias-disable, bias-pull-down, bias-pull-up,
drive-strength, slew-rate, input-enable, input-disable are supported
for some individual pins listed at the end.
For more details, refer to
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
For example:
pinctrl: pinctrl@6501d130 {
compatible = "brcm,ns2-pinmux";
reg = <0x6501d130 0x08>,
<0x660a0028 0x04>,
<0x660009b0 0x40>;
pinctrl-names = "default";
pinctrl-0 = <&nand_sel>, <&uart3_rx>, <&sdio0_d4>;
/* Select nand function */
nand_sel: nand_sel {
function = "nand";
groups = "nand_grp";
};
/* Pull up the uart3 rx pin */
uart3_rx: uart3_rx {
pins = "uart3_sin";
bias-pull-up;
};
/* Set the drive strength of sdio d4 pin */
sdio0_d4: sdio0_d4 {
pins = "sdio0_data4";
drive-strength = <8>;
};
};
List of supported functions and groups in Northstar2:
"nand": "nand_grp"
"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp",
"nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp",
"nor_addr_12_15_grp"
"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp",
"gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp",
"gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp",
"gpio_28_29_grp", "gpio_30_31_grp"
"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp",
"pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp"
"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp"
"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp",
"uart1_rts_cts_grp", "uart1_in_out_grp"
"uart2": "uart2_rts_cts_grp"
"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp"
List of pins that support pinconf parameters:
"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout",
"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck",
"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7",
"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4",
"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1",
"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk",
"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1",
"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk",
"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc",
"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent",
"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc",
"usb2_overcurrent", "sata_led1", "sata_led0"
Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.yaml
+111
View File
@@ -0,0 +1,111 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,ns2-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Northstar2 IOMUX Controller
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
properties:
compatible:
const: brcm,ns2-pinmux
reg:
maxItems: 3
additionalProperties:
description: Pin group node properties
type: object
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml#
- $ref: /schemas/pinctrl/pinmux-node.yaml#
additionalProperties: false
properties:
function:
description: The mux function to select
$ref: /schemas/types.yaml#/definitions/string
groups:
items:
enum: [
nand_grp, nor_data_grp, nor_adv_grp, nor_addr_0_3_grp,
nor_addr_4_5_grp, nor_addr_6_7_grp, nor_addr_8_9_grp,
nor_addr_10_11_grp, nor_addr_12_15_grp, gpio_0_1_grp, gpio_2_5_grp,
gpio_6_7_grp, gpio_8_9_grp, gpio_10_11_grp, gpio_12_13_grp,
gpio_14_17_grp, gpio_18_19_grp, gpio_20_21_grp, gpio_22_23_grp,
gpio_24_25_grp, gpio_26_27_grp, gpio_28_29_grp, gpio_30_31_grp,
pcie_ab1_clk_wak_grp, pcie_a3_clk_wak_grp, pcie_b3_clk_wak_grp,
pcie_b2_clk_wak_grp, pcie_a2_clk_wak_grp, uart0_modem_grp,
uart0_rts_cts_grp, uart0_in_out_grp, uart1_ext_clk_grp,
uart1_dcd_dsr_grp, uart1_ri_dtr_grp, uart1_rts_cts_grp,
uart1_in_out_grp, uart2_rts_cts_grp, pwm_0_grp, pwm_1_grp, pwm_2_grp,
pwm_3_grp
]
pins:
items:
enum: [
qspi_wp, qspi_hold, qspi_cs, qspi_sck, uart3_sin, uart3_sout,
qspi_mosi, qspi_miso, spi0_fss, spi0_rxd, spi0_txd, spi0_sck,
spi1_fss, spi1_rxd, spi1_txd, spi1_sck, sdio0_data7, sdio0_emmc_rst,
sdio0_led_on, sdio0_wp, sdio0_data3, sdio0_data4, sdio0_data5,
sdio0_data6, sdio0_cmd, sdio0_data0, sdio0_data1, sdio0_data2,
sdio1_led_on, sdio1_wp, sdio0_cd_l, sdio0_clk, sdio1_data5,
sdio1_data6, sdio1_data7, sdio1_emmc_rst, sdio1_data1, sdio1_data2,
sdio1_data3, sdio1_data4, sdio1_cd_l, sdio1_clk, sdio1_cmd,
sdio1_data0, ext_mdio_0, ext_mdc_0, usb3_p1_vbus_ppc,
usb3_p1_overcurrent, usb3_p0_vbus_ppc, usb3_p0_overcurrent,
usb2_presence_indication, usb2_vbus_present, usb2_vbus_ppc,
usb2_overcurrent, sata_led1, sata_led0
]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
slew-rate: true
input-enable: true
input-disable: true
oneOf:
- required:
- groups
- function
- required:
- pins
required:
- compatible
- reg
examples:
- |
pinctrl@6501d130 {
compatible = "brcm,ns2-pinmux";
reg = <0x6501d130 0x08>,
<0x660a0028 0x04>,
<0x660009b0 0x40>;
/* Select nand function */
nand-sel {
function = "nand";
groups = "nand_grp";
};
/* Pull up the uart3 rx pin */
uart3-rx {
pins = "uart3_sin";
bias-pull-up;
};
/* Set the drive strength of sdio d4 pin */
sdio0-d4 {
pins = "sdio0_data4";
drive-strength = <8>;
};
};
Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
+91
View File
@@ -0,0 +1,91 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cix Sky1 Soc Pin Controller
maintainers:
- Gary Yang <gary.yang@cixtech.com>
description:
The pin-controller is used to control Soc pins. There are two pin-controllers
on Cix Sky1 platform. one is used under S0 state, the other one is used under
S0 and S5 state.
properties:
compatible:
enum:
- cix,sky1-pinctrl
- cix,sky1-pinctrl-s5
reg:
items:
- description: gpio base
patternProperties:
'-cfg$':
type: object
additionalProperties: false
description:
A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine.
patternProperties:
'pins$':
type: object
additionalProperties: false
description:
Each subnode will list the pins it needs, and how they should
be configured, with regard to muxer configuration, bias pull,
and drive strength.
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
properties:
pinmux:
description:
Values are constructed from pin number and mux setting, pin
number is left shifted by 8 bits, then ORed with mux setting
bias-disable: true
bias-pull-up: true
bias-pull-down: true
drive-strength:
description:
typical current when output high level.
enum: [ 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 17, 18, 20, 21, 23,
24 ]
required:
- pinmux
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0)
pinctrl@4170000 {
compatible = "cix,sky1-pinctrl";
reg = <0x4170000 0x1000>;
wifi_vbat_gpio: wifi-vbat-gpio-cfg {
pins {
pinmux = <CIX_PAD_GPIO012_FUNC_GPIO012>;
bias-pull-up;
drive-strength = <8>;
};
};
};
Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
-195
View File
@@ -1,195 +0,0 @@
* Marvell Armada 37xx SoC pin and gpio controller
Each Armada 37xx SoC come with two pin and gpio controller one for the
south bridge and the other for the north bridge.
Inside this set of register the gpio latch allows exposing some
configuration of the SoC and especially the clock frequency of the
xtal. Hence, this node is a represent as syscon allowing sharing the
register between multiple hardware block.
GPIO and pin controller:
------------------------
Main node:
Refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning
of the phrase "pin configuration node".
Required properties for pinctrl driver:
- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
for the south bridge
"marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
for the north bridge
- reg: The first set of register are for pinctrl/gpio and the second
set for the interrupt controller
- interrupts: list of the interrupt use by the gpio
Available groups and functions for the North bridge:
group: jtag
- pins 20-24
- functions jtag, gpio
group sdio0
- pins 8-10
- functions sdio, gpio
group emmc_nb
- pins 27-35
- functions emmc, gpio
group pwm0
- pin 11 (GPIO1-11)
- functions pwm, led, gpio
group pwm1
- pin 12
- functions pwm, led, gpio
group pwm2
- pin 13
- functions pwm, led, gpio
group pwm3
- pin 14
- functions pwm, led, gpio
group pmic1
- pin 7
- functions pmic, gpio
group pmic0
- pin 6
- functions pmic, gpio
group i2c2
- pins 2-3
- functions i2c, gpio
group i2c1
- pins 0-1
- functions i2c, gpio
group spi_cs1
- pin 17
- functions spi, gpio
group spi_cs2
- pin 18
- functions spi, gpio
group spi_cs3
- pin 19
- functions spi, gpio
group onewire
- pin 4
- functions onewire, gpio
group uart1
- pins 25-26
- functions uart, gpio
group spi_quad
- pins 15-16
- functions spi, gpio
group uart2
- pins 9-10 and 18-19
- functions uart, gpio
Available groups and functions for the South bridge:
group usb32_drvvbus0
- pin 36
- functions drvbus, gpio
group usb2_drvvbus1
- pin 37
- functions drvbus, gpio
group sdio_sb
- pins 60-65
- functions sdio, gpio
group rgmii
- pins 42-53
- functions mii, gpio
group pcie1
- pins 39
- functions pcie, gpio
group pcie1_clkreq
- pins 40
- functions pcie, gpio
group pcie1_wakeup
- pins 41
- functions pcie, gpio
group smi
- pins 54-55
- functions smi, gpio
group ptp
- pins 56
- functions ptp, gpio
group ptp_clk
- pin 57
- functions ptp, mii
group ptp_trig
- pin 58
- functions ptp, mii
group mii_col
- pin 59
- functions mii, mii_err
GPIO subnode:
Please refer to gpio.txt in this directory for details of gpio-ranges property
and the common GPIO bindings used by client devices.
Required properties for gpio driver under the gpio subnode:
- interrupts: List of interrupt specifier for the controllers interrupt.
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the
second cell specifies GPIO flags, as defined in
<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
GPIO_ACTIVE_LOW flags are supported.
- gpio-ranges: Range of pins managed by the GPIO controller.
Xtal Clock bindings for Marvell Armada 37xx SoCs
------------------------------------------------
see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
Example:
pinctrl_sb: pinctrl-sb@18800 {
compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
reg = <0x18800 0x100>, <0x18C00 0x20>;
gpio {
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sb 0 0 29>;
gpio-controller;
interrupts =
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
};
rgmii_pins: mii-pins {
groups = "rgmii";
function = "mii";
};
};
Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml
+124
View File
@@ -0,0 +1,124 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/marvell,armada3710-xb-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 37xx SoC pin and gpio controller
maintainers:
- Gregory CLEMENT <gregory.clement@bootlin.com>
- Marek Behún <kabel@kernel.org>
- Miquel Raynal <miquel.raynal@bootlin.com>
description: >
Each Armada 37xx SoC come with two pin and gpio controller one for the south
bridge and the other for the north bridge.
Inside this set of register the gpio latch allows exposing some configuration
of the SoC and especially the clock frequency of the xtal. Hence, this node is
a represent as syscon allowing sharing the register between multiple hardware
block.
properties:
compatible:
items:
- enum:
- marvell,armada3710-sb-pinctrl
- marvell,armada3710-nb-pinctrl
- const: syscon
- const: simple-mfd
reg:
items:
- description: pinctrl and GPIO controller registers
- description: interrupt controller registers
gpio:
description: GPIO controller subnode
type: object
additionalProperties: false
properties:
'#gpio-cells':
const: 2
gpio-controller: true
gpio-ranges:
description: Range of pins managed by the GPIO controller
'#interrupt-cells':
const: 2
interrupt-controller: true
interrupts:
description: List of interrupt specifiers for the GPIO controller
required:
- '#gpio-cells'
- gpio-ranges
- gpio-controller
- '#interrupt-cells'
- interrupt-controller
- interrupts
xtal-clk:
type: object
additionalProperties: false
properties:
compatible:
const: marvell,armada-3700-xtal-clock
'#clock-cells':
const: 0
clock-output-names: true
patternProperties:
'-pins$':
$ref: pinmux-node.yaml#
additionalProperties: false
properties:
groups:
enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,
pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi,
spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
usb2_drvvbus1, usb32_drvvbus ]
function:
enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire,
pcie, pmic, ptp, pwm, sdio, smi, spi, uart ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl_sb: pinctrl@18800 {
compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
reg = <0x18800 0x100>, <0x18C00 0x20>;
gpio {
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sb 0 0 29>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts =
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
};
};
Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml
+86
View File
@@ -0,0 +1,86 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/marvell,berlin2-soc-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Berlin pin-controller driver
maintainers:
- Antoine Tenart <atenart@kernel.org>
- Jisheng Zhang <jszhang@kernel.org>
description: >
Pin control registers are part of both chip controller and system controller
register sets. Pin controller nodes should be a sub-node of either the chip
controller or system controller node. The pins controlled are organized in
groups, so no actual pin information is needed.
A pin-controller node should contain subnodes representing the pin group
configurations, one per function. Each subnode has the group name and the
muxing function used.
Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is
called a 'function' in the pin-controller subsystem.
properties:
compatible:
items:
- enum:
- marvell,berlin2-soc-pinctrl
- marvell,berlin2-system-pinctrl
- marvell,berlin2cd-soc-pinctrl
- marvell,berlin2cd-system-pinctrl
- marvell,berlin2q-soc-pinctrl
- marvell,berlin2q-system-pinctrl
- marvell,berlin4ct-avio-pinctrl
- marvell,berlin4ct-soc-pinctrl
- marvell,berlin4ct-system-pinctrl
- syna,as370-soc-pinctrl
reg:
maxItems: 1
additionalProperties:
description: Pin group configuration subnodes.
type: object
$ref: /schemas/pinctrl/pinmux-node.yaml#
additionalProperties: false
properties:
groups:
description: List of pin group names.
$ref: /schemas/types.yaml#/definitions/string-array
function:
description: Function used to mux the group.
$ref: /schemas/types.yaml#/definitions/string
required:
- groups
- function
allOf:
- if:
properties:
compatible:
contains:
enum:
- marvell,berlin4ct-avio-pinctrl
- marvell,berlin4ct-soc-pinctrl
- marvell,berlin4ct-system-pinctrl
- syna,as370-soc-pinctrl
then:
required:
- reg
examples:
- |
pinctrl {
compatible = "marvell,berlin2q-system-pinctrl";
uart0-pmux {
groups = "GSM12";
function = "uart0";
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml
+211
View File
@@ -0,0 +1,211 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT6878 Pin Controller
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- Igor Belwon <igor.belwon@mentallysanemainliners.org>
description:
The MediaTek MT6878 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt6878-pinctrl
reg:
items:
- description: pin controller base
- description: bl group IO
- description: bm group IO
- description: br group IO
- description: bl1 group IO
- description: br1 group IO
- description: lm group IO
- description: lt group IO
- description: rm group IO
- description: rt group IO
- description: EINT controller E block
- description: EINT controller S block
- description: EINT controller W block
- description: EINT controller C block
reg-names:
items:
- const: base
- const: bl
- const: bm
- const: br
- const: bl1
- const: br1
- const: lm
- const: lt
- const: rm
- const: rt
- const: eint-e
- const: eint-s
- const: eint-w
- const: eint-c
gpio-controller: true
'#gpio-cells':
description:
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
the amount of cells must be specified as 2. See the below mentioned gpio
binding representation for description of particular cells.
const: 2
gpio-ranges:
maxItems: 1
gpio-line-names:
maxItems: 216
interrupts:
description: The interrupt outputs to sysirq
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
# PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'^pins':
type: object
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
description:
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
properties:
pinmux:
description:
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux are defined as macros in
arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
drive-strength-microamp:
enum: [125, 250, 500, 1000]
bias-pull-down:
oneOf:
- type: boolean
- enum: [75000, 5000]
description: Pull down RSEL type resistance values (in ohms)
description:
For normal pull down type there is no need to specify a resistance
value, hence this can be specified as a boolean property.
For RSEL pull down type a resistance value (in ohms) can be added.
bias-pull-up:
oneOf:
- type: boolean
- enum: [10000, 5000, 4000, 3000]
description: Pull up RSEL type resistance values (in ohms)
description:
For normal pull up type there is no need to specify a resistance
value, hence this can be specified as a boolean property.
For RSEL pull up type a resistance value (in ohms) can be added.
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1)
#define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
pio: pinctrl@10005000 {
compatible = "mediatek,mt6878-pinctrl";
reg = <0x10005000 0x1000>,
<0x11d10000 0x1000>,
<0x11d30000 0x1000>,
<0x11d40000 0x1000>,
<0x11d50000 0x1000>,
<0x11d60000 0x1000>,
<0x11e20000 0x1000>,
<0x11e30000 0x1000>,
<0x11eb0000 0x1000>,
<0x11ec0000 0x1000>,
<0x11ce0000 0x1000>,
<0x11de0000 0x1000>,
<0x11e60000 0x1000>,
<0x1c01e000 0x1000>;
reg-names = "base", "bl", "bm", "br", "bl1", "br1",
"lm", "lt", "rm", "rt", "eint-e", "eint-s",
"eint-w", "eint-c";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 220>;
interrupt-controller;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
gpio-pins {
pins {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
bias-pull-up = <4000>;
drive-strength = <6>;
};
};
i2c0-pins {
pins-bus {
pinmux = <PINMUX_GPIO99__FUNC_SCL0>,
<PINMUX_GPIO100__FUNC_SDA0>;
bias-pull-down = <75000>;
drive-strength-microamp = <1000>;
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml
+5
View File
@@ -61,6 +61,11 @@ required:
- "#gpio-cells"
patternProperties:
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog
'-pins$':
type: object
additionalProperties: false
Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
+89
View File
@@ -0,0 +1,89 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PolarFire SoC iomux0
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
description:
iomux0 is responsible for routing some functions to either the FPGA fabric,
or to MSSIOs. It only performs muxing, and has no IO configuration role, as
fabric IOs are configured separately and just routing a function to MSSIOs is
not sufficient for it to actually get mapped to an MSSIO, just makes it
possible.
properties:
compatible:
oneOf:
- const: microchip,mpfs-pinctrl-iomux0
- items:
- const: microchip,pic64gx-pinctrl-iomux0
- const: microchip,mpfs-pinctrl-iomux0
reg:
maxItems: 1
pinctrl-use-default: true
patternProperties:
'^mux-':
type: object
$ref: pinmux-node.yaml
additionalProperties: false
properties:
function:
description:
A string containing the name of the function to mux to the group.
enum: [ spi0, spi1, i2c0, i2c1, can0, can1, qspi, uart0, uart1, uart2,
uart3, uart4, mdio0, mdio1 ]
groups:
description:
An array of strings. Each string contains the name of a group.
items:
enum: [ spi0_fabric, spi0_mssio, spi1_fabric, spi1_mssio, i2c0_fabric,
i2c0_mssio, i2c1_fabric, i2c1_mssio, can0_fabric, can0_mssio,
can1_fabric, can1_mssio, qspi_fabric, qspi_mssio,
uart0_fabric, uart0_mssio, uart1_fabric, uart1_mssio,
uart2_fabric, uart2_mssio, uart3_fabric, uart3_mssio,
uart4_fabric, uart4_mssio, mdio0_fabric, mdio0_mssio,
mdio1_fabric, mdio1_mssio ]
required:
- function
- groups
required:
- compatible
- reg
additionalProperties: false
examples:
- |
soc {
#size-cells = <1>;
#address-cells = <1>;
pinctrl@200 {
compatible = "microchip,mpfs-pinctrl-iomux0";
reg = <0x200 0x4>;
mux-spi0-fabric {
function = "spi0";
groups = "spi0_fabric";
};
mux-spi1-mssio {
function = "spi1";
groups = "spi1_mssio";
};
};
};
...
Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml
+74
View File
@@ -0,0 +1,74 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PIC64GX GPIO2 Mux
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
description:
The "GPIO2 Mux" determines whether GPIO2 or select other functions are
available on package pins on PIC64GX. Some of these functions must be
mapped to this mux via iomux0 for settings here to have any impact.
properties:
compatible:
const: microchip,pic64gx-pinctrl-gpio2
reg:
maxItems: 1
pinctrl-use-default: true
patternProperties:
'^mux-':
type: object
$ref: pinmux-node.yaml
additionalProperties: false
properties:
function:
description:
A string containing the name of the function to mux to the group.
enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2, gpio ]
groups:
description:
An array of strings. Each string contains the name of a group.
items:
enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2,
gpio_mdio0, gpio_mdio1, gpio_spi0, gpio_can0, gpio_pcie,
gpio_qspi, gpio_uart3, gpio_uart4, gpio_can1, gpio_uart2 ]
required:
- function
- groups
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@41000000 {
compatible = "microchip,pic64gx-pinctrl-gpio2";
reg = <0x41000000 0x4>;
pinctrl-use-default;
pinctrl-names = "default";
pinctrl-0 = <&mdio0_gpio2>, <&mdio1_gpio2>, <&spi0_gpio2>, <&qspi_gpio2>,
<&uart3_gpio2>, <&uart4_gpio2>, <&can1_gpio2>, <&can0_gpio2>,
<&uart2_gpio2>;
mux-gpio2 {
function = "gpio";
groups = "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie",
"gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1";
};
};
...
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
+17
View File
@@ -153,4 +153,21 @@ properties:
pin. Typically indicates how many double-inverters are
used to delay the signal.
skew-delay-input-ps:
description:
this affects the expected clock skew in ps on an input pin.
skew-delay-output-ps:
description:
this affects the expected delay in ps before latching a value to
an output pin.
if:
required:
- skew-delay
then:
properties:
skew-delay-input-ps: false
skew-delay-output-ps: false
additionalProperties: true
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
+1
View File
@@ -24,6 +24,7 @@ properties:
- items:
- enum:
- ti,am437-padconf
- ti,am62l-padconf
- ti,am654-padconf
- ti,dra7-padconf
- ti,omap2420-padconf
Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml
+127
View File
@@ -0,0 +1,127 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,kaanapali-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Kaanapali TLMM block
maintainers:
- Jingyi Wang <jingyi.wang@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Kaanapali SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,kaanapali-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 109
gpio-line-names:
maxItems: 217
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-kaanapali-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-kaanapali-tlmm-state"
additionalProperties: false
$defs:
qcom-kaanapali-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-6])$"
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
audio_ext_mclk1, audio_ref_clk, cam_asc_mclk2, cam_asc_mclk4,
cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer,
cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx,
coex_uart2_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail,
ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, ddr_pxi2,
ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0,
gnss_adc1, i2chub0_se0, i2chub0_se1, i2chub0_se2, i2chub0_se3,
i2chub0_se4, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist,
mdp_esync0_out, mdp_esync1_out, mdp_vsync, mdp_vsync0_out,
mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3,
pcie0_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
qdss_gpio_traceclk, qdss_gpio_tracectl, qdss_gpio_tracedata,
qlink_big_enable, qlink_big_request, qlink_little_enable,
qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3,
qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,
qup2_se2, qup2_se3, qup2_se4, qup3_se0, qup3_se1, qup3_se2,
qup3_se3, qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2,
qup4_se3, qup4_se4, sd_write_protect, sdc40, sdc41, sdc42, sdc43,
sdc4_clk, sdc4_cmd, sys_throttle, tb_trig_sdc2, tb_trig_sdc4,
tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1,
tsense_pwm2, tsense_pwm3, tsense_pwm4, tsense_pwm5, tsense_pwm6,
tsense_pwm7, uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1,
vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f100000 {
compatible = "qcom,kaanapali-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 218>;
interrupt-controller;
#interrupt-cells = <2>;
qup-uart7-state {
pins = "gpio62", "gpio63";
function = "qup1_se7";
};
};
...
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml
+2 -2
View File
@@ -107,12 +107,12 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
msmgpio: pinctrl@800000 {
tlmm: pinctrl@800000 {
compatible = "qcom,msm8960-pinctrl";
reg = <0x800000 0x4000>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&msmgpio 0 0 152>;
gpio-ranges = <&tlmm 0 0 152>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
+15
View File
@@ -59,7 +59,11 @@ properties:
- qcom,pmc8180-gpio
- qcom,pmc8180c-gpio
- qcom,pmc8380-gpio
- qcom,pmcx0102-gpio
- qcom,pmd8028-gpio
- qcom,pmh0101-gpio
- qcom,pmh0104-gpio
- qcom,pmh0110-gpio
- qcom,pmi632-gpio
- qcom,pmi8950-gpio
- qcom,pmi8994-gpio
@@ -68,6 +72,7 @@ properties:
- qcom,pmiv0104-gpio
- qcom,pmk8350-gpio
- qcom,pmk8550-gpio
- qcom,pmk8850-gpio
- qcom,pmm8155au-gpio
- qcom,pmm8654au-gpio
- qcom,pmp8074-gpio
@@ -191,6 +196,8 @@ allOf:
- qcom,pm8950-gpio
- qcom,pm8953-gpio
- qcom,pmi632-gpio
- qcom,pmh0104-gpio
- qcom,pmk8850-gpio
then:
properties:
gpio-line-names:
@@ -303,6 +310,8 @@ allOf:
compatible:
contains:
enum:
- qcom,pmcx0102-gpio
- qcom,pmh0110-gpio
- qcom,pmi8998-gpio
then:
properties:
@@ -318,6 +327,7 @@ allOf:
compatible:
contains:
enum:
- qcom,pmh0101-gpio
- qcom,pmih0108-gpio
then:
properties:
@@ -481,13 +491,18 @@ $defs:
- gpio1-gpio22 for pm8994
- gpio1-gpio26 for pm8998
- gpio1-gpio22 for pma8084
- gpio1-gpio14 for pmcx0102
- gpio1-gpio4 for pmd8028
- gpio1-gpio18 for pmh0101
- gpio1-gpio8 for pmh0104
- gpio1-gpio14 for pmh0110
- gpio1-gpio8 for pmi632
- gpio1-gpio2 for pmi8950
- gpio1-gpio10 for pmi8994
- gpio1-gpio18 for pmih0108
- gpio1-gpio4 for pmk8350
- gpio1-gpio6 for pmk8550
- gpio1-gpio8 for pmk8850
- gpio1-gpio10 for pmm8155au
- gpio1-gpio12 for pmm8654au
- gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12)
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml
+7 -1
View File
@@ -16,7 +16,13 @@ description:
properties:
compatible:
const: qcom,sm6115-lpass-lpi-pinctrl
oneOf:
- enum:
- qcom,sm6115-lpass-lpi-pinctrl
- items:
- enum:
- qcom,qcm2290-lpass-lpi-pinctrl
- const: qcom,sm6115-lpass-lpi-pinctrl
reg:
items:
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+1
View File
@@ -44,6 +44,7 @@ properties:
- rockchip,rk3328-pinctrl
- rockchip,rk3368-pinctrl
- rockchip,rk3399-pinctrl
- rockchip,rk3506-pinctrl
- rockchip,rk3528-pinctrl
- rockchip,rk3562-pinctrl
- rockchip,rk3568-pinctrl
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+1
View File
@@ -41,6 +41,7 @@ properties:
- samsung,exynos7870-wakeup-eint
- samsung,exynos7885-wakeup-eint
- samsung,exynos850-wakeup-eint
- samsung,exynos8890-wakeup-eint
- samsung,exynos8895-wakeup-eint
- const: samsung,exynos7-wakeup-eint
- items:
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+5 -1
View File
@@ -36,6 +36,7 @@ properties:
compatible:
enum:
- axis,artpec8-pinctrl
- axis,artpec9-pinctrl
- google,gs101-pinctrl
- samsung,s3c64xx-pinctrl
- samsung,s5pv210-pinctrl
@@ -52,6 +53,7 @@ properties:
- samsung,exynos7870-pinctrl
- samsung,exynos7885-pinctrl
- samsung,exynos850-pinctrl
- samsung,exynos8890-pinctrl
- samsung,exynos8895-pinctrl
- samsung,exynos9810-pinctrl
- samsung,exynos990-pinctrl
@@ -133,7 +135,9 @@ allOf:
properties:
compatible:
contains:
const: google,gs101-pinctrl
enum:
- google,gs101-pinctrl
- samsung,exynos8890-pinctrl
then:
required:
- clocks
Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt
-83
View File
@@ -1,83 +0,0 @@
* Spreadtrum Pin Controller
The Spreadtrum pin controller are organized in 3 blocks (types).
The first block comprises some global control registers, and each
register contains several bit fields with one bit or several bits
to configure for some global common configuration, such as domain
pad driving level, system control select and so on ("domain pad
driving level": One pin can output 3.0v or 1.8v, depending on the
related domain pad driving selection, if the related domain pad
select 3.0v, then the pin can output 3.0v. "system control" is used
to choose one function (like: UART0) for which system, since we
have several systems (AP/CP/CM4) on one SoC.).
There are too much various configuration that we can not list all
of them, so we can not make every Spreadtrum-special configuration
as one generic configuration, and maybe it will add more strange
global configuration in future. Then we add one "sprd,control" to
set these various global control configuration, and we need use
magic number for this property.
Moreover we recognise every fields comprising one bit or several
bits in one global control register as one pin, thus we should
record every pin's bit offset, bit width and register offset to
configure this field (pin).
The second block comprises some common registers which have unified
register definition, and each register described one pin is used
to configure the pin sleep mode, function select and sleep related
configuration.
Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
related configuration are:
- input-enable
- input-disable
- output-high
- output-low
- bias-pull-up
- bias-pull-down
In some situation we need set the pin sleep mode and pin sleep related
configuration, to set the pin sleep related configuration automatically
by hardware when the system specified by sleep mode goes into deep
sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP
and set the pin sleep related configuration as "input-enable", which
means when PUBCP system goes into deep sleep mode, this pin will be set
input enable automatically.
Moreover we can not use the "sleep" state, since some systems (like:
PUBCP system) do not run linux kernel OS (only AP system run linux
kernel on SC9860 platform), then we can not select "sleep" state
when the PUBCP system goes into deep sleep mode. Thus we introduce
"sprd,sleep-mode" property to set pin sleep mode.
The last block comprises some misc registers which also have unified
register definition, and each register described one pin is used to
configure drive strength, pull up/down and so on. Especially for pull
up, we have two kind pull up resistor: 20K and 4.7K.
Required properties for Spreadtrum pin controller:
- compatible: "sprd,<soc>-pinctrl"
Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported SoCs.
- reg: The register address of pin controller device.
- pins : An array of pin names.
Optional properties:
- function: Specified the function name.
- drive-strength: Drive strength in mA.
- input-schmitt-disable: Enable schmitt-trigger mode.
- input-schmitt-enable: Disable schmitt-trigger mode.
- bias-disable: Disable pin bias.
- bias-pull-down: Pull down on pin.
- bias-pull-up: Pull up on pin.
- input-enable: Enable pin input.
- input-disable: Enable pin output.
- output-high: Set the pin as an output level high.
- output-low: Set the pin as an output level low.
- sleep-hardware-state: Indicate these configs in this state are sleep related.
- sprd,control: Control values referring to databook for global control pins.
- sprd,sleep-mode: Sleep mode selection.
Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported values.
Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt
-70
View File
@@ -1,70 +0,0 @@
* Spreadtrum SC9860 Pin Controller
Please refer to sprd,pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: Must be "sprd,sc9860-pinctrl".
- reg: The register address of pin controller device.
- pins : An array of strings, each string containing the name of a pin.
Optional properties:
- function: A string containing the name of the function, values must be
one of: "func1", "func2", "func3" and "func4".
- drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
12, 14, 16, 20, 21, 24, 25, 27, 29, 31 and 33.
- input-schmitt-disable: Enable schmitt-trigger mode.
- input-schmitt-enable: Disable schmitt-trigger mode.
- bias-disable: Disable pin bias.
- bias-pull-down: Pull down on pin.
- bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
is 20K and 4700 for pull-up resistor is 4.7K.
- input-enable: Enable pin input.
- input-disable: Enable pin output.
- output-high: Set the pin as an output level high.
- output-low: Set the pin as an output level low.
- sleep-hardware-state: Indicate these configs in this state are sleep related.
- sprd,control: Control values referring to databook for global control pins.
- sprd,sleep-mode: Choose the pin sleep mode, and supported values are:
AP_SLEEP, PUBCP_SLEEP, TGLDSP_SLEEP and AGDSP_SLEEP.
Pin sleep mode definition:
enum pin_sleep_mode {
AP_SLEEP = BIT(0),
PUBCP_SLEEP = BIT(1),
TGLDSP_SLEEP = BIT(2),
AGDSP_SLEEP = BIT(3),
};
Example:
pin_controller: pinctrl@402a0000 {
compatible = "sprd,sc9860-pinctrl";
reg = <0x402a0000 0x10000>;
grp1: sd0 {
pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE";
sprd,control = <0x1>;
};
grp2: rfctl_33 {
pins = "SC9860_RFCTL33";
function = "func2";
sprd,sleep-mode = <AP_SLEEP | PUBCP_SLEEP>;
grp2_sleep_mode: rfctl_33_sleep {
pins = "SC9860_RFCTL33";
sleep-hardware-state;
output-low;
}
};
grp3: rfctl_misc_20 {
pins = "SC9860_RFCTL20_MISC";
drive-strength = <10>;
bias-pull-up = <4700>;
grp3_sleep_mode: rfctl_misc_sleep {
pins = "SC9860_RFCTL20_MISC";
sleep-hardware-state;
bias-pull-up;
}
};
};
Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.yaml
+199
View File
@@ -0,0 +1,199 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/sprd,sc9860-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Spreadtrum SC9860 Pin Controller
maintainers:
- Baolin Wang <baolin.wang@linux.alibaba.com>
description: >
The Spreadtrum pin controller are organized in 3 blocks (types).
The first block comprises some global control registers, and each
register contains several bit fields with one bit or several bits
to configure for some global common configuration, such as domain
pad driving level, system control select and so on ("domain pad
driving level": One pin can output 3.0v or 1.8v, depending on the
related domain pad driving selection, if the related domain pad
select 3.0v, then the pin can output 3.0v. "system control" is used
to choose one function (like: UART0) for which system, since we
have several systems (AP/CP/CM4) on one SoC.).
There are too much various configuration that we can not list all
of them, so we can not make every Spreadtrum-special configuration
as one generic configuration, and maybe it will add more strange
global configuration in future. Then we add one "sprd,control" to
set these various global control configuration, and we need use
magic number for this property.
Moreover we recognize every fields comprising one bit or several
bits in one global control register as one pin, thus we should
record every pin's bit offset, bit width and register offset to
configure this field (pin).
The second block comprises some common registers which have unified
register definition, and each register described one pin is used
to configure the pin sleep mode, function select and sleep related
configuration.
Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
related configuration are:
- input-enable
- input-disable
- output-high
- output-low
- bias-pull-up
- bias-pull-down
In some situation we need set the pin sleep mode and pin sleep related
configuration, to set the pin sleep related configuration automatically
by hardware when the system specified by sleep mode goes into deep
sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP
and set the pin sleep related configuration as "input-enable", which
means when PUBCP system goes into deep sleep mode, this pin will be set
input enable automatically.
Moreover we can not use the "sleep" state, since some systems (like:
PUBCP system) do not run linux kernel OS (only AP system run linux
kernel on SC9860 platform), then we can not select "sleep" state
when the PUBCP system goes into deep sleep mode. Thus we introduce
"sprd,sleep-mode" property to set pin sleep mode.
The last block comprises some misc registers which also have unified
register definition, and each register described one pin is used to
configure drive strength, pull up/down and so on. Especially for pull
up, we have two kind pull up resistor: 20K and 4.7K.
properties:
compatible:
const: sprd,sc9860-pinctrl
reg:
maxItems: 1
additionalProperties:
$ref: '#/$defs/pin-node'
unevaluatedProperties: false
properties:
function:
description: Function to assign to the pins.
enum:
- func1
- func2
- func3
- func4
drive-strength:
description: Drive strength in mA.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4, 6, 8, 10, 12, 14, 16, 20, 21, 24, 25, 27, 29, 31, 33]
input-schmitt-disable: true
input-schmitt-enable: true
bias-pull-up:
enum: [20000, 4700]
sprd,sleep-mode:
description: Pin sleep mode selection.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 0x1f
sprd,control:
description: Control values referring to databook for global control pins.
$ref: /schemas/types.yaml#/definitions/uint32
patternProperties:
'sleep$':
$ref: '#/$defs/pin-node'
unevaluatedProperties: false
properties:
bias-pull-up:
type: boolean
sleep-hardware-state:
description: Indicate these configs in sleep related state.
type: boolean
$defs:
pin-node:
type: object
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml#
- $ref: /schemas/pinctrl/pinmux-node.yaml#
properties:
pins:
description: Names of pins to configure.
$ref: /schemas/types.yaml#/definitions/string-array
bias-disable:
description: Disable pin bias.
type: boolean
bias-pull-down:
description: Pull down on pin.
type: boolean
bias-pull-up: true
input-enable:
description: Enable pin input.
type: boolean
input-disable:
description: Enable pin output.
type: boolean
output-high:
description: Set the pin as an output level high.
type: boolean
output-low:
description: Set the pin as an output level low.
type: boolean
required:
- compatible
- reg
examples:
- |
pin_controller: pinctrl@402a0000 {
compatible = "sprd,sc9860-pinctrl";
reg = <0x402a0000 0x10000>;
grp1: sd0 {
pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE";
sprd,control = <0x1>;
};
grp2: rfctl_33 {
pins = "SC9860_RFCTL33";
function = "func2";
sprd,sleep-mode = <3>;
grp2_sleep_mode: rfctl_33_sleep {
pins = "SC9860_RFCTL33";
sleep-hardware-state;
output-low;
};
};
grp3: rfctl_misc_20 {
pins = "SC9860_RFCTL20_MISC";
drive-strength = <10>;
bias-pull-up = <4700>;
grp3_sleep_mode: rfctl_misc_sleep {
pins = "SC9860_RFCTL20_MISC";
sleep-hardware-state;
bias-pull-up;
};
};
};
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+85 -16
View File
@@ -151,6 +151,8 @@ patternProperties:
pinctrl group available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive, output high/low and output speed.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pinmux:
$ref: /schemas/types.yaml#/definitions/uint32-array
@@ -195,26 +197,19 @@ patternProperties:
pinmux = <STM32_PINMUX('A', 9, RSVD)>;
};
bias-disable:
type: boolean
bias-disable: true
bias-pull-down:
type: boolean
bias-pull-down: true
bias-pull-up:
type: boolean
bias-pull-up: true
drive-push-pull:
type: boolean
drive-push-pull: true
drive-open-drain:
type: boolean
drive-open-drain: true
output-low:
type: boolean
output-low: true
output-high:
type: boolean
output-high: true
slew-rate:
description: |
@@ -222,15 +217,68 @@ patternProperties:
1: Medium speed
2: Fast speed
3: High speed
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
minimum: 0
maximum: 3
skew-delay-input-ps:
description: |
IO synchronization skew rate applied to the input path
enum: [0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250]
skew-delay-output-ps:
description: |
IO synchronization latch delay applied to the output path
enum: [0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250]
st,io-sync:
$ref: /schemas/types.yaml#/definitions/string
enum:
- pass-through
- clock inverted
- data on rising edge
- data on falling edge
- data on both edges
description: |
IO synchronization through re-sampling or inversion
"pass-through" - data or clock GPIO pass-through
"clock inverted" - clock GPIO inverted
"data on rising edge" - data GPIO re-sampled on clock rising edge
"data on falling edge" - data GPIO re-sampled on clock falling edge
"data on both edges" - data GPIO re-sampled on both clock edges
default: pass-through
required:
- pinmux
# Not allowed both skew-delay-input-ps and skew-delay-output-ps
if:
required:
- skew-delay-input-ps
then:
properties:
skew-delay-output-ps: false
allOf:
- $ref: pinctrl.yaml#
- if:
not:
properties:
compatible:
contains:
enum:
- st,stm32mp257-pinctrl
- st,stm32mp257-z-pinctrl
then:
patternProperties:
'-[0-9]*$':
patternProperties:
'^pins':
properties:
skew-delay-input-ps: false
skew-delay-output-ps: false
st,io-sync: false
required:
- compatible
- '#address-cells'
@@ -311,4 +359,25 @@ examples:
pinctrl-names = "default";
};
- |
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
//Example 4 skew-delay and st,io-sync
pinctrl: pinctrl@44240000 {
compatible = "st,stm32mp257-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44240000 0xa0400>;
eth3_rgmii_pins_a: eth3-rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 6, AF14)>;
st,io-sync = "data on both edges";
};
pins2 {
pinmux = <STM32_PINMUX('H', 2, AF14)>;
skew-delay-output-ps = <500>;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
-1
View File
@@ -42,7 +42,6 @@ patternProperties:
function:
description:
Function to mux.
$ref: /schemas/types.yaml#/definitions/string
enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8,
spi0, spi1, spi2, spi3, spi4, spi5, spi6,
uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in]
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
+12 -1
View File
@@ -18,10 +18,17 @@ properties:
items:
- const: microchip,mpfs-mss-top-sysreg
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
'#reset-cells':
description:
The AHB/AXI peripherals on the PolarFire SoC have reset support, so
@@ -31,6 +38,10 @@ properties:
of PolarFire clock/reset IDs.
const: 1
pinctrl@200:
type: object
$ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
required:
- compatible
- reg
@@ -40,7 +51,7 @@ additionalProperties: false
examples:
- |
syscon@20002000 {
compatible = "microchip,mpfs-mss-top-sysreg", "syscon";
compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
reg = <0x20002000 0x1000>;
#reset-cells = <1>;
};
MAINTAINERS
+34 -30
View File
@@ -195,7 +195,7 @@ F: drivers/pinctrl/pinctrl-upboard.c
F: include/linux/mfd/upboard-fpga.h
AB8500 BATTERY AND CHARGER DRIVERS
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
F: Documentation/devicetree/bindings/power/supply/*ab8500*
F: drivers/power/supply/*ab8500*
@@ -2070,7 +2070,7 @@ F: Documentation/devicetree/bindings/display/arm,hdlcd.yaml
F: drivers/gpu/drm/arm/hdlcd_*
ARM INTEGRATOR, VERSATILE AND REALVIEW SUPPORT
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/arm,integrator.yaml
@@ -2243,7 +2243,7 @@ F: Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml
F: drivers/memory/pl353-smc.c
ARM PRIMECELL SSP PL022 SPI DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/spi/spi-pl022.yaml
@@ -2256,7 +2256,7 @@ F: drivers/tty/serial/amba-pl01*.c
F: include/linux/amba/serial.h
ARM PRIMECELL VIC PL190/PL192 DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml
@@ -2573,7 +2573,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/bitmain.yaml
F: Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt
F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.yaml
F: arch/arm64/boot/dts/bitmain/
F: drivers/clk/clk-bm1880.c
F: drivers/pinctrl/pinctrl-bm1880.c
@@ -2685,7 +2685,7 @@ F: tools/perf/util/cs-etm.*
ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
M: Hans Ulli Kroll <ulli.kroll@googlemail.com>
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git https://github.com/ulli-kroll/linux.git
@@ -3087,7 +3087,7 @@ F: include/dt-bindings/clock/mstar-*
F: include/dt-bindings/gpio/msc313-gpio.h
ARM/NOMADIK/Ux500 ARCHITECTURES
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
@@ -3793,7 +3793,7 @@ F: Documentation/devicetree/bindings/media/i2c/asahi-kasei,ak7375.yaml
F: drivers/media/i2c/ak7375.c
ASAHI KASEI AK8974 DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-iio@vger.kernel.org
S: Supported
W: http://www.akm.com/
@@ -6853,7 +6853,7 @@ S: Maintained
F: drivers/pinctrl/pinctrl-cy8c95x0.c
CYPRESS CY8CTMA140 TOUCHSCREEN DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-input@vger.kernel.org
S: Maintained
F: drivers/input/touchscreen/cy8ctma140.c
@@ -6873,13 +6873,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/
F: drivers/media/common/cypress_firmware*
CYTTSP TOUCHSCREEN DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-input@vger.kernel.org
S: Maintained
F: drivers/input/touchscreen/cyttsp*
D-LINK DIR-685 TOUCHKEYS DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-input@vger.kernel.org
S: Supported
F: drivers/input/keyboard/dlink-dir685-touchkeys.c
@@ -7742,13 +7742,13 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/gpu/drm/tiny/appletbdrm.c
DRM DRIVER FOR ARM PL111 CLCD
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/gpu/drm/pl111/
DRM DRIVER FOR ARM VERSATILE TFT PANELS
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.yaml
@@ -7798,7 +7798,7 @@ F: Documentation/devicetree/bindings/display/panel/ebbg,ft8719.yaml
F: drivers/gpu/drm/panel/panel-ebbg-ft8719.c
DRM DRIVER FOR FARADAY TVE200 TV ENCODER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/gpu/drm/tve200/
@@ -7994,14 +7994,14 @@ F: include/dt-bindings/clock/qcom,dsi-phy-28nm.h
F: include/uapi/drm/msm_drm.h
DRM DRIVER FOR NOVATEK NT35510 PANELS
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml
F: drivers/gpu/drm/panel/panel-novatek-nt35510.c
DRM DRIVER FOR NOVATEK NT35560 PANELS
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml
@@ -8119,7 +8119,7 @@ F: Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml
F: drivers/gpu/drm/panel/panel-raydium-rm67191.c
DRM DRIVER FOR SAMSUNG DB7430 PANELS
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/panel/samsung,lms397kf04.yaml
@@ -8216,7 +8216,7 @@ F: Documentation/devicetree/bindings/display/solomon,ssd13*.yaml
F: drivers/gpu/drm/solomon/ssd130x*
DRM DRIVER FOR ST-ERICSSON MCDE
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/ste,mcde.yaml
@@ -8248,7 +8248,7 @@ F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml
F: drivers/gpu/drm/bridge/ti-sn65dsi86.c
DRM DRIVER FOR TPO TPG110 PANELS
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml
@@ -8292,7 +8292,7 @@ F: drivers/gpu/drm/vmwgfx/
F: include/uapi/drm/vmwgfx_drm.h
DRM DRIVER FOR WIDECHIPS WS2401 PANELS
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/panel/samsung,lms380kf01.yaml
@@ -9590,7 +9590,7 @@ F: include/linux/fanotify.h
F: include/uapi/linux/fanotify.h
FARADAY FOTG210 USB2 DUAL-ROLE CONTROLLER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-usb@vger.kernel.org
S: Maintained
F: drivers/usb/fotg210/
@@ -10780,7 +10780,7 @@ F: drivers/gpio/gpio-sloppy-logic-analyzer.c
F: tools/gpio/gpio-sloppy-logic-analyzer.sh
GPIO SUBSYSTEM
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
M: Bartosz Golaszewski <brgl@kernel.org>
L: linux-gpio@vger.kernel.org
S: Maintained
@@ -13182,7 +13182,7 @@ F: Documentation/devicetree/bindings/iio/imu/invensense,icm45600.yaml
F: drivers/iio/imu/inv_icm45600/
INVENSENSE MPU-3050 GYROSCOPE DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-iio@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.yaml
@@ -14112,7 +14112,7 @@ F: drivers/auxdisplay/ks0108.c
F: include/linux/ks0108.h
KTD253 BACKLIGHT DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
F: Documentation/devicetree/bindings/leds/backlight/kinetic,ktd253.yaml
F: drivers/video/backlight/ktd253-backlight.c
@@ -14324,7 +14324,7 @@ F: drivers/ata/pata_arasan_cf.c
F: include/linux/pata_arasan_cf_data.h
LIBATA PATA FARADAY FTIDE010 AND GEMINI SATA BRIDGE DRIVERS
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-ide@vger.kernel.org
S: Maintained
F: drivers/ata/pata_ftide010.c
@@ -19946,7 +19946,7 @@ F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
F: drivers/pci/controller/dwc/*imx6*
PCI DRIVER FOR INTEL IXP4XX
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
S: Maintained
F: Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml
F: drivers/pci/controller/pci-ixp4xx.c
@@ -20057,7 +20057,7 @@ F: drivers/pci/controller/cadence/pci-j721e.c
F: drivers/pci/controller/dwc/pci-dra7xx.c
PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml
@@ -20513,7 +20513,7 @@ K: (?i)clone3
K: \b(clone_args|kernel_clone_args)\b
PIN CONTROL SUBSYSTEM
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-gpio@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
@@ -21940,7 +21940,7 @@ F: Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml
F: drivers/watchdog/realtek_otto_wdt.c
REALTEK RTL83xx SMI DSA ROUTER CHIPS
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
M: Alvin Šipraga <alsi@bang-olufsen.dk>
S: Maintained
F: Documentation/devicetree/bindings/net/dsa/realtek.yaml
@@ -22434,6 +22434,8 @@ F: Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml
F: Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
F: Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml
F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
F: Documentation/devicetree/bindings/riscv/microchip.yaml
F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -22447,6 +22449,8 @@ F: drivers/gpio/gpio-mpfs.c
F: drivers/i2c/busses/i2c-microchip-corei2c.c
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/pci/controller/plda/pcie-microchip-host.c
F: drivers/pinctrl/pinctrl-mpfs-iomux0.c
F: drivers/pinctrl/pinctrl-pic64gx-gpio2.c
F: drivers/pwm/pwm-microchip-core.c
F: drivers/reset/reset-mpfs.c
F: drivers/rtc/rtc-mpfs.c
@@ -23761,7 +23765,7 @@ S: Supported
F: net/smc/
SHARP GP2AP002A00F/GP2AP002S00F SENSOR DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
L: linux-iio@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git
drivers/pinctrl/Kconfig
+19
View File
@@ -486,6 +486,15 @@ config PINCTRL_PIC32MZDA
def_bool y if PIC32MZDA
select PINCTRL_PIC32
config PINCTRL_PIC64GX
bool "pic64gx gpio2 pinctrl driver"
depends on ARCH_MICROCHIP || COMPILE_TEST
depends on OF
select GENERIC_PINCONF
default y
help
This selects the pinctrl driver for gpio2 on pic64gx.
config PINCTRL_PISTACHIO
bool "IMG Pistachio SoC pinctrl driver"
depends on OF && (MIPS || COMPILE_TEST)
@@ -497,6 +506,15 @@ config PINCTRL_PISTACHIO
help
This support pinctrl and GPIO driver for IMG Pistachio SoC.
config PINCTRL_POLARFIRE_SOC
bool "Polarfire SoC pinctrl driver"
depends on ARCH_MICROCHIP || COMPILE_TEST
depends on OF
select GENERIC_PINCONF
default y
help
This selects the pinctrl driver for Microchip Polarfire SoC.
config PINCTRL_RK805
tristate "Pinctrl and GPIO driver for RK805 PMIC"
depends on MFD_RK8XX
@@ -686,6 +704,7 @@ source "drivers/pinctrl/aspeed/Kconfig"
source "drivers/pinctrl/bcm/Kconfig"
source "drivers/pinctrl/berlin/Kconfig"
source "drivers/pinctrl/cirrus/Kconfig"
source "drivers/pinctrl/cix/Kconfig"
source "drivers/pinctrl/freescale/Kconfig"
source "drivers/pinctrl/intel/Kconfig"
source "drivers/pinctrl/mediatek/Kconfig"
drivers/pinctrl/Makefile
+3
View File
@@ -48,7 +48,9 @@ obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PEF2256) += pinctrl-pef2256.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PIC64GX) += pinctrl-pic64gx-gpio2.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) += pinctrl-mpfs-iomux0.o
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RP1) += pinctrl-rp1.o
@@ -69,6 +71,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-y += bcm/
obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
obj-y += cirrus/
obj-y += cix/
obj-y += freescale/
obj-$(CONFIG_X86) += intel/
obj-y += mediatek/
drivers/pinctrl/cix/Kconfig
+15
View File
@@ -0,0 +1,15 @@
# SPDX-License-Identifier: GPL-2.0-only
config PINCTRL_SKY1_BASE
tristate
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select REGMAP
config PINCTRL_SKY1
tristate "Cix Sky1 pinctrl driver"
depends on ARCH_CIX || COMPILE_TEST
depends on HAS_IOMEM
select PINCTRL_SKY1_BASE
help
Say Y here to enable the sky1 pinctrl driver
drivers/pinctrl/cix/Makefile
+4
View File
@@ -0,0 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
# Cix Sky1 pin control drivers
obj-$(CONFIG_PINCTRL_SKY1_BASE) += pinctrl-sky1-base.o
obj-$(CONFIG_PINCTRL_SKY1) += pinctrl-sky1.o
drivers/pinctrl/cix/pinctrl-sky1-base.c
+587
View File
@@ -0,0 +1,587 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Author: Jerry Zhu <Jerry.Zhu@cixtech.com>
// Author: Gary Yang <gary.yang@cixtech.com>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
#include "../pinmux.h"
#include "pinctrl-sky1.h"
#define SKY1_PIN_SIZE (4)
#define SKY1_MUX_MASK GENMASK(8, 7)
#define SKY1_MUX_SHIFT (7)
#define SKY1_PULLCONF_MASK GENMASK(6, 5)
#define SKY1_PULLUP_BIT (6)
#define SKY1_PULLDN_BIT (5)
#define SKY1_DS_MASK GENMASK(3, 0)
#define CIX_PIN_NO_SHIFT (8)
#define CIX_PIN_FUN_MASK GENMASK(1, 0)
#define CIX_GET_PIN_NO(x) ((x) >> CIX_PIN_NO_SHIFT)
#define CIX_GET_PIN_FUNC(x) ((x) & CIX_PIN_FUN_MASK)
#define SKY1_DEFAULT_DS_VAL (4)
static const char * const sky1_gpio_functions[] = {
"func0", "func1", "func2", "func3",
};
static unsigned char sky1_ds_table[] = {
2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 17, 18, 20, 21, 23, 24,
};
static bool sky1_pctrl_is_function_valid(struct sky1_pinctrl *spctl,
u32 pin_num, u32 fnum)
{
int i;
for (i = 0; i < spctl->info->npins; i++) {
const struct sky1_pin_desc *pin = spctl->info->pins + i;
if (pin->pin.number == pin_num) {
if (fnum < pin->nfunc)
return true;
break;
}
}
return false;
}
static int sky1_pctrl_dt_node_to_map_func(struct sky1_pinctrl *spctl,
u32 pin, u32 fnum, struct sky1_pinctrl_group *grp,
struct pinctrl_map **map, unsigned int *reserved_maps,
unsigned int *num_maps)
{
bool ret;
if (*num_maps == *reserved_maps)
return -ENOSPC;
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.group = grp->name;
ret = sky1_pctrl_is_function_valid(spctl, pin, fnum);
if (!ret) {
dev_err(spctl->dev, "invalid function %d on pin %d .\n",
fnum, pin);
return -EINVAL;
}
(*map)[*num_maps].data.mux.function = sky1_gpio_functions[fnum];
(*num_maps)++;
return 0;
}
static struct sky1_pinctrl_group *
sky1_pctrl_find_group_by_pin(struct sky1_pinctrl *spctl, u32 pin)
{
int i;
for (i = 0; i < spctl->info->npins; i++) {
struct sky1_pinctrl_group *grp =
(struct sky1_pinctrl_group *)spctl->groups + i;
if (grp->pin == pin)
return grp;
}
return NULL;
}
static int sky1_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *node,
struct pinctrl_map **map,
unsigned int *reserved_maps,
unsigned int *num_maps)
{
struct property *pins;
u32 pinfunc, pin, func;
int num_pins, num_funcs, maps_per_pin;
unsigned long *configs;
unsigned int num_configs;
bool has_config = false;
int i, err;
unsigned int reserve = 0;
struct sky1_pinctrl_group *grp;
struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
pins = of_find_property(node, "pinmux", NULL);
if (!pins) {
dev_err(spctl->dev, "missing pins property in node %pOFn .\n",
node);
return -EINVAL;
}
err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
&num_configs);
if (err)
return err;
if (num_configs)
has_config = true;
num_pins = pins->length / sizeof(u32);
num_funcs = num_pins;
maps_per_pin = 0;
if (num_funcs)
maps_per_pin++;
if (has_config && num_pins >= 1)
maps_per_pin++;
if (!num_pins || !maps_per_pin) {
err = -EINVAL;
goto exit;
}
reserve = num_pins * maps_per_pin;
err = pinctrl_utils_reserve_map(pctldev, map,
reserved_maps, num_maps, reserve);
if (err < 0)
goto exit;
for (i = 0; i < num_pins; i++) {
err = of_property_read_u32_index(node, "pinmux",
i, &pinfunc);
if (err)
goto exit;
pin = CIX_GET_PIN_NO(pinfunc);
func = CIX_GET_PIN_FUNC(pinfunc);
pctldev->num_functions = ARRAY_SIZE(sky1_gpio_functions);
if (pin >= pctldev->desc->npins ||
func >= pctldev->num_functions) {
dev_err(spctl->dev, "invalid pins value.\n");
err = -EINVAL;
goto exit;
}
grp = sky1_pctrl_find_group_by_pin(spctl, pin);
if (!grp) {
dev_err(spctl->dev, "unable to match pin %d to group\n",
pin);
err = -EINVAL;
goto exit;
}
err = sky1_pctrl_dt_node_to_map_func(spctl, pin, func, grp,
map, reserved_maps, num_maps);
if (err < 0)
goto exit;
if (has_config) {
err = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps, num_maps, grp->name,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (err < 0)
goto exit;
}
}
err = 0;
exit:
kfree(configs);
return err;
}
static int sky1_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map, unsigned int *num_maps)
{
unsigned int reserved_maps;
int ret;
*map = NULL;
*num_maps = 0;
reserved_maps = 0;
for_each_child_of_node_scoped(np_config, np) {
ret = sky1_pctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
return ret;
}
}
return 0;
}
static void sky1_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map,
unsigned int num_maps)
{
kfree(map);
}
static int sky1_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
return spctl->info->npins;
}
static const char *sky1_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
return spctl->groups[group].name;
}
static int sky1_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
*pins = (unsigned int *)&spctl->groups[group].pin;
*num_pins = 1;
return 0;
}
static void sky1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int offset)
{
seq_printf(s, "%s", dev_name(pctldev->dev));
}
static const struct pinctrl_ops sky1_pctrl_ops = {
.dt_node_to_map = sky1_pctrl_dt_node_to_map,
.dt_free_map = sky1_dt_free_map,
.get_groups_count = sky1_pctrl_get_groups_count,
.get_group_name = sky1_pctrl_get_group_name,
.get_group_pins = sky1_pctrl_get_group_pins,
.pin_dbg_show = sky1_pin_dbg_show,
};
static int sky1_pmx_set_one_pin(struct sky1_pinctrl *spctl,
unsigned int pin, unsigned char muxval)
{
u32 reg_val;
void __iomem *pin_reg;
pin_reg = spctl->base + pin * SKY1_PIN_SIZE;
reg_val = readl(pin_reg);
reg_val &= ~SKY1_MUX_MASK;
reg_val |= muxval << SKY1_MUX_SHIFT;
writel(reg_val, pin_reg);
dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n",
pin * SKY1_PIN_SIZE, reg_val);
return 0;
}
static int sky1_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
bool ret;
struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
struct sky1_pinctrl_group *g =
(struct sky1_pinctrl_group *)spctl->groups + group;
ret = sky1_pctrl_is_function_valid(spctl, g->pin, function);
if (!ret) {
dev_err(spctl->dev, "invalid function %d on group %d .\n",
function, group);
return -EINVAL;
}
sky1_pmx_set_one_pin(spctl, g->pin, function);
return 0;
}
static int sky1_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(sky1_gpio_functions);
}
static const char *sky1_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return sky1_gpio_functions[selector];
}
static int sky1_pmx_get_func_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char * const **groups,
unsigned int * const num_groups)
{
struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
const struct sky1_pinctrl_soc_info *info = spctl->info;
*groups = spctl->grp_names;
*num_groups = info->npins;
return 0;
}
static const struct pinmux_ops sky1_pmx_ops = {
.get_functions_count = sky1_pmx_get_funcs_cnt,
.get_function_groups = sky1_pmx_get_func_groups,
.get_function_name = sky1_pmx_get_func_name,
.set_mux = sky1_pmx_set_mux,
};
static int sky1_pconf_set_pull_select(struct sky1_pinctrl *spctl,
unsigned int pin, bool enable, bool isup)
{
u32 reg_val, reg_pullsel = 0;
void __iomem *pin_reg;
pin_reg = spctl->base + pin * SKY1_PIN_SIZE;
reg_val = readl(pin_reg);
reg_val &= ~SKY1_PULLCONF_MASK;
if (!enable)
goto update;
if (isup)
reg_pullsel = BIT(SKY1_PULLUP_BIT);
else
reg_pullsel = BIT(SKY1_PULLDN_BIT);
update:
reg_val |= reg_pullsel;
writel(reg_val, pin_reg);
dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n",
pin * SKY1_PIN_SIZE, reg_val);
return 0;
}
static int sky1_ds_to_index(unsigned char driving)
{
int i;
for (i = 0; i < sizeof(sky1_ds_table); i++)
if (driving == sky1_ds_table[i])
return i;
return SKY1_DEFAULT_DS_VAL;
}
static int sky1_pconf_set_driving(struct sky1_pinctrl *spctl,
unsigned int pin, unsigned char driving)
{
unsigned int reg_val, val;
void __iomem *pin_reg;
if (pin >= spctl->info->npins)
return -EINVAL;
pin_reg = spctl->base + pin * SKY1_PIN_SIZE;
reg_val = readl(pin_reg);
reg_val &= ~SKY1_DS_MASK;
val = sky1_ds_to_index(driving);
reg_val |= (val & SKY1_DS_MASK);
writel(reg_val, pin_reg);
dev_dbg(spctl->dev, "write: offset 0x%x val 0x%x\n",
pin * SKY1_PIN_SIZE, reg_val);
return 0;
}
static int sky1_pconf_parse_conf(struct pinctrl_dev *pctldev,
unsigned int pin, enum pin_config_param param,
enum pin_config_param arg)
{
int ret = 0;
struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = sky1_pconf_set_pull_select(spctl, pin, false, false);
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = sky1_pconf_set_pull_select(spctl, pin, true, true);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = sky1_pconf_set_pull_select(spctl, pin, true, false);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = sky1_pconf_set_driving(spctl, pin, arg);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int sky1_pconf_group_get(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *config)
{
struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
struct sky1_pinctrl_group *g = &spctl->groups[group];
*config = g->config;
return 0;
}
static int sky1_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int group,
unsigned long *configs, unsigned int num_configs)
{
struct sky1_pinctrl *spctl = pinctrl_dev_get_drvdata(pctldev);
struct sky1_pinctrl_group *g = &spctl->groups[group];
int i, ret;
for (i = 0; i < num_configs; i++) {
ret = sky1_pconf_parse_conf(pctldev, g->pin,
pinconf_to_config_param(configs[i]),
pinconf_to_config_argument(configs[i]));
if (ret < 0)
return ret;
g->config = configs[i];
}
return 0;
}
static const struct pinconf_ops sky1_pinconf_ops = {
.pin_config_group_get = sky1_pconf_group_get,
.pin_config_group_set = sky1_pconf_group_set,
};
static int sky1_pctrl_build_state(struct platform_device *pdev)
{
struct sky1_pinctrl *spctl = platform_get_drvdata(pdev);
const struct sky1_pinctrl_soc_info *info = spctl->info;
int i;
/* Allocate groups */
spctl->groups = devm_kcalloc(&pdev->dev, info->npins,
sizeof(*spctl->groups), GFP_KERNEL);
if (!spctl->groups)
return -ENOMEM;
/* We assume that one pin is one group, use pin name as group name. */
spctl->grp_names = devm_kcalloc(&pdev->dev, info->npins,
sizeof(*spctl->grp_names), GFP_KERNEL);
if (!spctl->grp_names)
return -ENOMEM;
for (i = 0; i < info->npins; i++) {
const struct sky1_pin_desc *pin = spctl->info->pins + i;
struct sky1_pinctrl_group *group =
(struct sky1_pinctrl_group *)spctl->groups + i;
group->name = pin->pin.name;
group->pin = pin->pin.number;
spctl->grp_names[i] = pin->pin.name;
}
return 0;
}
int sky1_base_pinctrl_probe(struct platform_device *pdev,
const struct sky1_pinctrl_soc_info *info)
{
struct pinctrl_desc *sky1_pinctrl_desc;
struct sky1_pinctrl *spctl;
struct pinctrl_pin_desc *pins;
int ret, i;
if (!info || !info->pins || !info->npins) {
dev_err(&pdev->dev, "wrong pinctrl info\n");
return -EINVAL;
}
/* Create state holders etc for this driver */
spctl = devm_kzalloc(&pdev->dev, sizeof(*spctl), GFP_KERNEL);
if (!spctl)
return -ENOMEM;
spctl->info = info;
platform_set_drvdata(pdev, spctl);
spctl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(spctl->base))
return PTR_ERR(spctl->base);
sky1_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*sky1_pinctrl_desc),
GFP_KERNEL);
if (!sky1_pinctrl_desc)
return -ENOMEM;
pins = devm_kcalloc(&pdev->dev, info->npins, sizeof(*pins),
GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < info->npins; i++)
pins[i] = info->pins[i].pin;
ret = sky1_pctrl_build_state(pdev);
if (ret)
return ret;
sky1_pinctrl_desc->name = dev_name(&pdev->dev);
sky1_pinctrl_desc->pins = pins;
sky1_pinctrl_desc->npins = info->npins;
sky1_pinctrl_desc->pctlops = &sky1_pctrl_ops;
sky1_pinctrl_desc->pmxops = &sky1_pmx_ops;
sky1_pinctrl_desc->confops = &sky1_pinconf_ops;
sky1_pinctrl_desc->owner = THIS_MODULE;
spctl->dev = &pdev->dev;
ret = devm_pinctrl_register_and_init(&pdev->dev,
sky1_pinctrl_desc, spctl,
&spctl->pctl);
if (ret) {
dev_err(&pdev->dev, "could not register SKY1 pinctrl driver\n");
return ret;
}
/*
* The SKY1 SoC has two pin controllers: one for normal working state
* and one for sleep state. Since one controller only has working
* states and the other only sleep states, it will seem to the
* controller is always in the first configured state, so no
* transitions between default->sleep->default are detected and no
* new pin states are applied when we go in and out of sleep state.
*
* To counter this, provide dummies, so that the sleep-only pin
* controller still get some default states, and the working state pin
* controller get some sleep states, so that state transitions occur
* and we re-configure pins for default and sleep states.
*/
pinctrl_provide_dummies();
dev_dbg(&pdev->dev, "initialized SKY1 pinctrl driver\n");
return pinctrl_enable(spctl->pctl);
}
EXPORT_SYMBOL_GPL(sky1_base_pinctrl_probe);
MODULE_AUTHOR("Jerry Zhu <Jerry.Zhu@cixtech.com>");
MODULE_DESCRIPTION("Cix SKy1 pinctrl base driver");
MODULE_LICENSE("GPL");
drivers/pinctrl/cix/pinctrl-sky1.c
+559
View File
@@ -0,0 +1,559 @@
// SPDX-License-Identifier: GPL-2.0
//
// Author: Jerry Zhu <Jerry.Zhu@cixtech.com>
// Author: Gary Yang <gary.yang@cixtech.com>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "linux/stddef.h"
#include "../core.h"
#include "pinctrl-sky1.h"
/* Pad names for the s5 domain pinmux subsystem */
static const char * const gpio1_group[] = {"GPIO1"};
static const char * const gpio2_group[] = {"GPIO2"};
static const char * const gpio3_group[] = {"GPIO3"};
static const char * const gpio4_group[] = {"GPIO4"};
static const char * const gpio5_group[] = {"GPIO5"};
static const char * const gpio6_group[] = {"GPIO6"};
static const char * const gpio7_group[] = {"GPIO7"};
static const char * const gpio8_group[] = {"GPIO8"};
static const char * const gpio9_group[] = {"GPIO9"};
static const char * const gpio10_group[] = {"GPIO10"};
static const char * const gpio11_group[] = {"GPIO11"};
static const char * const gpio12_group[] = {"GPIO12"};
static const char * const gpio13_group[] = {"GPIO13"};
static const char * const gpio14_group[] = {"GPIO14"};
static const char * const rsmrst_group[] = { };
static const char * const srst_group[] = { };
static const char * const slp_s3_group[] = { };
static const char * const slp_s5_group[] = { };
static const char * const pwrgd_group[] = { };
static const char * const pwrok_group[] = { };
static const char * const pwrbtn_group[] = { };
static const char * const ddrio_gate_group[] = { };
static const char * const jtag_gpio_group[] = { };
static const char * const jtag_tck_group[] = { };
static const char * const jtag_tdi_group[] = { };
static const char * const jtag_tdo_group[] = { };
static const char * const tms_group[] = { };
static const char * const trsl_group[] = { };
static const char * const sfi_i2c0_scl_group[] = {"SFI_I2C0_SCL",
"SFI_I3C0_SCL"};
static const char * const sfi_i2c0_sda_group[] = {"SFI_I2C0_SDA",
"SFI_I3C0_SDA"};
static const char * const sfi_i2c1_scl_group[] = {"SFI_I2C1_SCL",
"SFI_I3C1_SCL", "SFI_SPI_CS0"};
static const char * const sfi_i2c1_sda_group[] = {"SFI_I2C1_SDA",
"SFI_I3C1_SDA", "SFI_SPI_CS1"};
static const char * const sfi_gpio0_group[] = {"GPIO15", "SFI_SPI_SCK",
"SFI_GPIO0"};
static const char * const sfi_gpio1_group[] = {"GPIO16", "SFI_SPI_MOSI",
"SFI_GPIO1"};
static const char * const sfi_gpio2_group[] = {"GPIO17", "SFI_SPI_MISO",
"SFI_GPIO2"};
static const char * const gpio18_group[] = {"SFI_GPIO3", "GPIO18"};
static const char * const gpio19_group[] = {"SFI_GPIO4", "GPIO19"};
static const char * const gpio20_group[] = {"SFI_GPIO5", "GPIO20"};
static const char * const gpio21_group[] = {"SFI_GPIO6", "GPIO21"};
static const char * const gpio22_group[] = {"SFI_GPIO7", "GPIO22"};
static const char * const gpio23_group[] = {"SFI_GPIO8", "GPIO23",
"SFI_I3C0_PUR_EN_L"};
static const char * const gpio24_group[] = {"SFI_GPIO9", "GPIO24",
"SFI_I3C1_PUR_EN_L"};
static const char * const spi1_miso_group[] = {"SPI1_MISO", "GPIO25"};
static const char * const spi1_cs0_group[] = {"SPI1_CS0", "GPIO26"};
static const char * const spi1_cs1_group[] = {"SPI1_CS1", "GPIO27"};
static const char * const spi1_mosi_group[] = {"SPI1_MOSI", "GPIO28"};
static const char * const spi1_clk_group[] = {"SPI1_CLK", "GPIO29"};
static const char * const gpio30_group[] = {"GPIO30", "USB_0C0_L"};
static const char * const gpio31_group[] = {"GPIO31", "USB_0C1_L"};
static const char * const gpio32_group[] = {"GPIO32", "USB_0C2_L"};
static const char * const gpio33_group[] = {"GPIO33", "USB_0C3_L"};
static const char * const gpio34_group[] = {"GPIO34", "USB_0C4_L"};
static const char * const gpio35_group[] = {"GPIO35", "USB_0C5_L"};
static const char * const gpio36_group[] = {"GPIO36", "USB_0C6_L"};
static const char * const gpio37_group[] = {"GPIO37", "USB_0C7_L"};
static const char * const gpio38_group[] = {"GPIO38", "USB_0C8_L"};
static const char * const gpio39_group[] = {"GPIO39", "USB_0C9_L"};
static const char * const gpio40_group[] = {"GPIO40", "USB_DRIVE_VBUS0"};
static const char * const gpio41_group[] = {"GPIO41", "USB_DRIVE_VBUS4"};
static const char * const gpio42_group[] = {"GPIO42", "USB_DRIVE_VBUS5"};
static const char * const se_qspi_clk_group[] = {"SE_QSPI_CLK", "QSPI_CLK"};
static const char * const se_qspi_cs_group[] = {"SE_QSPI_CS_L", "QSPI_CS_L"};
static const char * const se_qspi_data0_group[] = {"SE_QSPI_DATA0",
"QSPI_DATA0"};
static const char * const se_qspi_data1_group[] = {"SE_QSPI_DATA1",
"QSPI_DATA1"};
static const char * const se_qspi_data2_group[] = {"SE_QSPI_DATA2",
"QSPI_DATA2"};
static const char * const se_qspi_data3_group[] = {"SE_QSPI_DATA3",
"QSPI_DATA3"};
static const struct sky1_pin_desc sky1_pinctrl_s5_pads[] = {
SKY_PINFUNCTION(PINCTRL_PIN(0, "GPIO1"), gpio1),
SKY_PINFUNCTION(PINCTRL_PIN(1, "GPIO2"), gpio2),
SKY_PINFUNCTION(PINCTRL_PIN(2, "GPIO3"), gpio3),
SKY_PINFUNCTION(PINCTRL_PIN(3, "GPIO4"), gpio4),
SKY_PINFUNCTION(PINCTRL_PIN(4, "GPIO5"), gpio5),
SKY_PINFUNCTION(PINCTRL_PIN(5, "GPIO6"), gpio6),
SKY_PINFUNCTION(PINCTRL_PIN(6, "GPIO7"), gpio7),
SKY_PINFUNCTION(PINCTRL_PIN(7, "GPIO8"), gpio8),
SKY_PINFUNCTION(PINCTRL_PIN(8, "GPIO9"), gpio9),
SKY_PINFUNCTION(PINCTRL_PIN(9, "GPIO10"), gpio10),
SKY_PINFUNCTION(PINCTRL_PIN(10, "GPIO11"), gpio11),
SKY_PINFUNCTION(PINCTRL_PIN(11, "GPIO12"), gpio12),
SKY_PINFUNCTION(PINCTRL_PIN(12, "GPIO13"), gpio13),
SKY_PINFUNCTION(PINCTRL_PIN(13, "GPIO14"), gpio14),
SKY_PINFUNCTION(PINCTRL_PIN(14, "RSMRST_L"), rsmrst),
SKY_PINFUNCTION(PINCTRL_PIN(15, "SRST_L"), srst),
SKY_PINFUNCTION(PINCTRL_PIN(16, "SLP_S3_L"), slp_s3),
SKY_PINFUNCTION(PINCTRL_PIN(17, "SLP_S5_L"), slp_s5),
SKY_PINFUNCTION(PINCTRL_PIN(18, "PWRGD"), pwrgd),
SKY_PINFUNCTION(PINCTRL_PIN(19, "PWROK"), pwrok),
SKY_PINFUNCTION(PINCTRL_PIN(20, "PWRBTN_L"), pwrbtn),
SKY_PINFUNCTION(PINCTRL_PIN(21, "VDD_DDRIO_GATE"), ddrio_gate),
SKY_PINFUNCTION(PINCTRL_PIN(22, "JTAG_GPIO_L"), jtag_gpio),
SKY_PINFUNCTION(PINCTRL_PIN(23, "JTAG_TCK"), jtag_tck),
SKY_PINFUNCTION(PINCTRL_PIN(24, "JTAG_TDI"), jtag_tdi),
SKY_PINFUNCTION(PINCTRL_PIN(25, "JTAG_TDO"), jtag_tdo),
SKY_PINFUNCTION(PINCTRL_PIN(26, "TMS"), tms),
SKY_PINFUNCTION(PINCTRL_PIN(27, "TRSL_L"), trsl),
SKY_PINFUNCTION(PINCTRL_PIN(28, "SFI_I2C0_SCL"), sfi_i2c0_scl),
SKY_PINFUNCTION(PINCTRL_PIN(29, "SFI_I2C0_SDA"), sfi_i2c0_sda),
SKY_PINFUNCTION(PINCTRL_PIN(30, "SFI_I2C1_SCL"), sfi_i2c1_scl),
SKY_PINFUNCTION(PINCTRL_PIN(31, "SFI_I2C1_SDA"), sfi_i2c1_sda),
SKY_PINFUNCTION(PINCTRL_PIN(32, "SFI_GPIO0"), sfi_gpio0),
SKY_PINFUNCTION(PINCTRL_PIN(33, "SFI_GPIO1"), sfi_gpio1),
SKY_PINFUNCTION(PINCTRL_PIN(34, "SFI_GPIO2"), sfi_gpio2),
SKY_PINFUNCTION(PINCTRL_PIN(35, "GPIO18"), gpio18),
SKY_PINFUNCTION(PINCTRL_PIN(36, "GPIO19"), gpio19),
SKY_PINFUNCTION(PINCTRL_PIN(37, "GPIO20"), gpio20),
SKY_PINFUNCTION(PINCTRL_PIN(38, "GPIO21"), gpio21),
SKY_PINFUNCTION(PINCTRL_PIN(39, "GPIO22"), gpio22),
SKY_PINFUNCTION(PINCTRL_PIN(40, "GPIO23"), gpio23),
SKY_PINFUNCTION(PINCTRL_PIN(41, "GPIO24"), gpio24),
SKY_PINFUNCTION(PINCTRL_PIN(42, "SPI1_MISO"), spi1_miso),
SKY_PINFUNCTION(PINCTRL_PIN(43, "SPI1_CS0"), spi1_cs0),
SKY_PINFUNCTION(PINCTRL_PIN(44, "SPI1_CS1"), spi1_cs1),
SKY_PINFUNCTION(PINCTRL_PIN(45, "SPI1_MOSI"), spi1_mosi),
SKY_PINFUNCTION(PINCTRL_PIN(46, "SPI1_CLK"), spi1_clk),
SKY_PINFUNCTION(PINCTRL_PIN(47, "GPIO30"), gpio30),
SKY_PINFUNCTION(PINCTRL_PIN(48, "GPIO31"), gpio31),
SKY_PINFUNCTION(PINCTRL_PIN(49, "GPIO32"), gpio32),
SKY_PINFUNCTION(PINCTRL_PIN(50, "GPIO33"), gpio33),
SKY_PINFUNCTION(PINCTRL_PIN(51, "GPIO34"), gpio34),
SKY_PINFUNCTION(PINCTRL_PIN(52, "GPIO35"), gpio35),
SKY_PINFUNCTION(PINCTRL_PIN(53, "GPIO36"), gpio36),
SKY_PINFUNCTION(PINCTRL_PIN(54, "GPIO37"), gpio37),
SKY_PINFUNCTION(PINCTRL_PIN(55, "GPIO38"), gpio38),
SKY_PINFUNCTION(PINCTRL_PIN(56, "GPIO39"), gpio39),
SKY_PINFUNCTION(PINCTRL_PIN(57, "GPIO40"), gpio40),
SKY_PINFUNCTION(PINCTRL_PIN(58, "GPIO41"), gpio41),
SKY_PINFUNCTION(PINCTRL_PIN(59, "GPIO42"), gpio42),
SKY_PINFUNCTION(PINCTRL_PIN(60, "SE_QSPI_CLK"), se_qspi_clk),
SKY_PINFUNCTION(PINCTRL_PIN(61, "SE_QSPI_CS_L"), se_qspi_cs),
SKY_PINFUNCTION(PINCTRL_PIN(62, "SE_QSPI_DATA0"), se_qspi_data0),
SKY_PINFUNCTION(PINCTRL_PIN(63, "SE_QSPI_DATA1"), se_qspi_data1),
SKY_PINFUNCTION(PINCTRL_PIN(64, "SE_QSPI_DATA2"), se_qspi_data2),
SKY_PINFUNCTION(PINCTRL_PIN(65, "SE_QSPI_DATA3"), se_qspi_data3),
};
/* Pad names for the s0 domain pinmux subsystem */
static const char * const gpio43_group[] = {"GPIO43"};
static const char * const gpio44_group[] = {"GPIO44"};
static const char * const gpio45_group[] = {"GPIO45"};
static const char * const gpio46_group[] = {"GPIO46"};
static const char * const reset_in_group[] = { };
static const char * const plt_reset_group[] = { };
static const char * const thermtrip_group[] = { };
static const char * const prochot_group[] = { };
static const char * const pm_i2c0_clk_group[] = { };
static const char * const pm_i2c0_data_group[] = { };
static const char * const pm_i2c1_clk_group[] = { };
static const char * const pm_i2c1_data_group[] = { };
static const char * const pm_i2c2_clk_group[] = { };
static const char * const pm_i2c2_data_group[] = { };
static const char * const pm_i2c3_clk_group[] = { };
static const char * const pm_i2c3_data_group[] = { };
static const char * const strap0_group[] = { };
static const char * const strap1_group[] = { };
static const char * const dp2_digon_group[] = {"DP2_DIGON"};
static const char * const dp2_blon_group[] = {"DP2_BLON"};
static const char * const dp2_vary_bl_group[] = {"DP2_VARY_BL"};
static const char * const i2c7_scl_group[] = {"I2C7_SCL"};
static const char * const i2c7_sda_group[] = {"I2C7_SDA"};
static const char * const uart6_csu_se_txd_group[] = { };
static const char * const clk_req1_group[] = { };
static const char * const clk_req3_group[] = { };
static const char * const i2c5_scl_group[] = {"I2C5_SCL", "GPIO47"};
static const char * const i2c5_sda_group[] = {"I2C5_SDA", "GPIO48"};
static const char * const i2c6_scl_group[] = {"I2C6_SCL", "GPIO49"};
static const char * const i2c6_sda_group[] = {"I2C6_SDA", "GPIO50"};
static const char * const i2c0_scl_group[] = {"I2C0_SCL", "GPIO51"};
static const char * const i2c0_sda_group[] = {"I2C0_SDA", "GPIO52"};
static const char * const i2c1_scl_group[] = {"I2C1_SCL", "GPIO53"};
static const char * const i2c1_sda_group[] = {"I2C1_SDA", "GPIO54"};
static const char * const i2c2_scl_group[] = {"I2C2_SCL", "I3C0_SCL",
"GPIO55"};
static const char * const i2c2_sda_group[] = {"I2C2_SDA", "I3C0_SDA",
"GPIO56"};
static const char * const gpio57_group[] = {"GPIO57", "I3C0_PUR_EN_L"};
static const char * const i2c3_scl_group[] = {"I2C3_SCL", "I3C1_SCL",
"GPIO58"};
static const char * const i2c3_sda_group[] = {"I2C3_SDA", "I3C1_SDA",
"GPIO59"};
static const char * const gpio60_group[] = {"GPIO60", "I3C1_PUR_EN_L"};
static const char * const i2c4_scl_group[] = {"I2C4_SCL", "GPIO61"};
static const char * const i2c4_sda_group[] = {"I2C4_SDA", "GPIO62"};
static const char * const hda_bitclk_group[] = {"HDA_BITCLK", "I2S0_SCK",
"I2S9_RSCK_DBG"};
static const char * const hda_rst_group[] = {"HDA_RST_L", "I2S0_DATA_IN",
"I2S9_DATA_IN_DBG"};
static const char * const hda_sdin0_group[] = {"HDA_SDIN0", "I2S0_MCLK",
"I2S9_TSCK_DBG"};
static const char * const hda_sdout0_group[] = {"HDA_SDOUT0", "I2S0_DATA_OUT",
"I2S9_TWS_DBG"};
static const char * const hda_sync_group[] = {"HDA_SYNC", "I2S0_WS",
"I2S9_RWS_DBG"};
static const char * const hda_sdin1_group[] = {"HDA_SDIN1", "GPIO63",
"I2S9_DATA_IN1_DBG"};
static const char * const hda_sdout1_group[] = {"HDA_SDOUT1", "GPIO64",
"I2S9_DATA_OUT0_DBG"};
static const char * const i2s1_mclk_group[] = {"I2S1_MCLK", "GPIO65"};
static const char * const i2s1_sck_group[] = {"I2S1_SCK", "GPIO66"};
static const char * const i2s1_ws_group[] = {"I2S1_WS", "GPIO67"};
static const char * const i2s1_data_in_group[] = {"I2S1_DATA_IN", "GPIO68"};
static const char * const i2s1_data_out_group[] = {"I2S1_DATA_OUT", "GPIO69"};
static const char * const i2s2_mck_group[] = {"I2S2_MCLK", "GPIO70"};
static const char * const i2s2_rsck_group[] = {"I2S2_RSCK", "GPIO71",
"I2S5_RSCK_DBG", "I2S6_RSCK_DBG"};
static const char * const i2s2_rws_group[] = {"I2S2_RWS", "GPIO72",
"I2S5_RWS_DBG", "I2S6_RWS_DBG"};
static const char * const i2s2_tsck_group[] = {"I2S2_TSCK", "GPIO73",
"I2S5_TSCK_DBG", "I2S6_TSCK_DBG"};
static const char * const i2s2_tws_group[] = {"I2S2_TWS", "GPIO74",
"I2S5_TWS_DBG", "I2S6_TWS_DBG"};
static const char * const i2s2_data_in0_group[] = {"I2S2_DATA_IN0", "GPIO75",
"I2S5_DATA_IN0_DBG", "I2S6_DATA_IN0_DBG"};
static const char * const i2s2_data_in1_group[] = {"I2S2_DATA_IN1", "GPIO76",
"I2S5_DATA_IN1_DBG", "I2S6_DATA_IN1_DBG"};
static const char * const i2s2_data_out0_group[] = {"I2S2_DATA_OUT0", "GPIO77",
"I2S5_DATA_OUT0_DBG", "I2S6_DATA_OUT0_DBG"};
static const char * const i2s2_data_out1_group[] = {"I2S2_DATA_OUT1", "GPIO78",
"I2S5_DATA_OUT1_DBG", "I2S6_DATA_OUT1_DBG"};
static const char * const i2s2_data_out2_group[] = {"I2S2_DATA_OUT2",
"GPIO79"};
static const char * const i2s2_data_out3_group[] = {"I2S2_DATA_OUT3", "GPIO80",
"I2S9_DATA_OUT1_DBG"};
static const char * const i2s3_mclk_group[] = {"I2S3_MCLK", "GPIO81"};
static const char * const i2s3_rsck_group[] = {"I2S3_RSCK", "GPIO82",
"I2S7_RSCK_DBG", "I2S8_RSCK_DBG"};
static const char * const i2s3_rws_group[] = {"I2S3_RWS", "GPIO83",
"I2S7_RWS_DBG", "I2S8_RWS_DBG"};
static const char * const i2s3_tsck_group[] = {"I2S3_TSCK", "GPIO84",
"I2S7_TSCK_DBG", "I2S8_TSCK_DBG"};
static const char * const i2s3_tws_group[] = {"I2S3_TWS", "GPIO85",
"I2S7_TWS_DBG", "I2S8_TWS_DBG"};
static const char * const i2s3_data_in0_group[] = {"I2S3_DATA_IN0", "GPIO86",
"I2S7_DATA_IN0_DBG", "I2S8_DATA_IN0_DBG"};
static const char * const i2s3_data_in1_group[] = {"I2S3_DATA_IN1", "GPIO87",
"I2S7_DATA_IN1_DBG", "I2S8_DATA_IN1_DBG"};
static const char * const i2s3_data_out0_group[] = {"I2S3_DATA_OUT0", "GPIO88",
"I2S7_DATA_OUT0_DBG", "I2S8_DATA_OUT0_DBG"};
static const char * const i2s3_data_out1_group[] = {"I2S3_DATA_OUT1", "GPIO89",
"I2S7_DATA_OUT1_DBG", "I2S8_DATA_OUT1_DBG"};
static const char * const gpio90_group[] = {"GPIO90", "I2S4_MCLK_LB"};
static const char * const gpio91_group[] = {"GPIO91", "I2S4_SCK_LB"};
static const char * const gpio92_group[] = {"GPIO92", "I2S4_WS_LB"};
static const char * const gpio93_group[] = {"GPIO93", "I2S4_DATA_IN_LB"};
static const char * const gpio94_group[] = {"GPIO94", "I2S4_DATA_OUT_LB"};
static const char * const uart0_txd_group[] = {"UART0_TXD", "PWM0", "GPIO95"};
static const char * const uart0_rxd_group[] = {"UART0_RXD", "PWM1", "GPIO96"};
static const char * const uart0_cts_group[] = {"UART0_CTS", "FAN_OUT2",
"GPIO97"};
static const char * const uart0_rts_group[] = {"UART0_RTS", "FAN_TACH2",
"GPIO98"};
static const char * const uart1_txd_group[] = {"UART1_TXD", "FAN_OUT0",
"GPIO99"};
static const char * const uart1_rxd_group[] = {"UART1_RXD", "FAN_TACH0",
"GPIO100"};
static const char * const uart1_cts_group[] = {"UART1_CTS", "FAN_OUT1",
"GPIO101"};
static const char * const uart1_rts_group[] = {"UART1_RTS", "FAN_TACH1",
"GPIO102"};
static const char * const uart2_txd_group[] = {"UART2_TXD", "GPIO103"};
static const char * const uart2_rxd_group[] = {"UART2_RXD", "GPIO104"};
static const char * const uart3_txd_group[] = {"UART3_TXD", "GPIO105"};
static const char * const uart3_rxd_group[] = {"UART3_RXD", "GPIO106"};
static const char * const uart3_cts_group[] = {"UART3_CTS", "GPIO107",
"TRIGIN0"};
static const char * const uart3_rts_group[] = {"UART3_RTS", "GPIO108",
"TRIGIN1"};
static const char * const uart4_csu_pm_txd_group[] = {"UART4_CSU_PM_TXD",
"GPIO109"};
static const char * const uart4_csu_pm_rxd_group[] = {"UART4_CSU_PM_RXD",
"GPIO110"};
static const char * const uart5_csu_se_txd_group[] = {"UART5_CSU_SE_TXD",
"GPIO111"};
static const char * const uart5_csu_se_rxd_group[] = {"UART5_CSU_SE_RXD",
"GPIO112"};
static const char * const uart6_csu_se_rxd_group[] = {"UART6_CSU_SE_RXD",
"GPIO113"};
static const char * const clk_req0_group[] = {"CLK_REQ0_L", "GPIO114"};
static const char * const clk_req2_group[] = {"CLK_REQ2_L", "GPIO115"};
static const char * const clk_req4_group[] = {"CLK_REQ4_L", "GPIO116"};
static const char * const csi0_mclk0_group[] = {"CSI0_MCLK0", "GPIO117"};
static const char * const csi0_mclk1_group[] = {"CSI0_MCLK1", "GPIO118"};
static const char * const csi1_mclk0_group[] = {"CSI1_MCLK0", "GPIO119"};
static const char * const csi1_mclk1_group[] = {"CSI1_MCLK1", "GPIO120"};
static const char * const gpio121_group[] = {"GPIO121", "GMAC0_REFCLK_25M"};
static const char * const gpio122_group[] = {"GPIO122", "GMAC0_TX_CTL"};
static const char * const gpio123_group[] = {"GPIO123", "GMAC0_TXD0"};
static const char * const gpio124_group[] = {"GPIO124", "GMAC0_TXD1"};
static const char * const gpio125_group[] = {"GPIO125", "GMAC0_TXD2"};
static const char * const gpio126_group[] = {"GPIO126", "GMAC0_TXD3"};
static const char * const gpio127_group[] = {"GPIO127", "GMAC0_TX_CLK"};
static const char * const gpio128_group[] = {"GPIO128", "GMAC0_RX_CTL"};
static const char * const gpio129_group[] = {"GPIO129", "GMAC0_RXD0"};
static const char * const gpio130_group[] = {"GPIO130", "GMAC0_RXD1"};
static const char * const gpio131_group[] = {"GPIO131", "GMAC0_RXD2"};
static const char * const gpio132_group[] = {"GPIO132", "GMAC0_RXD3"};
static const char * const gpio133_group[] = {"GPIO133", "GMAC0_RX_CLK"};
static const char * const gpio134_group[] = {"GPIO134", "GMAC0_MDC"};
static const char * const gpio135_group[] = {"GPIO135", "GMAC0_MDIO"};
static const char * const gpio136_group[] = {"GPIO136", "GMAC1_REFCLK_25M"};
static const char * const gpio137_group[] = {"GPIO137", "GMAC1_TX_CTL"};
static const char * const gpio138_group[] = {"GPIO138", "GMAC1_TXD0",
"SPI2_MISO"};
static const char * const gpio139_group[] = {"GPIO139", "GMAC1_TXD1",
"SPI2_CS0"};
static const char * const gpio140_group[] = {"GPIO140", "GMAC1_TXD2",
"SPI2_CS1"};
static const char * const gpio141_group[] = {"GPIO141", "GMAC1_TXD3",
"SPI2_MOSI"};
static const char * const gpio142_group[] = {"GPIO142", "GMAC1_TX_CLK",
"SPI2_CLK"};
static const char * const gpio143_group[] = {"GPIO143", "GMAC1_RX_CTL"};
static const char * const gpio144_group[] = {"GPIO144", "GMAC1_RXD0"};
static const char * const gpio145_group[] = {"GPIO145", "GMAC1_RXD1"};
static const char * const gpio146_group[] = {"GPIO146", "GMAC1_RXD2"};
static const char * const gpio147_group[] = {"GPIO147", "GMAC1_RXD3"};
static const char * const gpio148_group[] = {"GPIO148", "GMAC1_RX_CLK"};
static const char * const gpio149_group[] = {"GPIO149", "GMAC1_MDC"};
static const char * const gpio150_group[] = {"GPIO150", "GMAC1_MDIO"};
static const char * const gpio151_group[] = {"GPIO151", "PM_GPIO0"};
static const char * const gpio152_group[] = {"GPIO152", "PM_GPIO1"};
static const char * const gpio153_group[] = {"GPIO153", "PM_GPIO2"};
static const struct sky1_pin_desc sky1_pinctrl_pads[] = {
SKY_PINFUNCTION(PINCTRL_PIN(0, "GPIO43"), gpio43),
SKY_PINFUNCTION(PINCTRL_PIN(1, "GPIO44"), gpio44),
SKY_PINFUNCTION(PINCTRL_PIN(2, "GPIO45"), gpio45),
SKY_PINFUNCTION(PINCTRL_PIN(3, "GPIO46"), gpio46),
SKY_PINFUNCTION(PINCTRL_PIN(4, "RESET_IN_L"), reset_in),
SKY_PINFUNCTION(PINCTRL_PIN(5, "PLT_RESET_L"), plt_reset),
SKY_PINFUNCTION(PINCTRL_PIN(6, "THERMTRIP_L"), thermtrip),
SKY_PINFUNCTION(PINCTRL_PIN(7, "PROCHOT_L"), prochot),
SKY_PINFUNCTION(PINCTRL_PIN(8, "PM_I2C0_CLK"), pm_i2c0_clk),
SKY_PINFUNCTION(PINCTRL_PIN(9, "PM_I2C0_DATA"), pm_i2c0_data),
SKY_PINFUNCTION(PINCTRL_PIN(10, "PM_I2C1_CLK"), pm_i2c1_clk),
SKY_PINFUNCTION(PINCTRL_PIN(11, "PM_I2C1_DATA"), pm_i2c1_data),
SKY_PINFUNCTION(PINCTRL_PIN(12, "PM_I2C2_CLK"), pm_i2c2_clk),
SKY_PINFUNCTION(PINCTRL_PIN(13, "PM_I2C2_DATA"), pm_i2c2_data),
SKY_PINFUNCTION(PINCTRL_PIN(14, "PM_I2C3_CLK"), pm_i2c3_clk),
SKY_PINFUNCTION(PINCTRL_PIN(15, "PM_I2C3_DATA"), pm_i2c3_data),
SKY_PINFUNCTION(PINCTRL_PIN(16, "STRAP0"), strap0),
SKY_PINFUNCTION(PINCTRL_PIN(17, "STRAP1"), strap1),
SKY_PINFUNCTION(PINCTRL_PIN(18, "DP2_DIGON"), dp2_digon),
SKY_PINFUNCTION(PINCTRL_PIN(19, "DP2_BLON"), dp2_blon),
SKY_PINFUNCTION(PINCTRL_PIN(20, "DP2_VARY_BL"), dp2_vary_bl),
SKY_PINFUNCTION(PINCTRL_PIN(21, "I2C7_SCL"), i2c7_scl),
SKY_PINFUNCTION(PINCTRL_PIN(22, "I2C7_SDA"), i2c7_sda),
SKY_PINFUNCTION(PINCTRL_PIN(23, "UART6_CSU_SE_TXD"), uart6_csu_se_txd),
SKY_PINFUNCTION(PINCTRL_PIN(24, "CLK_REQ1_L"), clk_req1),
SKY_PINFUNCTION(PINCTRL_PIN(25, "CLK_REQ3_L"), clk_req3),
SKY_PINFUNCTION(PINCTRL_PIN(26, "I2C5_SCL"), i2c5_scl),
SKY_PINFUNCTION(PINCTRL_PIN(27, "I2C5_SDA"), i2c5_sda),
SKY_PINFUNCTION(PINCTRL_PIN(28, "I2C6_SCL"), i2c6_scl),
SKY_PINFUNCTION(PINCTRL_PIN(29, "I2C6_SDA"), i2c6_sda),
SKY_PINFUNCTION(PINCTRL_PIN(30, "I2C0_CLK"), i2c0_scl),
SKY_PINFUNCTION(PINCTRL_PIN(31, "I2C0_SDA"), i2c0_sda),
SKY_PINFUNCTION(PINCTRL_PIN(32, "I2C1_CLK"), i2c1_scl),
SKY_PINFUNCTION(PINCTRL_PIN(33, "I2C1_SDA"), i2c1_sda),
SKY_PINFUNCTION(PINCTRL_PIN(34, "I2C2_SCL"), i2c2_scl),
SKY_PINFUNCTION(PINCTRL_PIN(35, "I2C2_SDA"), i2c2_sda),
SKY_PINFUNCTION(PINCTRL_PIN(36, "GPIO57"), gpio57),
SKY_PINFUNCTION(PINCTRL_PIN(37, "I2C3_SCL"), i2c3_scl),
SKY_PINFUNCTION(PINCTRL_PIN(38, "I2C3_SDA"), i2c3_sda),
SKY_PINFUNCTION(PINCTRL_PIN(39, "GPIO60"), gpio60),
SKY_PINFUNCTION(PINCTRL_PIN(40, "I2C4_SCL"), i2c4_scl),
SKY_PINFUNCTION(PINCTRL_PIN(41, "I2C4_SDA"), i2c4_sda),
SKY_PINFUNCTION(PINCTRL_PIN(42, "HDA_BITCLK"), hda_bitclk),
SKY_PINFUNCTION(PINCTRL_PIN(43, "HDA_RST_L"), hda_rst),
SKY_PINFUNCTION(PINCTRL_PIN(44, "HDA_SDIN0"), hda_sdin0),
SKY_PINFUNCTION(PINCTRL_PIN(45, "HDA_SDOUT0"), hda_sdout0),
SKY_PINFUNCTION(PINCTRL_PIN(46, "HDA_SYNC"), hda_sync),
SKY_PINFUNCTION(PINCTRL_PIN(47, "HDA_SDIN1"), hda_sdin1),
SKY_PINFUNCTION(PINCTRL_PIN(48, "HDA_SDOUT1"), hda_sdout1),
SKY_PINFUNCTION(PINCTRL_PIN(49, "I2S1_MCLK"), i2s1_mclk),
SKY_PINFUNCTION(PINCTRL_PIN(50, "I2S1_SCK"), i2s1_sck),
SKY_PINFUNCTION(PINCTRL_PIN(51, "I2S1_WS"), i2s1_ws),
SKY_PINFUNCTION(PINCTRL_PIN(52, "I2S1_DATA_IN"), i2s1_data_in),
SKY_PINFUNCTION(PINCTRL_PIN(53, "I2S1_DATA_OUT"), i2s1_data_out),
SKY_PINFUNCTION(PINCTRL_PIN(54, "I2S2_MCLK"), i2s2_mck),
SKY_PINFUNCTION(PINCTRL_PIN(55, "I2S2_RSCK"), i2s2_rsck),
SKY_PINFUNCTION(PINCTRL_PIN(56, "I2S2_RWS"), i2s2_rws),
SKY_PINFUNCTION(PINCTRL_PIN(57, "I2S2_TSCK"), i2s2_tsck),
SKY_PINFUNCTION(PINCTRL_PIN(58, "I2S2_TWS"), i2s2_tws),
SKY_PINFUNCTION(PINCTRL_PIN(59, "I2S2_DATA_IN0"), i2s2_data_in0),
SKY_PINFUNCTION(PINCTRL_PIN(60, "I2S2_DATA_IN1"), i2s2_data_in1),
SKY_PINFUNCTION(PINCTRL_PIN(61, "I2S2_DATA_OUT0"), i2s2_data_out0),
SKY_PINFUNCTION(PINCTRL_PIN(62, "I2S2_DATA_OUT1"), i2s2_data_out1),
SKY_PINFUNCTION(PINCTRL_PIN(63, "I2S2_DATA_OUT2"), i2s2_data_out2),
SKY_PINFUNCTION(PINCTRL_PIN(64, "I2S2_DATA_OUT3"), i2s2_data_out3),
SKY_PINFUNCTION(PINCTRL_PIN(65, "I2S3_MCLK"), i2s3_mclk),
SKY_PINFUNCTION(PINCTRL_PIN(66, "I2S3_RSCK"), i2s3_rsck),
SKY_PINFUNCTION(PINCTRL_PIN(67, "I2S3_RWS"), i2s3_rws),
SKY_PINFUNCTION(PINCTRL_PIN(68, "I2S3_TSCK"), i2s3_tsck),
SKY_PINFUNCTION(PINCTRL_PIN(69, "I2S3_TWS"), i2s3_tws),
SKY_PINFUNCTION(PINCTRL_PIN(70, "I2S3_DATA_IN0"), i2s3_data_in0),
SKY_PINFUNCTION(PINCTRL_PIN(71, "I2S3_DATA_IN1"), i2s3_data_in1),
SKY_PINFUNCTION(PINCTRL_PIN(72, "I2S3_DATA_OUT0"), i2s3_data_out0),
SKY_PINFUNCTION(PINCTRL_PIN(73, "I2S3_DATA_OUT1"), i2s3_data_out1),
SKY_PINFUNCTION(PINCTRL_PIN(74, "GPIO90"), gpio90),
SKY_PINFUNCTION(PINCTRL_PIN(75, "GPIO91"), gpio91),
SKY_PINFUNCTION(PINCTRL_PIN(76, "GPIO92"), gpio92),
SKY_PINFUNCTION(PINCTRL_PIN(77, "GPIO93"), gpio93),
SKY_PINFUNCTION(PINCTRL_PIN(78, "GPIO94"), gpio94),
SKY_PINFUNCTION(PINCTRL_PIN(79, "UART0_TXD"), uart0_txd),
SKY_PINFUNCTION(PINCTRL_PIN(80, "UART0_RXD"), uart0_rxd),
SKY_PINFUNCTION(PINCTRL_PIN(81, "UART0_CTS"), uart0_cts),
SKY_PINFUNCTION(PINCTRL_PIN(82, "UART0_RTS"), uart0_rts),
SKY_PINFUNCTION(PINCTRL_PIN(83, "UART1_TXD"), uart1_txd),
SKY_PINFUNCTION(PINCTRL_PIN(84, "UART1_RXD"), uart1_rxd),
SKY_PINFUNCTION(PINCTRL_PIN(85, "UART1_CTS"), uart1_cts),
SKY_PINFUNCTION(PINCTRL_PIN(86, "UART1_RTS"), uart1_rts),
SKY_PINFUNCTION(PINCTRL_PIN(87, "UART2_TXD"), uart2_txd),
SKY_PINFUNCTION(PINCTRL_PIN(88, "UART2_RXD"), uart2_rxd),
SKY_PINFUNCTION(PINCTRL_PIN(89, "UART3_TXD"), uart3_txd),
SKY_PINFUNCTION(PINCTRL_PIN(90, "UART3_RXD"), uart3_rxd),
SKY_PINFUNCTION(PINCTRL_PIN(91, "UART3_CTS"), uart3_cts),
SKY_PINFUNCTION(PINCTRL_PIN(92, "UART3_RTS"), uart3_rts),
SKY_PINFUNCTION(PINCTRL_PIN(93, "UART4_CSU_PM_TXD"), uart4_csu_pm_txd),
SKY_PINFUNCTION(PINCTRL_PIN(94, "UART4_CSU_PM_RXD"), uart4_csu_pm_rxd),
SKY_PINFUNCTION(PINCTRL_PIN(95, "UART5_CSU_SE_TXD"), uart5_csu_se_txd),
SKY_PINFUNCTION(PINCTRL_PIN(96, "UART5_CSU_SE_RXD"), uart5_csu_se_rxd),
SKY_PINFUNCTION(PINCTRL_PIN(97, "UART6_CSU_SE_RXD"), uart6_csu_se_rxd),
SKY_PINFUNCTION(PINCTRL_PIN(98, "CLK_REQ0_L"), clk_req0),
SKY_PINFUNCTION(PINCTRL_PIN(99, "CLK_REQ2_L"), clk_req2),
SKY_PINFUNCTION(PINCTRL_PIN(100, "CLK_REQ4_L"), clk_req4),
SKY_PINFUNCTION(PINCTRL_PIN(101, "CSI0_MCLK0"), csi0_mclk0),
SKY_PINFUNCTION(PINCTRL_PIN(102, "CSI0_MCLK1"), csi0_mclk1),
SKY_PINFUNCTION(PINCTRL_PIN(103, "CSI1_MCLK0"), csi1_mclk0),
SKY_PINFUNCTION(PINCTRL_PIN(104, "CSI1_MCLK1"), csi1_mclk1),
SKY_PINFUNCTION(PINCTRL_PIN(105, "GPIO121"), gpio121),
SKY_PINFUNCTION(PINCTRL_PIN(106, "GPIO122"), gpio122),
SKY_PINFUNCTION(PINCTRL_PIN(107, "GPIO123"), gpio123),
SKY_PINFUNCTION(PINCTRL_PIN(108, "GPIO124"), gpio124),
SKY_PINFUNCTION(PINCTRL_PIN(109, "GPIO125"), gpio125),
SKY_PINFUNCTION(PINCTRL_PIN(110, "GPIO126"), gpio126),
SKY_PINFUNCTION(PINCTRL_PIN(111, "GPIO127"), gpio127),
SKY_PINFUNCTION(PINCTRL_PIN(112, "GPIO128"), gpio128),
SKY_PINFUNCTION(PINCTRL_PIN(113, "GPIO129"), gpio129),
SKY_PINFUNCTION(PINCTRL_PIN(114, "GPIO130"), gpio130),
SKY_PINFUNCTION(PINCTRL_PIN(115, "GPIO131"), gpio131),
SKY_PINFUNCTION(PINCTRL_PIN(116, "GPIO132"), gpio132),
SKY_PINFUNCTION(PINCTRL_PIN(117, "GPIO133"), gpio133),
SKY_PINFUNCTION(PINCTRL_PIN(118, "GPIO134"), gpio134),
SKY_PINFUNCTION(PINCTRL_PIN(119, "GPIO135"), gpio135),
SKY_PINFUNCTION(PINCTRL_PIN(120, "GPIO136"), gpio136),
SKY_PINFUNCTION(PINCTRL_PIN(121, "GPIO137"), gpio137),
SKY_PINFUNCTION(PINCTRL_PIN(122, "GPIO138"), gpio138),
SKY_PINFUNCTION(PINCTRL_PIN(123, "GPIO139"), gpio139),
SKY_PINFUNCTION(PINCTRL_PIN(124, "GPIO140"), gpio140),
SKY_PINFUNCTION(PINCTRL_PIN(125, "GPIO141"), gpio141),
SKY_PINFUNCTION(PINCTRL_PIN(126, "GPIO142"), gpio142),
SKY_PINFUNCTION(PINCTRL_PIN(127, "GPIO143"), gpio143),
SKY_PINFUNCTION(PINCTRL_PIN(128, "GPIO144"), gpio144),
SKY_PINFUNCTION(PINCTRL_PIN(129, "GPIO145"), gpio145),
SKY_PINFUNCTION(PINCTRL_PIN(130, "GPIO146"), gpio146),
SKY_PINFUNCTION(PINCTRL_PIN(131, "GPIO147"), gpio147),
SKY_PINFUNCTION(PINCTRL_PIN(132, "GPIO148"), gpio148),
SKY_PINFUNCTION(PINCTRL_PIN(133, "GPIO149"), gpio149),
SKY_PINFUNCTION(PINCTRL_PIN(134, "GPIO150"), gpio150),
SKY_PINFUNCTION(PINCTRL_PIN(135, "GPIO151"), gpio151),
SKY_PINFUNCTION(PINCTRL_PIN(136, "GPIO152"), gpio152),
SKY_PINFUNCTION(PINCTRL_PIN(137, "GPIO153"), gpio153),
};
static const struct sky1_pinctrl_soc_info sky1_pinctrl_s5_info = {
.pins = sky1_pinctrl_s5_pads,
.npins = ARRAY_SIZE(sky1_pinctrl_s5_pads),
};
static const struct sky1_pinctrl_soc_info sky1_pinctrl_info = {
.pins = sky1_pinctrl_pads,
.npins = ARRAY_SIZE(sky1_pinctrl_pads),
};
static const struct of_device_id sky1_pinctrl_of_match[] = {
{ .compatible = "cix,sky1-pinctrl-s5", .data = &sky1_pinctrl_s5_info, },
{ .compatible = "cix,sky1-pinctrl", .data = &sky1_pinctrl_info, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sky1_pinctrl_of_match);
static int __maybe_unused sky1_pinctrl_suspend(struct device *dev)
{
struct sky1_pinctrl *spctl = dev_get_drvdata(dev);
return pinctrl_force_sleep(spctl->pctl);
}
static int __maybe_unused sky1_pinctrl_resume(struct device *dev)
{
struct sky1_pinctrl *spctl = dev_get_drvdata(dev);
return pinctrl_force_default(spctl->pctl);
}
const struct dev_pm_ops sky1_pinctrl_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(sky1_pinctrl_suspend,
sky1_pinctrl_resume)
};
EXPORT_SYMBOL_GPL(sky1_pinctrl_pm_ops);
static int sky1_pinctrl_probe(struct platform_device *pdev)
{
const struct sky1_pinctrl_soc_info *pinctrl_info;
pinctrl_info = device_get_match_data(&pdev->dev);
if (!pinctrl_info)
return -ENODEV;
return sky1_base_pinctrl_probe(pdev, pinctrl_info);
}
static struct platform_driver sky1_pinctrl_driver = {
.driver = {
.name = "sky1-pinctrl",
.of_match_table = sky1_pinctrl_of_match,
.pm = &sky1_pinctrl_pm_ops,
},
.probe = sky1_pinctrl_probe,
};
static int __init sky1_pinctrl_init(void)
{
return platform_driver_register(&sky1_pinctrl_driver);
}
arch_initcall(sky1_pinctrl_init);
MODULE_AUTHOR("Jerry Zhu <Jerry.Zhu@cixtech.com>");
MODULE_DESCRIPTION("Cix Sky1 pinctrl driver");
MODULE_LICENSE("GPL");
drivers/pinctrl/cix/pinctrl-sky1.h
+48
View File
@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Author: Jerry Zhu <Jerry.Zhu@cixtech.com>
*/
#ifndef __DRIVERS_PINCTRL_SKY1_H
#define __DRIVERS_PINCTRL_SKY1_H
struct sky1_pinctrl_group {
const char *name;
unsigned long config;
unsigned int pin;
};
struct sky1_pin_desc {
const struct pinctrl_pin_desc pin;
const char * const *func_group;
unsigned int nfunc;
};
struct sky1_pinctrl_soc_info {
const struct sky1_pin_desc *pins;
unsigned int npins;
};
#define SKY_PINFUNCTION(_pin, _func) \
((struct sky1_pin_desc) { \
.pin = _pin, \
.func_group = _func##_group, \
.nfunc = ARRAY_SIZE(_func##_group), \
})
/**
* @dev: a pointer back to containing device
* @base: the offset to the controller in virtual memory
*/
struct sky1_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
const struct sky1_pinctrl_soc_info *info;
struct sky1_pinctrl_group *groups;
const char **grp_names;
};
int sky1_base_pinctrl_probe(struct platform_device *pdev,
const struct sky1_pinctrl_soc_info *info);
#endif /* __DRIVERS_PINCTRL_SKY1_H */
drivers/pinctrl/core.c
+2 -1
View File
@@ -70,6 +70,7 @@ void pinctrl_provide_dummies(void)
{
pinctrl_dummy_state = true;
}
EXPORT_SYMBOL_GPL(pinctrl_provide_dummies);
const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
{
@@ -2416,7 +2417,7 @@ EXPORT_SYMBOL_GPL(devm_pinctrl_unregister);
static int __init pinctrl_init(void)
{
pr_info("initialized pinctrl subsystem\n");
pr_debug("initialized pinctrl subsystem\n");
pinctrl_init_debugfs();
return 0;
}
drivers/pinctrl/intel/pinctrl-alderlake.c
+30 -38
View File
@@ -27,14 +27,6 @@
#define ADL_S_GPI_IS 0x200
#define ADL_S_GPI_IE 0x220
#define ADL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define ADL_N_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N)
@@ -316,28 +308,28 @@ static const struct pinctrl_pin_desc adln_pins[] = {
};
static const struct intel_padgroup adln_community0_gpps[] = {
ADL_GPP(0, 0, 25, 0), /* GPP_B */
ADL_GPP(1, 26, 41, 32), /* GPP_T */
ADL_GPP(2, 42, 66, 64), /* GPP_A */
INTEL_GPP(0, 0, 25, 0), /* GPP_B */
INTEL_GPP(1, 26, 41, 32), /* GPP_T */
INTEL_GPP(2, 42, 66, 64), /* GPP_A */
};
static const struct intel_padgroup adln_community1_gpps[] = {
ADL_GPP(0, 67, 74, 96), /* GPP_S */
ADL_GPP(1, 75, 94, 128), /* GPP_I */
ADL_GPP(2, 95, 118, 160), /* GPP_H */
ADL_GPP(3, 119, 139, 192), /* GPP_D */
ADL_GPP(4, 140, 168, 224), /* vGPIO */
INTEL_GPP(0, 67, 74, 96), /* GPP_S */
INTEL_GPP(1, 75, 94, 128), /* GPP_I */
INTEL_GPP(2, 95, 118, 160), /* GPP_H */
INTEL_GPP(3, 119, 139, 192), /* GPP_D */
INTEL_GPP(4, 140, 168, 224), /* vGPIO */
};
static const struct intel_padgroup adln_community4_gpps[] = {
ADL_GPP(0, 169, 192, 256), /* GPP_C */
ADL_GPP(1, 193, 217, 288), /* GPP_F */
ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
ADL_GPP(3, 224, 248, 320), /* GPP_E */
INTEL_GPP(0, 169, 192, 256), /* GPP_C */
INTEL_GPP(1, 193, 217, 288), /* GPP_F */
INTEL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(3, 224, 248, 320), /* GPP_E */
};
static const struct intel_padgroup adln_community5_gpps[] = {
ADL_GPP(0, 249, 256, 352), /* GPP_R */
INTEL_GPP(0, 249, 256, 352), /* GPP_R */
};
static const struct intel_community adln_communities[] = {
@@ -680,35 +672,35 @@ static const struct pinctrl_pin_desc adls_pins[] = {
};
static const struct intel_padgroup adls_community0_gpps[] = {
ADL_GPP(0, 0, 24, 0), /* GPP_I */
ADL_GPP(1, 25, 47, 32), /* GPP_R */
ADL_GPP(2, 48, 59, 64), /* GPP_J */
ADL_GPP(3, 60, 86, 96), /* vGPIO */
ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */
INTEL_GPP(0, 0, 24, 0), /* GPP_I */
INTEL_GPP(1, 25, 47, 32), /* GPP_R */
INTEL_GPP(2, 48, 59, 64), /* GPP_J */
INTEL_GPP(3, 60, 86, 96), /* vGPIO */
INTEL_GPP(4, 87, 94, 128), /* vGPIO_0 */
};
static const struct intel_padgroup adls_community1_gpps[] = {
ADL_GPP(0, 95, 118, 160), /* GPP_B */
ADL_GPP(1, 119, 126, 192), /* GPP_G */
ADL_GPP(2, 127, 150, 224), /* GPP_H */
INTEL_GPP(0, 95, 118, 160), /* GPP_B */
INTEL_GPP(1, 119, 126, 192), /* GPP_G */
INTEL_GPP(2, 127, 150, 224), /* GPP_H */
};
static const struct intel_padgroup adls_community3_gpps[] = {
ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */
ADL_GPP(1, 160, 175, 256), /* GPP_A */
ADL_GPP(2, 176, 199, 288), /* GPP_C */
INTEL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */
INTEL_GPP(1, 160, 175, 256), /* GPP_A */
INTEL_GPP(2, 176, 199, 288), /* GPP_C */
};
static const struct intel_padgroup adls_community4_gpps[] = {
ADL_GPP(0, 200, 207, 320), /* GPP_S */
ADL_GPP(1, 208, 230, 352), /* GPP_E */
ADL_GPP(2, 231, 245, 384), /* GPP_K */
ADL_GPP(3, 246, 269, 416), /* GPP_F */
INTEL_GPP(0, 200, 207, 320), /* GPP_S */
INTEL_GPP(1, 208, 230, 352), /* GPP_E */
INTEL_GPP(2, 231, 245, 384), /* GPP_K */
INTEL_GPP(3, 246, 269, 416), /* GPP_F */
};
static const struct intel_padgroup adls_community5_gpps[] = {
ADL_GPP(0, 270, 294, 448), /* GPP_D */
ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(0, 270, 294, 448), /* GPP_D */
INTEL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_community adls_communities[] = {
drivers/pinctrl/intel/pinctrl-baytrail.c
+8 -12
View File
@@ -1498,9 +1498,9 @@ static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
if (ret)
dev_err(dev, "failed to add GPIO pin range\n");
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
return ret;
return 0;
}
static int byt_gpio_probe(struct intel_pinctrl *vg)
@@ -1548,9 +1548,9 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
ret = devm_gpiochip_add_data(vg->dev, gc, vg);
if (ret)
dev_err(vg->dev, "failed adding byt-gpio chip\n");
return dev_err_probe(vg->dev, ret, "failed to register gpiochip\n");
return ret;
return 0;
}
static int byt_set_soc_data(struct intel_pinctrl *vg,
@@ -1601,10 +1601,8 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
vg->dev = dev;
ret = byt_set_soc_data(vg, soc_data);
if (ret) {
dev_err(dev, "failed to set soc data\n");
return ret;
}
if (ret)
return dev_err_probe(dev, ret, "failed to set soc data\n");
vg->pctldesc = byt_pinctrl_desc;
vg->pctldesc.name = dev_name(dev);
@@ -1612,10 +1610,8 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
vg->pctldesc.npins = vg->soc->npins;
vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
if (IS_ERR(vg->pctldev)) {
dev_err(dev, "failed to register pinctrl driver\n");
return PTR_ERR(vg->pctldev);
}
if (IS_ERR(vg->pctldev))
return dev_err_probe(dev, PTR_ERR(vg->pctldev), "failed to register pinctrl\n");
ret = byt_gpio_probe(vg);
if (ret)
drivers/pinctrl/intel/pinctrl-cannonlake.c
+30 -38
View File
@@ -28,14 +28,6 @@
#define CNL_H_GPI_IS 0x100
#define CNL_H_GPI_IE 0x120
#define CNL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define CNL_LP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)
@@ -362,32 +354,32 @@ static const struct pinctrl_pin_desc cnlh_pins[] = {
};
static const struct intel_padgroup cnlh_community0_gpps[] = {
CNL_GPP(0, 0, 24, 0), /* GPP_A */
CNL_GPP(1, 25, 50, 32), /* GPP_B */
INTEL_GPP(0, 0, 24, 0), /* GPP_A */
INTEL_GPP(1, 25, 50, 32), /* GPP_B */
};
static const struct intel_padgroup cnlh_community1_gpps[] = {
CNL_GPP(0, 51, 74, 64), /* GPP_C */
CNL_GPP(1, 75, 98, 96), /* GPP_D */
CNL_GPP(2, 99, 106, 128), /* GPP_G */
CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
INTEL_GPP(0, 51, 74, 64), /* GPP_C */
INTEL_GPP(1, 75, 98, 96), /* GPP_D */
INTEL_GPP(2, 99, 106, 128), /* GPP_G */
INTEL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
INTEL_GPP(4, 115, 146, 160), /* vGPIO_0 */
INTEL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
};
static const struct intel_padgroup cnlh_community3_gpps[] = {
CNL_GPP(0, 155, 178, 192), /* GPP_K */
CNL_GPP(1, 179, 202, 224), /* GPP_H */
CNL_GPP(2, 203, 215, 256), /* GPP_E */
CNL_GPP(3, 216, 239, 288), /* GPP_F */
CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(0, 155, 178, 192), /* GPP_K */
INTEL_GPP(1, 179, 202, 224), /* GPP_H */
INTEL_GPP(2, 203, 215, 256), /* GPP_E */
INTEL_GPP(3, 216, 239, 288), /* GPP_F */
INTEL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_padgroup cnlh_community4_gpps[] = {
CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
CNL_GPP(2, 269, 286, 320), /* GPP_I */
CNL_GPP(3, 287, 298, 352), /* GPP_J */
INTEL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
INTEL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(2, 269, 286, 320), /* GPP_I */
INTEL_GPP(3, 287, 298, 352), /* GPP_J */
};
static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
@@ -780,25 +772,25 @@ static const struct intel_function cnllp_functions[] = {
};
static const struct intel_padgroup cnllp_community0_gpps[] = {
CNL_GPP(0, 0, 24, 0), /* GPP_A */
CNL_GPP(1, 25, 50, 32), /* GPP_B */
CNL_GPP(2, 51, 58, 64), /* GPP_G */
CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(0, 0, 24, 0), /* GPP_A */
INTEL_GPP(1, 25, 50, 32), /* GPP_B */
INTEL_GPP(2, 51, 58, 64), /* GPP_G */
INTEL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_padgroup cnllp_community1_gpps[] = {
CNL_GPP(0, 68, 92, 96), /* GPP_D */
CNL_GPP(1, 93, 116, 128), /* GPP_F */
CNL_GPP(2, 117, 140, 160), /* GPP_H */
CNL_GPP(3, 141, 172, 192), /* vGPIO */
CNL_GPP(4, 173, 180, 224), /* vGPIO */
INTEL_GPP(0, 68, 92, 96), /* GPP_D */
INTEL_GPP(1, 93, 116, 128), /* GPP_F */
INTEL_GPP(2, 117, 140, 160), /* GPP_H */
INTEL_GPP(3, 141, 172, 192), /* vGPIO */
INTEL_GPP(4, 173, 180, 224), /* vGPIO */
};
static const struct intel_padgroup cnllp_community4_gpps[] = {
CNL_GPP(0, 181, 204, 256), /* GPP_C */
CNL_GPP(1, 205, 228, 288), /* GPP_E */
CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(0, 181, 204, 256), /* GPP_C */
INTEL_GPP(1, 205, 228, 288), /* GPP_E */
INTEL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
};
static const struct intel_community cnllp_communities[] = {
drivers/pinctrl/intel/pinctrl-cedarfork.c
+15 -22
View File
@@ -21,13 +21,6 @@
#define CDF_GPI_IS 0x200
#define CDF_GPI_IE 0x230
#define CDF_GPP(r, s, e) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
}
#define CDF_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, CDF)
@@ -288,24 +281,24 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
};
static const struct intel_padgroup cdf_community0_gpps[] = {
CDF_GPP(0, 0, 23), /* WEST2 */
CDF_GPP(1, 24, 47), /* WEST3 */
CDF_GPP(2, 48, 70), /* WEST01 */
CDF_GPP(3, 71, 90), /* WEST5 */
CDF_GPP(4, 91, 96), /* WESTC */
CDF_GPP(5, 97, 101), /* WESTC_DFX */
CDF_GPP(6, 102, 111), /* WESTA */
CDF_GPP(7, 112, 123), /* WESTB */
CDF_GPP(8, 124, 143), /* WESTD */
CDF_GPP(9, 144, 144), /* WESTD_PECI */
CDF_GPP(10, 145, 167), /* WESTF */
INTEL_GPP(0, 0, 23, 0), /* WEST2 */
INTEL_GPP(1, 24, 47, 24), /* WEST3 */
INTEL_GPP(2, 48, 70, 48), /* WEST01 */
INTEL_GPP(3, 71, 90, 71), /* WEST5 */
INTEL_GPP(4, 91, 96, 91), /* WESTC */
INTEL_GPP(5, 97, 101, 97), /* WESTC_DFX */
INTEL_GPP(6, 102, 111, 102), /* WESTA */
INTEL_GPP(7, 112, 123, 112), /* WESTB */
INTEL_GPP(8, 124, 143, 124), /* WESTD */
INTEL_GPP(9, 144, 144, 144), /* WESTD_PECI */
INTEL_GPP(10, 145, 167, 145), /* WESTF */
};
static const struct intel_padgroup cdf_community1_gpps[] = {
CDF_GPP(0, 168, 191), /* EAST2 */
CDF_GPP(1, 192, 202), /* EAST3 */
CDF_GPP(2, 203, 225), /* EAST0 */
CDF_GPP(3, 226, 236), /* EMMC */
INTEL_GPP(0, 168, 191, 168), /* EAST2 */
INTEL_GPP(1, 192, 202, 192), /* EAST3 */
INTEL_GPP(2, 203, 225, 203), /* EAST0 */
INTEL_GPP(3, 226, 236, 226), /* EMMC */
};
static const struct intel_community cdf_communities[] = {
drivers/pinctrl/intel/pinctrl-cherryview.c
+27 -59
View File
@@ -92,12 +92,6 @@ struct intel_community_context {
#define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE))
#define CHV_GPP(start, end) \
{ \
.base = (start), \
.size = (end) - (start) + 1, \
}
#define CHV_COMMUNITY(g, i, a) \
{ \
.gpps = (g), \
@@ -258,13 +252,13 @@ static const struct intel_function southwest_functions[] = {
};
static const struct intel_padgroup southwest_gpps[] = {
CHV_GPP(0, 7),
CHV_GPP(15, 22),
CHV_GPP(30, 37),
CHV_GPP(45, 52),
CHV_GPP(60, 67),
CHV_GPP(75, 82),
CHV_GPP(90, 97),
INTEL_GPP(0, 0, 7, 0),
INTEL_GPP(1, 15, 22, 15),
INTEL_GPP(2, 30, 37, 30),
INTEL_GPP(3, 45, 52, 45),
INTEL_GPP(4, 60, 67, 60),
INTEL_GPP(5, 75, 82, 75),
INTEL_GPP(6, 90, 97, 90),
};
/*
@@ -354,11 +348,11 @@ static const struct pinctrl_pin_desc north_pins[] = {
};
static const struct intel_padgroup north_gpps[] = {
CHV_GPP(0, 8),
CHV_GPP(15, 27),
CHV_GPP(30, 41),
CHV_GPP(45, 56),
CHV_GPP(60, 72),
INTEL_GPP(0, 0, 8, 0),
INTEL_GPP(1, 15, 27, 15),
INTEL_GPP(2, 30, 41, 30),
INTEL_GPP(3, 45, 56, 45),
INTEL_GPP(4, 60, 72, 60),
};
/*
@@ -406,8 +400,8 @@ static const struct pinctrl_pin_desc east_pins[] = {
};
static const struct intel_padgroup east_gpps[] = {
CHV_GPP(0, 11),
CHV_GPP(15, 26),
INTEL_GPP(0, 0, 11, 0),
INTEL_GPP(1, 15, 26, 15),
};
static const struct intel_community east_communities[] = {
@@ -526,12 +520,12 @@ static const struct intel_function southeast_functions[] = {
};
static const struct intel_padgroup southeast_gpps[] = {
CHV_GPP(0, 7),
CHV_GPP(15, 26),
CHV_GPP(30, 35),
CHV_GPP(45, 52),
CHV_GPP(60, 69),
CHV_GPP(75, 85),
INTEL_GPP(0, 0, 7, 0),
INTEL_GPP(1, 15, 26, 15),
INTEL_GPP(2, 30, 35, 30),
INTEL_GPP(3, 45, 52, 45),
INTEL_GPP(4, 60, 69, 60),
INTEL_GPP(5, 75, 85, 75),
};
static const struct intel_community southeast_communities[] = {
@@ -1517,26 +1511,6 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
return 0;
}
static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
struct device *dev = pctrl->dev;
const struct intel_community *community = &pctrl->communities[0];
const struct intel_padgroup *gpp;
int ret, i;
for (i = 0; i < community->ngpps; i++) {
gpp = &community->gpps[i];
ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size);
if (ret) {
dev_err(dev, "failed to add GPIO pin range\n");
return ret;
}
}
return 0;
}
static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
{
const struct intel_community *community = &pctrl->communities[0];
@@ -1550,7 +1524,7 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
chip->label = dev_name(dev);
chip->add_pin_ranges = chv_gpio_add_pin_ranges;
chip->add_pin_ranges = intel_gpio_add_pin_ranges;
chip->parent = dev;
chip->base = -1;
@@ -1567,17 +1541,13 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
chip->irq.init_valid_mask = chv_init_irq_valid_mask;
} else {
irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE);
if (irq_base < 0) {
dev_err(dev, "Failed to allocate IRQ numbers\n");
return irq_base;
}
if (irq_base < 0)
return dev_err_probe(dev, irq_base, "failed to allocate IRQ numbers\n");
}
ret = devm_gpiochip_add_data(dev, chip, pctrl);
if (ret) {
dev_err(dev, "Failed to register gpiochip\n");
return ret;
}
if (ret)
return dev_err_probe(dev, ret, "failed to register gpiochip\n");
if (!need_valid_mask) {
for (i = 0; i < community->ngpps; i++) {
@@ -1673,10 +1643,8 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
pctrl->pctldesc.npins = pctrl->soc->npins;
pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
if (IS_ERR(pctrl->pctldev)) {
dev_err(dev, "failed to register pinctrl driver\n");
return PTR_ERR(pctrl->pctldev);
}
if (IS_ERR(pctrl->pctldev))
return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), "failed to register pinctrl\n");
ret = chv_gpio_probe(pctrl, irq);
if (ret)
drivers/pinctrl/intel/pinctrl-denverton.c
+7 -14
View File
@@ -21,13 +21,6 @@
#define DNV_GPI_IS 0x100
#define DNV_GPI_IE 0x120
#define DNV_GPP(n, s, e) \
{ \
.reg_num = (n), \
.base = (s), \
.size = ((e) - (s) + 1), \
}
#define DNV_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, DNV)
@@ -222,16 +215,16 @@ static const struct intel_function dnv_functions[] = {
};
static const struct intel_padgroup dnv_north_gpps[] = {
DNV_GPP(0, 0, 31), /* North ALL_0 */
DNV_GPP(1, 32, 40), /* North ALL_1 */
INTEL_GPP(0, 0, 31, 0), /* North ALL_0 */
INTEL_GPP(1, 32, 40, 32), /* North ALL_1 */
};
static const struct intel_padgroup dnv_south_gpps[] = {
DNV_GPP(0, 41, 58), /* South DFX */
DNV_GPP(1, 59, 90), /* South GPP0_0 */
DNV_GPP(2, 91, 111), /* South GPP0_1 */
DNV_GPP(3, 112, 143), /* South GPP1_0 */
DNV_GPP(4, 144, 153), /* South GPP1_1 */
INTEL_GPP(0, 41, 58, 41), /* South DFX */
INTEL_GPP(1, 59, 90, 59), /* South GPP0_0 */
INTEL_GPP(2, 91, 111, 91), /* South GPP0_1 */
INTEL_GPP(3, 112, 143, 112), /* South GPP1_0 */
INTEL_GPP(4, 144, 153, 144), /* South GPP1_1 */
};
static const struct intel_community dnv_communities[] = {
drivers/pinctrl/intel/pinctrl-elkhartlake.c
+18 -25
View File
@@ -21,13 +21,6 @@
#define EHL_GPI_IS 0x100
#define EHL_GPI_IE 0x120
#define EHL_GPP(r, s, e) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
}
#define EHL_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, EHL)
@@ -106,9 +99,9 @@ static const struct pinctrl_pin_desc ehl_community0_pins[] = {
};
static const struct intel_padgroup ehl_community0_gpps[] = {
EHL_GPP(0, 0, 25), /* GPP_B */
EHL_GPP(1, 26, 41), /* GPP_T */
EHL_GPP(2, 42, 66), /* GPP_G */
INTEL_GPP(0, 0, 25, 0), /* GPP_B */
INTEL_GPP(1, 26, 41, 26), /* GPP_T */
INTEL_GPP(2, 42, 66, 42), /* GPP_G */
};
static const struct intel_community ehl_community0[] = {
@@ -245,11 +238,11 @@ static const struct pinctrl_pin_desc ehl_community1_pins[] = {
};
static const struct intel_padgroup ehl_community1_gpps[] = {
EHL_GPP(0, 0, 15), /* GPP_V */
EHL_GPP(1, 16, 39), /* GPP_H */
EHL_GPP(2, 40, 60), /* GPP_D */
EHL_GPP(3, 61, 84), /* GPP_U */
EHL_GPP(4, 85, 112), /* vGPIO */
INTEL_GPP(0, 0, 15, 0), /* GPP_V */
INTEL_GPP(1, 16, 39, 16), /* GPP_H */
INTEL_GPP(2, 40, 60, 40), /* GPP_D */
INTEL_GPP(3, 61, 84, 61), /* GPP_U */
INTEL_GPP(4, 85, 112, 85), /* vGPIO */
};
static const struct intel_community ehl_community1[] = {
@@ -286,7 +279,7 @@ static const struct pinctrl_pin_desc ehl_community2_pins[] = {
};
static const struct intel_padgroup ehl_community2_gpps[] = {
EHL_GPP(0, 0, 16), /* DSW */
INTEL_GPP(0, 0, 16, 0), /* DSW */
};
static const struct intel_community ehl_community2[] = {
@@ -356,10 +349,10 @@ static const struct pinctrl_pin_desc ehl_community3_pins[] = {
};
static const struct intel_padgroup ehl_community3_gpps[] = {
EHL_GPP(0, 0, 16), /* CPU */
EHL_GPP(1, 17, 18), /* GPP_S */
EHL_GPP(2, 19, 42), /* GPP_A */
EHL_GPP(3, 43, 46), /* vGPIO_3 */
INTEL_GPP(0, 0, 16, 0), /* CPU */
INTEL_GPP(1, 17, 18, 17), /* GPP_S */
INTEL_GPP(2, 19, 42, 19), /* GPP_A */
INTEL_GPP(3, 43, 46, 43), /* vGPIO_3 */
};
static const struct intel_community ehl_community3[] = {
@@ -462,10 +455,10 @@ static const struct pinctrl_pin_desc ehl_community4_pins[] = {
};
static const struct intel_padgroup ehl_community4_gpps[] = {
EHL_GPP(0, 0, 23), /* GPP_C */
EHL_GPP(1, 24, 48), /* GPP_F */
EHL_GPP(2, 49, 54), /* HVCMOS */
EHL_GPP(3, 55, 79), /* GPP_E */
INTEL_GPP(0, 0, 23, 0), /* GPP_C */
INTEL_GPP(1, 24, 48, 24), /* GPP_F */
INTEL_GPP(2, 49, 54, 49), /* HVCMOS */
INTEL_GPP(3, 55, 79, 55), /* GPP_E */
};
static const struct intel_community ehl_community4[] = {
@@ -493,7 +486,7 @@ static const struct pinctrl_pin_desc ehl_community5_pins[] = {
};
static const struct intel_padgroup ehl_community5_gpps[] = {
EHL_GPP(0, 0, 7), /* GPP_R */
INTEL_GPP(0, 0, 7, 0), /* GPP_R */
};
static const struct intel_community ehl_community5[] = {
drivers/pinctrl/intel/pinctrl-emmitsburg.c
+13 -20
View File
@@ -21,13 +21,6 @@
#define EBG_GPI_IS 0x200
#define EBG_GPI_IE 0x210
#define EBG_GPP(r, s, e) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
}
#define EBG_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, EBG)
@@ -311,31 +304,31 @@ static const struct pinctrl_pin_desc ebg_pins[] = {
};
static const struct intel_padgroup ebg_community0_gpps[] = {
EBG_GPP(0, 0, 20), /* GPP_A */
EBG_GPP(1, 21, 44), /* GPP_B */
EBG_GPP(2, 45, 65), /* SPI */
INTEL_GPP(0, 0, 20, 0), /* GPP_A */
INTEL_GPP(1, 21, 44, 21), /* GPP_B */
INTEL_GPP(2, 45, 65, 45), /* SPI */
};
static const struct intel_padgroup ebg_community1_gpps[] = {
EBG_GPP(0, 66, 87), /* GPP_C */
EBG_GPP(1, 88, 111), /* GPP_D */
INTEL_GPP(0, 66, 87, 66), /* GPP_C */
INTEL_GPP(1, 88, 111, 88), /* GPP_D */
};
static const struct intel_padgroup ebg_community3_gpps[] = {
EBG_GPP(0, 112, 135), /* GPP_E */
EBG_GPP(1, 136, 145), /* JTAG */
INTEL_GPP(0, 112, 135, 112), /* GPP_E */
INTEL_GPP(1, 136, 145, 136), /* JTAG */
};
static const struct intel_padgroup ebg_community4_gpps[] = {
EBG_GPP(0, 146, 165), /* GPP_H */
EBG_GPP(1, 166, 183), /* GPP_J */
INTEL_GPP(0, 146, 165, 146), /* GPP_H */
INTEL_GPP(1, 166, 183, 166), /* GPP_J */
};
static const struct intel_padgroup ebg_community5_gpps[] = {
EBG_GPP(0, 184, 207), /* GPP_I */
EBG_GPP(1, 208, 225), /* GPP_L */
EBG_GPP(2, 226, 243), /* GPP_M */
EBG_GPP(3, 244, 261), /* GPP_N */
INTEL_GPP(0, 184, 207, 184), /* GPP_I */
INTEL_GPP(1, 208, 225, 208), /* GPP_L */
INTEL_GPP(2, 226, 243, 226), /* GPP_M */
INTEL_GPP(3, 244, 261, 244), /* GPP_N */
};
static const struct intel_community ebg_communities[] = {
drivers/pinctrl/intel/pinctrl-icelake.c
+26 -34
View File
@@ -28,14 +28,6 @@
#define ICL_N_GPI_IS 0x100
#define ICL_N_GPI_IE 0x120
#define ICL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define ICL_LP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP)
@@ -302,29 +294,29 @@ static const struct pinctrl_pin_desc icllp_pins[] = {
};
static const struct intel_padgroup icllp_community0_gpps[] = {
ICL_GPP(0, 0, 7, 0), /* GPP_G */
ICL_GPP(1, 8, 33, 32), /* GPP_B */
ICL_GPP(2, 34, 58, 64), /* GPP_A */
INTEL_GPP(0, 0, 7, 0), /* GPP_G */
INTEL_GPP(1, 8, 33, 32), /* GPP_B */
INTEL_GPP(2, 34, 58, 64), /* GPP_A */
};
static const struct intel_padgroup icllp_community1_gpps[] = {
ICL_GPP(0, 59, 82, 96), /* GPP_H */
ICL_GPP(1, 83, 103, 128), /* GPP_D */
ICL_GPP(2, 104, 123, 160), /* GPP_F */
ICL_GPP(3, 124, 152, 192), /* vGPIO */
INTEL_GPP(0, 59, 82, 96), /* GPP_H */
INTEL_GPP(1, 83, 103, 128), /* GPP_D */
INTEL_GPP(2, 104, 123, 160), /* GPP_F */
INTEL_GPP(3, 124, 152, 192), /* vGPIO */
};
static const struct intel_padgroup icllp_community4_gpps[] = {
ICL_GPP(0, 153, 176, 224), /* GPP_C */
ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
ICL_GPP(2, 183, 206, 256), /* GPP_E */
ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(0, 153, 176, 224), /* GPP_C */
INTEL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(2, 183, 206, 256), /* GPP_E */
INTEL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_padgroup icllp_community5_gpps[] = {
ICL_GPP(0, 216, 223, 288), /* GPP_R */
ICL_GPP(1, 224, 231, 320), /* GPP_S */
ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(0, 216, 223, 288), /* GPP_R */
INTEL_GPP(1, 224, 231, 320), /* GPP_S */
INTEL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_community icllp_communities[] = {
@@ -632,27 +624,27 @@ static const struct pinctrl_pin_desc icln_pins[] = {
};
static const struct intel_padgroup icln_community0_gpps[] = {
ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
ICL_GPP(1, 9, 34, 32), /* GPP_B */
ICL_GPP(2, 35, 55, 64), /* GPP_A */
ICL_GPP(3, 56, 63, 96), /* GPP_S */
ICL_GPP(4, 64, 71, 128), /* GPP_R */
INTEL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(1, 9, 34, 32), /* GPP_B */
INTEL_GPP(2, 35, 55, 64), /* GPP_A */
INTEL_GPP(3, 56, 63, 96), /* GPP_S */
INTEL_GPP(4, 64, 71, 128), /* GPP_R */
};
static const struct intel_padgroup icln_community1_gpps[] = {
ICL_GPP(0, 72, 95, 160), /* GPP_H */
ICL_GPP(1, 96, 121, 192), /* GPP_D */
ICL_GPP(2, 122, 150, 224), /* vGPIO */
ICL_GPP(3, 151, 174, 256), /* GPP_C */
INTEL_GPP(0, 72, 95, 160), /* GPP_H */
INTEL_GPP(1, 96, 121, 192), /* GPP_D */
INTEL_GPP(2, 122, 150, 224), /* vGPIO */
INTEL_GPP(3, 151, 174, 256), /* GPP_C */
};
static const struct intel_padgroup icln_community4_gpps[] = {
ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
ICL_GPP(1, 181, 204, 288), /* GPP_E */
INTEL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(1, 181, 204, 288), /* GPP_E */
};
static const struct intel_padgroup icln_community5_gpps[] = {
ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
INTEL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
};
static const struct intel_community icln_communities[] = {
drivers/pinctrl/intel/pinctrl-intel.c
+19 -17
View File
@@ -1345,7 +1345,16 @@ static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
return 0;
}
static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
/**
* intel_gpio_add_pin_ranges - add GPIO pin ranges for all groups in all communities
* @gc: GPIO chip structure
*
* This function iterates over all communities and all groups and adds the respective
* GPIO pin ranges, so the GPIO library will correctly map a GPIO offset to a pin number.
*
* Return: 0, or negative error code if range can't be added.
*/
int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
const struct intel_community *community;
@@ -1356,14 +1365,13 @@ static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
grp->gpio_base, grp->base,
grp->size);
if (ret) {
dev_err(pctrl->dev, "failed to add GPIO pin range\n");
return ret;
}
if (ret)
return dev_err_probe(pctrl->dev, ret, "failed to add GPIO pin range\n");
}
return 0;
}
EXPORT_SYMBOL_NS_GPL(intel_gpio_add_pin_ranges, "PINCTRL_INTEL");
static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
{
@@ -1401,10 +1409,8 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
IRQF_SHARED | IRQF_NO_THREAD,
dev_name(pctrl->dev), pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to request interrupt\n");
return ret;
}
if (ret)
return dev_err_probe(pctrl->dev, ret, "failed to request interrupt\n");
/* Setup IRQ chip */
girq = &pctrl->chip.irq;
@@ -1417,10 +1423,8 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
girq->init_hw = intel_gpio_irq_init_hw;
ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to register gpiochip\n");
return ret;
}
if (ret)
return dev_err_probe(pctrl->dev, ret, "failed to register gpiochip\n");
return 0;
}
@@ -1668,10 +1672,8 @@ int intel_pinctrl_probe(struct platform_device *pdev,
pctrl->pctldesc.npins = pctrl->soc->npins;
pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
if (IS_ERR(pctrl->pctldev)) {
dev_err(dev, "failed to register pinctrl driver\n");
return PTR_ERR(pctrl->pctldev);
}
if (IS_ERR(pctrl->pctldev))
return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), "failed to register pinctrl\n");
ret = intel_gpio_probe(pctrl, irq);
if (ret)
drivers/pinctrl/intel/pinctrl-intel.h
+11
View File
@@ -76,6 +76,15 @@ enum {
INTEL_GPIO_BASE_MATCH = 0,
};
/* Initialise struct intel_padgroup */
#define INTEL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
/**
* struct intel_community - Intel pin community description
* @barno: MMIO BAR number where registers for this community reside
@@ -267,6 +276,8 @@ extern const struct dev_pm_ops intel_pinctrl_pm_ops;
const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
unsigned int pin);
int intel_gpio_add_pin_ranges(struct gpio_chip *gc);
int intel_get_groups_count(struct pinctrl_dev *pctldev);
const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group);
int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
drivers/pinctrl/intel/pinctrl-jasperlake.c
+13 -21
View File
@@ -21,14 +21,6 @@
#define JSL_GPI_IS 0x100
#define JSL_GPI_IE 0x120
#define JSL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define JSL_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, JSL)
@@ -283,28 +275,28 @@ static const struct pinctrl_pin_desc jsl_pins[] = {
};
static const struct intel_padgroup jsl_community0_gpps[] = {
JSL_GPP(0, 0, 19, 320), /* GPP_F */
JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */
JSL_GPP(2, 29, 54, 32), /* GPP_B */
JSL_GPP(3, 55, 75, 64), /* GPP_A */
JSL_GPP(4, 76, 83, 96), /* GPP_S */
JSL_GPP(5, 84, 91, 128), /* GPP_R */
INTEL_GPP(0, 0, 19, 320), /* GPP_F */
INTEL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(2, 29, 54, 32), /* GPP_B */
INTEL_GPP(3, 55, 75, 64), /* GPP_A */
INTEL_GPP(4, 76, 83, 96), /* GPP_S */
INTEL_GPP(5, 84, 91, 128), /* GPP_R */
};
static const struct intel_padgroup jsl_community1_gpps[] = {
JSL_GPP(0, 92, 115, 160), /* GPP_H */
JSL_GPP(1, 116, 141, 192), /* GPP_D */
JSL_GPP(2, 142, 170, 224), /* vGPIO */
JSL_GPP(3, 171, 194, 256), /* GPP_C */
INTEL_GPP(0, 92, 115, 160), /* GPP_H */
INTEL_GPP(1, 116, 141, 192), /* GPP_D */
INTEL_GPP(2, 142, 170, 224), /* vGPIO */
INTEL_GPP(3, 171, 194, 256), /* GPP_C */
};
static const struct intel_padgroup jsl_community4_gpps[] = {
JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
JSL_GPP(1, 201, 224, 288), /* GPP_E */
INTEL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(1, 201, 224, 288), /* GPP_E */
};
static const struct intel_padgroup jsl_community5_gpps[] = {
JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */
INTEL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */
};
static const struct intel_community jsl_communities[] = {
drivers/pinctrl/intel/pinctrl-lakefield.c
+9 -17
View File
@@ -21,14 +21,6 @@
#define LKF_GPI_IS 0x100
#define LKF_GPI_IE 0x110
#define LKF_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define LKF_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, LKF)
@@ -308,24 +300,24 @@ static const struct pinctrl_pin_desc lkf_pins[] = {
};
static const struct intel_padgroup lkf_community0_gpps[] = {
LKF_GPP(0, 0, 31, 0), /* EAST_0 */
LKF_GPP(1, 32, 59, 32), /* EAST_1 */
INTEL_GPP(0, 0, 31, 0), /* EAST_0 */
INTEL_GPP(1, 32, 59, 32), /* EAST_1 */
};
static const struct intel_padgroup lkf_community1_gpps[] = {
LKF_GPP(0, 60, 91, 64), /* NORTHWEST_0 */
LKF_GPP(1, 92, 123, 96), /* NORTHWEST_1 */
LKF_GPP(2, 124, 148, 128), /* NORTHWEST_2 */
INTEL_GPP(0, 60, 91, 64), /* NORTHWEST_0 */
INTEL_GPP(1, 92, 123, 96), /* NORTHWEST_1 */
INTEL_GPP(2, 124, 148, 128), /* NORTHWEST_2 */
};
static const struct intel_padgroup lkf_community2_gpps[] = {
LKF_GPP(0, 149, 180, 160), /* WEST_0 */
LKF_GPP(1, 181, 212, 192), /* WEST_1 */
LKF_GPP(2, 213, 237, 224), /* WEST_2 */
INTEL_GPP(0, 149, 180, 160), /* WEST_0 */
INTEL_GPP(1, 181, 212, 192), /* WEST_1 */
INTEL_GPP(2, 213, 237, 224), /* WEST_2 */
};
static const struct intel_padgroup lkf_community3_gpps[] = {
LKF_GPP(0, 238, 266, 256), /* SOUTHEAST */
INTEL_GPP(0, 238, 266, 256), /* SOUTHEAST */
};
static const struct intel_community lkf_communities[] = {
drivers/pinctrl/intel/pinctrl-lynxpoint.c
+10 -18
View File
@@ -700,9 +700,9 @@ static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
if (ret)
dev_err(dev, "failed to add GPIO pin range\n");
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
return ret;
return 0;
}
static int lp_gpio_probe(struct platform_device *pdev)
@@ -739,24 +739,18 @@ static int lp_gpio_probe(struct platform_device *pdev)
lg->pctldesc.npins = lg->soc->npins;
lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg);
if (IS_ERR(lg->pctldev)) {
dev_err(dev, "failed to register pinctrl driver\n");
return PTR_ERR(lg->pctldev);
}
if (IS_ERR(lg->pctldev))
return dev_err_probe(dev, PTR_ERR(lg->pctldev), "failed to register pinctrl\n");
platform_set_drvdata(pdev, lg);
io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!io_rc) {
dev_err(dev, "missing IO resources\n");
return -EINVAL;
}
if (!io_rc)
return dev_err_probe(dev, -EINVAL, "missing IO resources\n");
regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc));
if (!regs) {
dev_err(dev, "failed mapping IO region %pR\n", &io_rc);
return -EBUSY;
}
if (!regs)
return dev_err_probe(dev, -EBUSY, "failed mapping IO region %pR\n", &io_rc);
for (i = 0; i < lg->soc->ncommunities; i++) {
struct intel_community *comm = &lg->communities[i];
@@ -807,10 +801,8 @@ static int lp_gpio_probe(struct platform_device *pdev)
}
ret = devm_gpiochip_add_data(dev, gc, lg);
if (ret) {
dev_err(dev, "failed adding lp-gpio chip\n");
return ret;
}
if (ret)
return dev_err_probe(dev, ret, "failed to register gpiochip\n");
return 0;
}
drivers/pinctrl/intel/pinctrl-meteorlake.c
+23 -31
View File
@@ -27,14 +27,6 @@
#define MTL_S_GPI_IS 0x200
#define MTL_S_GPI_IE 0x210
#define MTL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define MTL_P_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P)
@@ -349,33 +341,33 @@ static const struct pinctrl_pin_desc mtlp_pins[] = {
};
static const struct intel_padgroup mtlp_community0_gpps[] = {
MTL_GPP(0, 0, 4, 0), /* CPU */
MTL_GPP(1, 5, 28, 32), /* GPP_V */
MTL_GPP(2, 29, 52, 64), /* GPP_C */
INTEL_GPP(0, 0, 4, 0), /* CPU */
INTEL_GPP(1, 5, 28, 32), /* GPP_V */
INTEL_GPP(2, 29, 52, 64), /* GPP_C */
};
static const struct intel_padgroup mtlp_community1_gpps[] = {
MTL_GPP(0, 53, 77, 96), /* GPP_A */
MTL_GPP(1, 78, 102, 128), /* GPP_E */
INTEL_GPP(0, 53, 77, 96), /* GPP_A */
INTEL_GPP(1, 78, 102, 128), /* GPP_E */
};
static const struct intel_padgroup mtlp_community3_gpps[] = {
MTL_GPP(0, 103, 128, 160), /* GPP_H */
MTL_GPP(1, 129, 154, 192), /* GPP_F */
MTL_GPP(2, 155, 169, 224), /* SPI0 */
MTL_GPP(3, 170, 183, 256), /* vGPIO_3 */
INTEL_GPP(0, 103, 128, 160), /* GPP_H */
INTEL_GPP(1, 129, 154, 192), /* GPP_F */
INTEL_GPP(2, 155, 169, 224), /* SPI0 */
INTEL_GPP(3, 170, 183, 256), /* vGPIO_3 */
};
static const struct intel_padgroup mtlp_community4_gpps[] = {
MTL_GPP(0, 184, 191, 288), /* GPP_S */
MTL_GPP(1, 192, 203, 320), /* JTAG */
INTEL_GPP(0, 184, 191, 288), /* GPP_S */
INTEL_GPP(1, 192, 203, 320), /* JTAG */
};
static const struct intel_padgroup mtlp_community5_gpps[] = {
MTL_GPP(0, 204, 228, 352), /* GPP_B */
MTL_GPP(1, 229, 253, 384), /* GPP_D */
MTL_GPP(2, 254, 285, 416), /* vGPIO_0 */
MTL_GPP(3, 286, 288, 448), /* vGPIO_1 */
INTEL_GPP(0, 204, 228, 352), /* GPP_B */
INTEL_GPP(1, 229, 253, 384), /* GPP_D */
INTEL_GPP(2, 254, 285, 416), /* vGPIO_0 */
INTEL_GPP(3, 286, 288, 448), /* vGPIO_1 */
};
static const struct intel_community mtlp_communities[] = {
@@ -554,20 +546,20 @@ static const struct pinctrl_pin_desc mtls_pins[] = {
};
static const struct intel_padgroup mtls_community0_gpps[] = {
MTL_GPP(0, 0, 27, 0), /* GPP_A */
MTL_GPP(1, 28, 46, 32), /* vGPIO_0 */
MTL_GPP(2, 47, 73, 64), /* GPP_C */
INTEL_GPP(0, 0, 27, 0), /* GPP_A */
INTEL_GPP(1, 28, 46, 32), /* vGPIO_0 */
INTEL_GPP(2, 47, 73, 64), /* GPP_C */
};
static const struct intel_padgroup mtls_community1_gpps[] = {
MTL_GPP(0, 74, 93, 96), /* GPP_B */
MTL_GPP(1, 94, 95, 128), /* vGPIO_3 */
MTL_GPP(2, 96, 119, 160), /* GPP_D */
INTEL_GPP(0, 74, 93, 96), /* GPP_B */
INTEL_GPP(1, 94, 95, 128), /* vGPIO_3 */
INTEL_GPP(2, 96, 119, 160), /* GPP_D */
};
static const struct intel_padgroup mtls_community3_gpps[] = {
MTL_GPP(0, 120, 135, 192), /* JTAG_CPU */
MTL_GPP(1, 136, 147, 224), /* vGPIO_4 */
INTEL_GPP(0, 120, 135, 192), /* JTAG_CPU */
INTEL_GPP(1, 136, 147, 224), /* vGPIO_4 */
};
static const struct intel_community mtls_communities[] = {
drivers/pinctrl/intel/pinctrl-meteorpoint.c
+19 -27
View File
@@ -21,14 +21,6 @@
#define MTP_GPI_IS 0x200
#define MTP_GPI_IE 0x220
#define MTP_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define MTP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, MTP)
@@ -395,37 +387,37 @@ static const struct pinctrl_pin_desc mtps_pins[] = {
};
static const struct intel_padgroup mtps_community0_gpps[] = {
MTP_GPP(0, 0, 24, 0), /* GPP_D */
MTP_GPP(1, 25, 38, 32), /* GPP_R */
MTP_GPP(2, 39, 56, 64), /* GPP_J */
MTP_GPP(3, 57, 87, 96), /* vGPIO */
INTEL_GPP(0, 0, 24, 0), /* GPP_D */
INTEL_GPP(1, 25, 38, 32), /* GPP_R */
INTEL_GPP(2, 39, 56, 64), /* GPP_J */
INTEL_GPP(3, 57, 87, 96), /* vGPIO */
};
static const struct intel_padgroup mtps_community1_gpps[] = {
MTP_GPP(0, 88, 102, 128), /* GPP_A */
MTP_GPP(1, 103, 114, 160), /* DIR_ESPI */
MTP_GPP(2, 115, 136, 192), /* GPP_B */
INTEL_GPP(0, 88, 102, 128), /* GPP_A */
INTEL_GPP(1, 103, 114, 160), /* DIR_ESPI */
INTEL_GPP(2, 115, 136, 192), /* GPP_B */
};
static const struct intel_padgroup mtps_community3_gpps[] = {
MTP_GPP(0, 137, 145, 224), /* SPI0 */
MTP_GPP(1, 146, 169, 256), /* GPP_C */
MTP_GPP(2, 170, 189, 288), /* GPP_H */
MTP_GPP(3, 190, 193, 320), /* vGPIO_3 */
MTP_GPP(4, 194, 201, 352), /* vGPIO_0 */
MTP_GPP(5, 202, 232, 384), /* vGPIO_4 */
INTEL_GPP(0, 137, 145, 224), /* SPI0 */
INTEL_GPP(1, 146, 169, 256), /* GPP_C */
INTEL_GPP(2, 170, 189, 288), /* GPP_H */
INTEL_GPP(3, 190, 193, 320), /* vGPIO_3 */
INTEL_GPP(4, 194, 201, 352), /* vGPIO_0 */
INTEL_GPP(5, 202, 232, 384), /* vGPIO_4 */
};
static const struct intel_padgroup mtps_community4_gpps[] = {
MTP_GPP(0, 233, 240, 416), /* GPP_S */
MTP_GPP(1, 241, 263, 448), /* GPP_E */
MTP_GPP(2, 264, 277, 480), /* GPP_K */
MTP_GPP(3, 278, 301, 512), /* GPP_F */
INTEL_GPP(0, 233, 240, 416), /* GPP_S */
INTEL_GPP(1, 241, 263, 448), /* GPP_E */
INTEL_GPP(2, 264, 277, 480), /* GPP_K */
INTEL_GPP(3, 278, 301, 512), /* GPP_F */
};
static const struct intel_padgroup mtps_community5_gpps[] = {
MTP_GPP(0, 302, 322, 544), /* GPP_I */
MTP_GPP(1, 323, 338, 576), /* JTAG_CPU */
INTEL_GPP(0, 302, 322, 544), /* GPP_I */
INTEL_GPP(1, 323, 338, 576), /* JTAG_CPU */
};
static const struct intel_community mtps_communities[] = {
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
+9 -17
View File
@@ -28,14 +28,6 @@
#define SPT_LP_GPI_IS 0x100
#define SPT_LP_GPI_IE 0x120
#define SPT_H_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define SPT_H_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, SPT_H)
@@ -538,21 +530,21 @@ static const struct intel_function spth_functions[] = {
};
static const struct intel_padgroup spth_community0_gpps[] = {
SPT_H_GPP(0, 0, 23, 0), /* GPP_A */
SPT_H_GPP(1, 24, 47, 24), /* GPP_B */
INTEL_GPP(0, 0, 23, 0), /* GPP_A */
INTEL_GPP(1, 24, 47, 24), /* GPP_B */
};
static const struct intel_padgroup spth_community1_gpps[] = {
SPT_H_GPP(0, 48, 71, 48), /* GPP_C */
SPT_H_GPP(1, 72, 95, 72), /* GPP_D */
SPT_H_GPP(2, 96, 108, 96), /* GPP_E */
SPT_H_GPP(3, 109, 132, 120), /* GPP_F */
SPT_H_GPP(4, 133, 156, 144), /* GPP_G */
SPT_H_GPP(5, 157, 180, 168), /* GPP_H */
INTEL_GPP(0, 48, 71, 48), /* GPP_C */
INTEL_GPP(1, 72, 95, 72), /* GPP_D */
INTEL_GPP(2, 96, 108, 96), /* GPP_E */
INTEL_GPP(3, 109, 132, 120), /* GPP_F */
INTEL_GPP(4, 133, 156, 144), /* GPP_G */
INTEL_GPP(5, 157, 180, 168), /* GPP_H */
};
static const struct intel_padgroup spth_community3_gpps[] = {
SPT_H_GPP(0, 181, 191, 192), /* GPP_I */
INTEL_GPP(0, 181, 191, 192), /* GPP_I */
};
static const struct intel_community spth_communities[] = {
drivers/pinctrl/intel/pinctrl-tangier.c
+1 -2
View File
@@ -562,8 +562,7 @@ static int tng_pinctrl_probe(struct platform_device *pdev,
tp->pctldev = devm_pinctrl_register(dev, &tp->pctldesc, tp);
if (IS_ERR(tp->pctldev))
return dev_err_probe(dev, PTR_ERR(tp->pctldev),
"failed to register pinctrl driver\n");
return dev_err_probe(dev, PTR_ERR(tp->pctldev), "failed to register pinctrl\n");
return 0;
}
drivers/pinctrl/intel/pinctrl-tigerlake.c
+31 -39
View File
@@ -28,14 +28,6 @@
#define TGL_H_GPI_IS 0x100
#define TGL_H_GPI_IE 0x120
#define TGL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define TGL_LP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP)
@@ -339,30 +331,30 @@ static const struct pinctrl_pin_desc tgllp_pins[] = {
};
static const struct intel_padgroup tgllp_community0_gpps[] = {
TGL_GPP(0, 0, 25, 0), /* GPP_B */
TGL_GPP(1, 26, 41, 32), /* GPP_T */
TGL_GPP(2, 42, 66, 64), /* GPP_A */
INTEL_GPP(0, 0, 25, 0), /* GPP_B */
INTEL_GPP(1, 26, 41, 32), /* GPP_T */
INTEL_GPP(2, 42, 66, 64), /* GPP_A */
};
static const struct intel_padgroup tgllp_community1_gpps[] = {
TGL_GPP(0, 67, 74, 96), /* GPP_S */
TGL_GPP(1, 75, 98, 128), /* GPP_H */
TGL_GPP(2, 99, 119, 160), /* GPP_D */
TGL_GPP(3, 120, 143, 192), /* GPP_U */
TGL_GPP(4, 144, 170, 224), /* vGPIO */
INTEL_GPP(0, 67, 74, 96), /* GPP_S */
INTEL_GPP(1, 75, 98, 128), /* GPP_H */
INTEL_GPP(2, 99, 119, 160), /* GPP_D */
INTEL_GPP(3, 120, 143, 192), /* GPP_U */
INTEL_GPP(4, 144, 170, 224), /* vGPIO */
};
static const struct intel_padgroup tgllp_community4_gpps[] = {
TGL_GPP(0, 171, 194, 256), /* GPP_C */
TGL_GPP(1, 195, 219, 288), /* GPP_F */
TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
TGL_GPP(3, 226, 250, 320), /* GPP_E */
TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(0, 171, 194, 256), /* GPP_C */
INTEL_GPP(1, 195, 219, 288), /* GPP_F */
INTEL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
INTEL_GPP(3, 226, 250, 320), /* GPP_E */
INTEL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_padgroup tgllp_community5_gpps[] = {
TGL_GPP(0, 260, 267, 352), /* GPP_R */
TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */
INTEL_GPP(0, 260, 267, 352), /* GPP_R */
INTEL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_community tgllp_communities[] = {
@@ -691,34 +683,34 @@ static const struct pinctrl_pin_desc tglh_pins[] = {
};
static const struct intel_padgroup tglh_community0_gpps[] = {
TGL_GPP(0, 0, 24, 0), /* GPP_A */
TGL_GPP(1, 25, 44, 32), /* GPP_R */
TGL_GPP(2, 45, 70, 64), /* GPP_B */
TGL_GPP(3, 71, 78, 96), /* vGPIO_0 */
INTEL_GPP(0, 0, 24, 0), /* GPP_A */
INTEL_GPP(1, 25, 44, 32), /* GPP_R */
INTEL_GPP(2, 45, 70, 64), /* GPP_B */
INTEL_GPP(3, 71, 78, 96), /* vGPIO_0 */
};
static const struct intel_padgroup tglh_community1_gpps[] = {
TGL_GPP(0, 79, 104, 128), /* GPP_D */
TGL_GPP(1, 105, 128, 160), /* GPP_C */
TGL_GPP(2, 129, 136, 192), /* GPP_S */
TGL_GPP(3, 137, 153, 224), /* GPP_G */
TGL_GPP(4, 154, 180, 256), /* vGPIO */
INTEL_GPP(0, 79, 104, 128), /* GPP_D */
INTEL_GPP(1, 105, 128, 160), /* GPP_C */
INTEL_GPP(2, 129, 136, 192), /* GPP_S */
INTEL_GPP(3, 137, 153, 224), /* GPP_G */
INTEL_GPP(4, 154, 180, 256), /* vGPIO */
};
static const struct intel_padgroup tglh_community3_gpps[] = {
TGL_GPP(0, 181, 193, 288), /* GPP_E */
TGL_GPP(1, 194, 217, 320), /* GPP_F */
INTEL_GPP(0, 181, 193, 288), /* GPP_E */
INTEL_GPP(1, 194, 217, 320), /* GPP_F */
};
static const struct intel_padgroup tglh_community4_gpps[] = {
TGL_GPP(0, 218, 241, 352), /* GPP_H */
TGL_GPP(1, 242, 251, 384), /* GPP_J */
TGL_GPP(2, 252, 266, 416), /* GPP_K */
INTEL_GPP(0, 218, 241, 352), /* GPP_H */
INTEL_GPP(1, 242, 251, 384), /* GPP_J */
INTEL_GPP(2, 252, 266, 416), /* GPP_K */
};
static const struct intel_padgroup tglh_community5_gpps[] = {
TGL_GPP(0, 267, 281, 448), /* GPP_I */
TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
INTEL_GPP(0, 267, 281, 448), /* GPP_I */
INTEL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_community tglh_communities[] = {
drivers/pinctrl/mediatek/Kconfig
+10
View File
@@ -181,6 +181,16 @@ config PINCTRL_MT6797
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT6878
bool "MediaTek MT6878 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
help
Say yes here to support pin controller and gpio driver
on the MediaTek MT6878 SoC.
config PINCTRL_MT6893
bool "MediaTek Dimensity MT6893 pin control"
depends on OF
drivers/pinctrl/mediatek/Makefile
+1
View File
@@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT6878) += pinctrl-mt6878.o
obj-$(CONFIG_PINCTRL_MT6893) += pinctrl-mt6893.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
drivers/pinctrl/mediatek/mtk-eint.c
+5
View File
@@ -66,6 +66,11 @@ const unsigned int debounce_time_mt6795[] = {
};
EXPORT_SYMBOL_GPL(debounce_time_mt6795);
const unsigned int debounce_time_mt6878[] = {
156, 313, 625, 1250, 20000, 40000, 80000, 160000, 320000, 640000, 0
};
EXPORT_SYMBOL_GPL(debounce_time_mt6878);
static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
unsigned int eint_num,
unsigned int offset)
drivers/pinctrl/mediatek/mtk-eint.h
+1
View File
@@ -52,6 +52,7 @@ struct mtk_eint_pin {
extern const unsigned int debounce_time_mt2701[];
extern const unsigned int debounce_time_mt6765[];
extern const unsigned int debounce_time_mt6795[];
extern const unsigned int debounce_time_mt6878[];
struct mtk_eint;
drivers/pinctrl/mediatek/pinctrl-airoha.c
+1217 -1132
View File
File diff suppressed because it is too large. Load diff
drivers/pinctrl/mediatek/pinctrl-mt6878.c
+1478
View File
File diff suppressed because it is too large. Load diff
drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h
+2248
View File
File diff suppressed because it is too large. Load diff
drivers/pinctrl/pinconf-generic.c
+47 -18
View File
@@ -54,6 +54,8 @@ static const struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true),
PCONFDUMP(PIN_CONFIG_SKEW_DELAY_INPUT_PS, "input skew delay", "ps", true),
PCONFDUMP(PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, "output skew delay", "ps", true),
};
static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
@@ -65,11 +67,12 @@ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
int i;
for (i = 0; i < nitems; i++) {
const struct pin_config_item *item = &items[i];
unsigned long config;
int ret;
/* We want to check out this parameter */
config = pinconf_to_config_packed(items[i].param, 0);
config = pinconf_to_config_packed(item->param, 0);
if (gname)
ret = pin_config_group_get(dev_name(pctldev->dev),
gname, &config);
@@ -86,15 +89,22 @@ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
if (*print_sep)
seq_puts(s, ", ");
*print_sep = 1;
seq_puts(s, items[i].display);
seq_puts(s, item->display);
/* Print unit if available */
if (items[i].has_arg) {
if (item->has_arg) {
u32 val = pinconf_to_config_argument(config);
if (items[i].format)
seq_printf(s, " (%u %s)", val, items[i].format);
if (item->format)
seq_printf(s, " (%u %s)", val, item->format);
else
seq_printf(s, " (0x%x)", val);
if (item->values && item->num_values) {
if (val < item->num_values)
seq_printf(s, " \"%s\"", item->values[val]);
else
seq_puts(s, " \"(unknown)\"");
}
}
}
}
@@ -104,7 +114,7 @@ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
* @pctldev: Pincontrol device
* @s: File to print to
* @gname: Group name specifying pins
* @pin: Pin number specyfying pin
* @pin: Pin number specifying pin
*
* Print the pinconf configuration for the requested pin(s) to @s. Pins can be
* specified either by pin using @pin or by group using @gname. Only one needs
@@ -190,6 +200,8 @@ static const struct pinconf_generic_params dt_params[] = {
{ "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
{ "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 },
{ "skew-delay-input-ps", PIN_CONFIG_SKEW_DELAY_INPUT_PS, 0 },
{ "skew-delay-output-ps", PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, 0 },
};
/**
@@ -205,10 +217,10 @@ static const struct pinconf_generic_params dt_params[] = {
* @ncfg. @ncfg is updated to reflect the number of entries after parsing. @cfg
* needs to have enough memory allocated to hold all possible entries.
*/
static void parse_dt_cfg(struct device_node *np,
const struct pinconf_generic_params *params,
unsigned int count, unsigned long *cfg,
unsigned int *ncfg)
static int parse_dt_cfg(struct device_node *np,
const struct pinconf_generic_params *params,
unsigned int count, unsigned long *cfg,
unsigned int *ncfg)
{
int i;
@@ -217,7 +229,19 @@ static void parse_dt_cfg(struct device_node *np,
int ret;
const struct pinconf_generic_params *par = &params[i];
ret = of_property_read_u32(np, par->property, &val);
if (par->values && par->num_values) {
ret = fwnode_property_match_property_string(of_fwnode_handle(np),
par->property,
par->values, par->num_values);
if (ret == -ENOENT)
return ret;
if (ret >= 0) {
val = ret;
ret = 0;
}
} else {
ret = of_property_read_u32(np, par->property, &val);
}
/* property not found */
if (ret == -EINVAL)
@@ -231,6 +255,8 @@ static void parse_dt_cfg(struct device_node *np,
cfg[*ncfg] = pinconf_to_config_packed(par->param, val);
(*ncfg)++;
}
return 0;
}
/**
@@ -242,7 +268,7 @@ static void parse_dt_cfg(struct device_node *np,
* @pmux: array with pin mux value entries
* @npins: number of pins
*
* pinmux propertity: mux value [0,7]bits and pin identity [8,31]bits.
* pinmux property: mux value [0,7]bits and pin identity [8,31]bits.
*/
int pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev,
unsigned int **pid, unsigned int **pmux,
@@ -323,13 +349,16 @@ int pinconf_generic_parse_dt_config(struct device_node *np,
if (!cfg)
return -ENOMEM;
parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg);
ret = parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg);
if (ret)
return ret;
if (pctldev && pctldev->desc->num_custom_params &&
pctldev->desc->custom_params)
parse_dt_cfg(np, pctldev->desc->custom_params,
pctldev->desc->num_custom_params, cfg, &ncfg);
ret = 0;
pctldev->desc->custom_params) {
ret = parse_dt_cfg(np, pctldev->desc->custom_params,
pctldev->desc->num_custom_params, cfg, &ncfg);
if (ret)
return ret;
}
/* no configs found at all */
if (ncfg == 0) {
drivers/pinctrl/pinctrl-mcp23s08.c
+4 -36
View File
@@ -44,17 +44,6 @@
#define MCP_GPIO 0x09
#define MCP_OLAT 0x0a
static const struct reg_default mcp23x08_defaults[] = {
{.reg = MCP_IODIR, .def = 0xff},
{.reg = MCP_IPOL, .def = 0x00},
{.reg = MCP_GPINTEN, .def = 0x00},
{.reg = MCP_DEFVAL, .def = 0x00},
{.reg = MCP_INTCON, .def = 0x00},
{.reg = MCP_IOCON, .def = 0x00},
{.reg = MCP_GPPU, .def = 0x00},
{.reg = MCP_OLAT, .def = 0x00},
};
static const struct regmap_range mcp23x08_volatile_range = {
.range_min = MCP_INTF,
.range_max = MCP_GPIO,
@@ -82,25 +71,13 @@ const struct regmap_config mcp23x08_regmap = {
.reg_stride = 1,
.volatile_table = &mcp23x08_volatile_table,
.precious_table = &mcp23x08_precious_table,
.reg_defaults = mcp23x08_defaults,
.num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
.cache_type = REGCACHE_FLAT,
.num_reg_defaults_raw = MCP_OLAT + 1,
.cache_type = REGCACHE_MAPLE,
.max_register = MCP_OLAT,
.disable_locking = true, /* mcp->lock protects the regmap */
};
EXPORT_SYMBOL_GPL(mcp23x08_regmap);
static const struct reg_default mcp23x17_defaults[] = {
{.reg = MCP_IODIR << 1, .def = 0xffff},
{.reg = MCP_IPOL << 1, .def = 0x0000},
{.reg = MCP_GPINTEN << 1, .def = 0x0000},
{.reg = MCP_DEFVAL << 1, .def = 0x0000},
{.reg = MCP_INTCON << 1, .def = 0x0000},
{.reg = MCP_IOCON << 1, .def = 0x0000},
{.reg = MCP_GPPU << 1, .def = 0x0000},
{.reg = MCP_OLAT << 1, .def = 0x0000},
};
static const struct regmap_range mcp23x17_volatile_range = {
.range_min = MCP_INTF << 1,
.range_max = MCP_GPIO << 1,
@@ -129,9 +106,8 @@ const struct regmap_config mcp23x17_regmap = {
.max_register = MCP_OLAT << 1,
.volatile_table = &mcp23x17_volatile_table,
.precious_table = &mcp23x17_precious_table,
.reg_defaults = mcp23x17_defaults,
.num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
.cache_type = REGCACHE_FLAT,
.num_reg_defaults_raw = MCP_OLAT + 1,
.cache_type = REGCACHE_MAPLE,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
.disable_locking = true, /* mcp->lock protects the regmap */
};
@@ -642,14 +618,6 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
/*
* Reset the chip - we don't really know what state it's in, so reset
* all pins to input first to prevent surprises.
*/
ret = mcp_write(mcp, MCP_IODIR, mcp->chip.ngpio == 16 ? 0xFFFF : 0xFF);
if (ret < 0)
return ret;
/* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
* and MCP_IOCON.HAEN = 1, so we work with all chips.
*/
drivers/pinctrl/pinctrl-mpfs-iomux0.c
+278
View File
@@ -0,0 +1,278 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/bitfield.h>
#include <linux/cleanup.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinctrl-utils.h"
#include "pinconf.h"
#include "pinmux.h"
#define MPFS_IOMUX0_REG 0x200
struct mpfs_iomux0_pinctrl {
struct pinctrl_dev *pctrl;
struct device *dev;
struct regmap *regmap;
struct pinctrl_desc desc;
};
struct mpfs_iomux0_pin_group {
const char *name;
const unsigned int *pins;
u32 mask;
u32 setting;
};
struct mpfs_iomux0_function {
const char *name;
const char * const *groups;
};
static const struct pinctrl_pin_desc mpfs_iomux0_pins[] = {
PINCTRL_PIN(0, "spi0"),
PINCTRL_PIN(1, "spi1"),
PINCTRL_PIN(2, "i2c0"),
PINCTRL_PIN(3, "i2c1"),
PINCTRL_PIN(4, "can0"),
PINCTRL_PIN(5, "can1"),
PINCTRL_PIN(6, "qspi"),
PINCTRL_PIN(7, "uart0"),
PINCTRL_PIN(8, "uart1"),
PINCTRL_PIN(9, "uart2"),
PINCTRL_PIN(10, "uart3"),
PINCTRL_PIN(11, "uart4"),
PINCTRL_PIN(12, "mdio0"),
PINCTRL_PIN(13, "mdio1"),
};
static const unsigned int mpfs_iomux0_spi0_pins[] = { 0 };
static const unsigned int mpfs_iomux0_spi1_pins[] = { 1 };
static const unsigned int mpfs_iomux0_i2c0_pins[] = { 2 };
static const unsigned int mpfs_iomux0_i2c1_pins[] = { 3 };
static const unsigned int mpfs_iomux0_can0_pins[] = { 4 };
static const unsigned int mpfs_iomux0_can1_pins[] = { 5 };
static const unsigned int mpfs_iomux0_qspi_pins[] = { 6 };
static const unsigned int mpfs_iomux0_uart0_pins[] = { 7 };
static const unsigned int mpfs_iomux0_uart1_pins[] = { 8 };
static const unsigned int mpfs_iomux0_uart2_pins[] = { 9 };
static const unsigned int mpfs_iomux0_uart3_pins[] = { 10 };
static const unsigned int mpfs_iomux0_uart4_pins[] = { 11 };
static const unsigned int mpfs_iomux0_mdio0_pins[] = { 12 };
static const unsigned int mpfs_iomux0_mdio1_pins[] = { 13 };
#define MPFS_IOMUX0_GROUP(_name, _mask) { \
.name = #_name "_mssio", \
.pins = mpfs_iomux0_##_name##_pins, \
.mask = _mask, \
.setting = 0x0, \
}, { \
.name = #_name "_fabric", \
.pins = mpfs_iomux0_##_name##_pins, \
.mask = _mask, \
.setting = _mask, \
}
static const struct mpfs_iomux0_pin_group mpfs_iomux0_pin_groups[] = {
MPFS_IOMUX0_GROUP(spi0, BIT(0)),
MPFS_IOMUX0_GROUP(spi1, BIT(1)),
MPFS_IOMUX0_GROUP(i2c0, BIT(2)),
MPFS_IOMUX0_GROUP(i2c1, BIT(3)),
MPFS_IOMUX0_GROUP(can0, BIT(4)),
MPFS_IOMUX0_GROUP(can1, BIT(5)),
MPFS_IOMUX0_GROUP(qspi, BIT(6)),
MPFS_IOMUX0_GROUP(uart0, BIT(7)),
MPFS_IOMUX0_GROUP(uart1, BIT(8)),
MPFS_IOMUX0_GROUP(uart2, BIT(9)),
MPFS_IOMUX0_GROUP(uart3, BIT(10)),
MPFS_IOMUX0_GROUP(uart4, BIT(11)),
MPFS_IOMUX0_GROUP(mdio0, BIT(12)),
MPFS_IOMUX0_GROUP(mdio1, BIT(13)),
};
static const char * const mpfs_iomux0_spi0_groups[] = { "spi0_mssio", "spi0_fabric" };
static const char * const mpfs_iomux0_spi1_groups[] = { "spi1_mssio", "spi1_fabric" };
static const char * const mpfs_iomux0_i2c0_groups[] = { "i2c0_mssio", "i2c0_fabric" };
static const char * const mpfs_iomux0_i2c1_groups[] = { "i2c1_mssio", "i2c1_fabric" };
static const char * const mpfs_iomux0_can0_groups[] = { "can0_mssio", "can0_fabric" };
static const char * const mpfs_iomux0_can1_groups[] = { "can1_mssio", "can1_fabric" };
static const char * const mpfs_iomux0_qspi_groups[] = { "qspi_mssio", "qspi_fabric" };
static const char * const mpfs_iomux0_uart0_groups[] = { "uart0_mssio", "uart0_fabric" };
static const char * const mpfs_iomux0_uart1_groups[] = { "uart1_mssio", "uart1_fabric" };
static const char * const mpfs_iomux0_uart2_groups[] = { "uart2_mssio", "uart2_fabric" };
static const char * const mpfs_iomux0_uart3_groups[] = { "uart3_mssio", "uart3_fabric" };
static const char * const mpfs_iomux0_uart4_groups[] = { "uart4_mssio", "uart4_fabric" };
static const char * const mpfs_iomux0_mdio0_groups[] = { "mdio0_mssio", "mdio0_fabric" };
static const char * const mpfs_iomux0_mdio1_groups[] = { "mdio1_mssio", "mdio1_fabric" };
#define MPFS_IOMUX0_FUNCTION(_name) { \
.name = #_name, \
.groups = mpfs_iomux0_##_name##_groups, \
}
static const struct mpfs_iomux0_function mpfs_iomux0_functions[] = {
MPFS_IOMUX0_FUNCTION(spi0),
MPFS_IOMUX0_FUNCTION(spi1),
MPFS_IOMUX0_FUNCTION(i2c0),
MPFS_IOMUX0_FUNCTION(i2c1),
MPFS_IOMUX0_FUNCTION(can0),
MPFS_IOMUX0_FUNCTION(can1),
MPFS_IOMUX0_FUNCTION(qspi),
MPFS_IOMUX0_FUNCTION(uart0),
MPFS_IOMUX0_FUNCTION(uart1),
MPFS_IOMUX0_FUNCTION(uart2),
MPFS_IOMUX0_FUNCTION(uart3),
MPFS_IOMUX0_FUNCTION(uart4),
MPFS_IOMUX0_FUNCTION(mdio0),
MPFS_IOMUX0_FUNCTION(mdio1),
};
static void mpfs_iomux0_pin_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
unsigned int pin)
{
struct mpfs_iomux0_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
u32 val;
seq_printf(seq, "reg: %x, pin: %u ", MPFS_IOMUX0_REG, pin);
regmap_read(pctrl->regmap, MPFS_IOMUX0_REG, &val);
val = (val & BIT(pin)) >> pin;
seq_printf(seq, "val: %x\n", val);
}
static int mpfs_iomux0_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(mpfs_iomux0_pin_groups);
}
static const char *mpfs_iomux0_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
{
return mpfs_iomux0_pin_groups[selector].name;
}
static int mpfs_iomux0_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
const unsigned int **pins, unsigned int *num_pins)
{
*pins = mpfs_iomux0_pin_groups[selector].pins;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops mpfs_iomux0_pinctrl_ops = {
.get_groups_count = mpfs_iomux0_groups_count,
.get_group_name = mpfs_iomux0_group_name,
.get_group_pins = mpfs_iomux0_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
.pin_dbg_show = mpfs_iomux0_pin_dbg_show,
};
static int mpfs_iomux0_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel,
unsigned int gsel)
{
struct mpfs_iomux0_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
struct device *dev = pctrl->dev;
const struct mpfs_iomux0_pin_group *group;
const struct mpfs_iomux0_function *function;
group = &mpfs_iomux0_pin_groups[gsel];
function = &mpfs_iomux0_functions[fsel];
dev_dbg(dev, "Setting func %s mask %x setting %x\n",
function->name, group->mask, group->setting);
regmap_assign_bits(pctrl->regmap, MPFS_IOMUX0_REG, group->mask, group->setting);
return 0;
}
static int mpfs_iomux0_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(mpfs_iomux0_functions);
}
static const char *mpfs_iomux0_pinmux_get_func_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return mpfs_iomux0_functions[selector].name;
}
static int mpfs_iomux0_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
*groups = mpfs_iomux0_functions[selector].groups;
*num_groups = 2;
return 0;
}
static const struct pinmux_ops mpfs_iomux0_pinmux_ops = {
.get_functions_count = mpfs_iomux0_pinmux_get_funcs_count,
.get_function_name = mpfs_iomux0_pinmux_get_func_name,
.get_function_groups = mpfs_iomux0_pinmux_get_groups,
.set_mux = mpfs_iomux0_pinmux_set_mux,
};
static int mpfs_iomux0_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mpfs_iomux0_pinctrl *pctrl;
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
if (IS_ERR(pctrl->regmap))
dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
pctrl->desc.name = dev_name(dev);
pctrl->desc.pins = mpfs_iomux0_pins;
pctrl->desc.npins = ARRAY_SIZE(mpfs_iomux0_pins);
pctrl->desc.pctlops = &mpfs_iomux0_pinctrl_ops;
pctrl->desc.pmxops = &mpfs_iomux0_pinmux_ops;
pctrl->desc.owner = THIS_MODULE;
pctrl->dev = dev;
platform_set_drvdata(pdev, pctrl);
pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
if (IS_ERR(pctrl->pctrl))
return PTR_ERR(pctrl->pctrl);
return 0;
}
static const struct of_device_id mpfs_iomux0_of_match[] = {
{ .compatible = "microchip,mpfs-pinctrl-iomux0" },
{ }
};
MODULE_DEVICE_TABLE(of, mpfs_iomux0_of_match);
static struct platform_driver mpfs_iomux0_driver = {
.driver = {
.name = "mpfs-pinctrl-iomux0",
.of_match_table = mpfs_iomux0_of_match,
},
.probe = mpfs_iomux0_probe,
};
module_platform_driver(mpfs_iomux0_driver);
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
MODULE_DESCRIPTION("Polarfire SoC iomux0 pinctrl driver");
MODULE_LICENSE("GPL");
drivers/pinctrl/pinctrl-pic64gx-gpio2.c
+356
View File
@@ -0,0 +1,356 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-utils.h"
#define PIC64GX_PINMUX_REG 0x0
static const struct regmap_config pic64gx_gpio2_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
.max_register = 0x0,
};
struct pic64gx_gpio2_pinctrl {
struct pinctrl_dev *pctrl;
struct device *dev;
struct regmap *regmap;
struct pinctrl_desc desc;
};
struct pic64gx_gpio2_pin_group {
const char *name;
const unsigned int *pins;
const unsigned int num_pins;
u32 mask;
u32 setting;
};
struct pic64gx_gpio2_function {
const char *name;
const char * const *groups;
const unsigned int num_groups;
};
static const struct pinctrl_pin_desc pic64gx_gpio2_pins[] = {
PINCTRL_PIN(0, "E14"),
PINCTRL_PIN(1, "E15"),
PINCTRL_PIN(2, "F16"),
PINCTRL_PIN(3, "F17"),
PINCTRL_PIN(4, "D19"),
PINCTRL_PIN(5, "B18"),
PINCTRL_PIN(6, "B10"),
PINCTRL_PIN(7, "C14"),
PINCTRL_PIN(8, "E18"),
PINCTRL_PIN(9, "D18"),
PINCTRL_PIN(10, "E19"),
PINCTRL_PIN(11, "C7"),
PINCTRL_PIN(12, "D6"),
PINCTRL_PIN(13, "D7"),
PINCTRL_PIN(14, "C9"),
PINCTRL_PIN(15, "C10"),
PINCTRL_PIN(16, "A5"),
PINCTRL_PIN(17, "A6"),
PINCTRL_PIN(18, "D8"),
PINCTRL_PIN(19, "D9"),
PINCTRL_PIN(20, "B8"),
PINCTRL_PIN(21, "A8"),
PINCTRL_PIN(22, "C12"),
PINCTRL_PIN(23, "B12"),
PINCTRL_PIN(24, "A11"),
PINCTRL_PIN(25, "A10"),
PINCTRL_PIN(26, "D11"),
PINCTRL_PIN(27, "C11"),
PINCTRL_PIN(28, "B9"),
};
static const unsigned int pic64gx_gpio2_mdio0_pins[] = {
0, 1
};
static const unsigned int pic64gx_gpio2_mdio1_pins[] = {
2, 3
};
static const unsigned int pic64gx_gpio2_spi0_pins[] = {
4, 5, 10, 11
};
static const unsigned int pic64gx_gpio2_can0_pins[] = {
6, 24, 28
};
static const unsigned int pic64gx_gpio2_pcie_pins[] = {
7, 8, 9
};
static const unsigned int pic64gx_gpio2_qspi_pins[] = {
12, 13, 14, 15, 16, 17
};
static const unsigned int pic64gx_gpio2_uart3_pins[] = {
18, 19
};
static const unsigned int pic64gx_gpio2_uart4_pins[] = {
20, 21
};
static const unsigned int pic64gx_gpio2_can1_pins[] = {
22, 23, 25
};
static const unsigned int pic64gx_gpio2_uart2_pins[] = {
26, 27
};
#define PIC64GX_PINCTRL_GROUP(_name, _mask) { \
.name = "gpio_" #_name, \
.pins = pic64gx_gpio2_##_name##_pins, \
.num_pins = ARRAY_SIZE(pic64gx_gpio2_##_name##_pins), \
.mask = _mask, \
.setting = 0x0, \
}, { \
.name = #_name, \
.pins = pic64gx_gpio2_##_name##_pins, \
.num_pins = ARRAY_SIZE(pic64gx_gpio2_##_name##_pins), \
.mask = _mask, \
.setting = _mask, \
}
static const struct pic64gx_gpio2_pin_group pic64gx_gpio2_pin_groups[] = {
PIC64GX_PINCTRL_GROUP(mdio0, BIT(0) | BIT(1)),
PIC64GX_PINCTRL_GROUP(mdio1, BIT(2) | BIT(3)),
PIC64GX_PINCTRL_GROUP(spi0, BIT(4) | BIT(5) | BIT(10) | BIT(11)),
PIC64GX_PINCTRL_GROUP(can0, BIT(6) | BIT(24) | BIT(28)),
PIC64GX_PINCTRL_GROUP(pcie, BIT(7) | BIT(8) | BIT(9)),
PIC64GX_PINCTRL_GROUP(qspi, GENMASK(17, 12)),
PIC64GX_PINCTRL_GROUP(uart3, BIT(18) | BIT(19)),
PIC64GX_PINCTRL_GROUP(uart4, BIT(20) | BIT(21)),
PIC64GX_PINCTRL_GROUP(can1, BIT(22) | BIT(23) | BIT(25)),
PIC64GX_PINCTRL_GROUP(uart2, BIT(26) | BIT(27)),
};
static const char * const pic64gx_gpio2_gpio_groups[] = {
"gpio_mdio0", "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie",
"gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1", "gpio_uart2"
};
static const char * const pic64gx_gpio2_mdio0_groups[] = {
"mdio0"
};
static const char * const pic64gx_gpio2_mdio1_groups[] = {
"mdio1"
};
static const char * const pic64gx_gpio2_spi0_groups[] = {
"spi0"
};
static const char * const pic64gx_gpio2_can0_groups[] = {
"can0"
};
static const char * const pic64gx_gpio2_pcie_groups[] = {
"pcie"
};
static const char * const pic64gx_gpio2_qspi_groups[] = {
"qspi"
};
static const char * const pic64gx_gpio2_uart3_groups[] = {
"uart3"
};
static const char * const pic64gx_gpio2_uart4_groups[] = {
"uart4"
};
static const char * const pic64gx_gpio2_can1_groups[] = {
"can1"
};
static const char * const pic64gx_gpio2_uart2_groups[] = {
"uart2"
};
#define PIC64GX_PINCTRL_FUNCTION(_name) { \
.name = #_name, \
.groups = pic64gx_gpio2_##_name##_groups, \
.num_groups = ARRAY_SIZE(pic64gx_gpio2_##_name##_groups), \
}
static const struct pic64gx_gpio2_function pic64gx_gpio2_functions[] = {
PIC64GX_PINCTRL_FUNCTION(gpio),
PIC64GX_PINCTRL_FUNCTION(mdio0),
PIC64GX_PINCTRL_FUNCTION(mdio1),
PIC64GX_PINCTRL_FUNCTION(spi0),
PIC64GX_PINCTRL_FUNCTION(can0),
PIC64GX_PINCTRL_FUNCTION(pcie),
PIC64GX_PINCTRL_FUNCTION(qspi),
PIC64GX_PINCTRL_FUNCTION(uart3),
PIC64GX_PINCTRL_FUNCTION(uart4),
PIC64GX_PINCTRL_FUNCTION(can1),
PIC64GX_PINCTRL_FUNCTION(uart2),
};
static void pic64gx_gpio2_pin_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
unsigned int pin)
{
struct pic64gx_gpio2_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
u32 val;
regmap_read(pctrl->regmap, PIC64GX_PINMUX_REG, &val);
val = (val & BIT(pin)) >> pin;
seq_printf(seq, "pin: %u val: %x\n", pin, val);
}
static int pic64gx_gpio2_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(pic64gx_gpio2_pin_groups);
}
static const char *pic64gx_gpio2_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
{
return pic64gx_gpio2_pin_groups[selector].name;
}
static int pic64gx_gpio2_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
const unsigned int **pins, unsigned int *num_pins)
{
*pins = pic64gx_gpio2_pin_groups[selector].pins;
*num_pins = pic64gx_gpio2_pin_groups[selector].num_pins;
return 0;
}
static const struct pinctrl_ops pic64gx_gpio2_pinctrl_ops = {
.get_groups_count = pic64gx_gpio2_groups_count,
.get_group_name = pic64gx_gpio2_group_name,
.get_group_pins = pic64gx_gpio2_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
.pin_dbg_show = pic64gx_gpio2_pin_dbg_show,
};
static int pic64gx_gpio2_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(pic64gx_gpio2_functions);
}
static const char *pic64gx_gpio2_pinmux_get_func_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return pic64gx_gpio2_functions[selector].name;
}
static int pic64gx_gpio2_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
*groups = pic64gx_gpio2_functions[selector].groups;
*num_groups = pic64gx_gpio2_functions[selector].num_groups;
return 0;
}
static int pic64gx_gpio2_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel,
unsigned int gsel)
{
struct pic64gx_gpio2_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
struct device *dev = pctrl->dev;
const struct pic64gx_gpio2_pin_group *group;
const struct pic64gx_gpio2_function *function;
group = &pic64gx_gpio2_pin_groups[gsel];
function = &pic64gx_gpio2_functions[fsel];
dev_dbg(dev, "Setting func %s mask %x setting %x\n",
function->name, group->mask, group->setting);
regmap_assign_bits(pctrl->regmap, PIC64GX_PINMUX_REG, group->mask, group->setting);
return 0;
}
static const struct pinmux_ops pic64gx_gpio2_pinmux_ops = {
.get_functions_count = pic64gx_gpio2_pinmux_get_funcs_count,
.get_function_name = pic64gx_gpio2_pinmux_get_func_name,
.get_function_groups = pic64gx_gpio2_pinmux_get_groups,
.set_mux = pic64gx_gpio2_pinmux_set_mux,
};
static int pic64gx_gpio2_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct pic64gx_gpio2_pinctrl *pctrl;
void __iomem *base;
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
dev_err(dev, "Failed get resource\n");
return PTR_ERR(base);
}
pctrl->regmap = devm_regmap_init_mmio(dev, base, &pic64gx_gpio2_regmap_config);
if (IS_ERR(pctrl->regmap)) {
dev_err(dev, "Failed to map regmap\n");
return PTR_ERR(pctrl->regmap);
}
pctrl->desc.name = dev_name(dev);
pctrl->desc.pins = pic64gx_gpio2_pins;
pctrl->desc.npins = ARRAY_SIZE(pic64gx_gpio2_pins);
pctrl->desc.pctlops = &pic64gx_gpio2_pinctrl_ops;
pctrl->desc.pmxops = &pic64gx_gpio2_pinmux_ops;
pctrl->desc.owner = THIS_MODULE;
pctrl->dev = dev;
platform_set_drvdata(pdev, pctrl);
pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
if (IS_ERR(pctrl->pctrl))
return PTR_ERR(pctrl->pctrl);
return 0;
}
static const struct of_device_id pic64gx_gpio2_of_match[] = {
{ .compatible = "microchip,pic64gx-pinctrl-gpio2" },
{ }
};
MODULE_DEVICE_TABLE(of, pic64gx_gpio2_of_match);
static struct platform_driver pic64gx_gpio2_driver = {
.driver = {
.name = "pic64gx-pinctrl-gpio2",
.of_match_table = pic64gx_gpio2_of_match,
},
.probe = pic64gx_gpio2_probe,
};
module_platform_driver(pic64gx_gpio2_driver);
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
MODULE_DESCRIPTION("pic64gx gpio2 pinctrl driver");
MODULE_LICENSE("GPL");
drivers/pinctrl/pinctrl-rockchip.c
+434 -8
View File
@@ -105,6 +105,29 @@
.pull_type[3] = pull3, \
}
#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0, \
iom1, iom2, iom3, \
offset0, offset1, \
offset2, offset3, drv0, \
drv1, drv2, drv3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = offset0 }, \
{ .type = iom1, .offset = offset1 }, \
{ .type = iom2, .offset = offset2 }, \
{ .type = iom3, .offset = offset3 }, \
}, \
.drv = { \
{ .drv_type = drv0, .offset = -1 }, \
{ .drv_type = drv1, .offset = -1 }, \
{ .drv_type = drv2, .offset = -1 }, \
{ .drv_type = drv3, .offset = -1 }, \
}, \
}
#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
{ \
.bank_num = id, \
@@ -233,6 +256,35 @@
.pull_type[3] = pull3, \
}
#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(id, pins, \
label, iom0, iom1, \
iom2, iom3, offset0, \
offset1, offset2, \
offset3, drv0, drv1, \
drv2, drv3, pull0, \
pull1, pull2, pull3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = offset0 }, \
{ .type = iom1, .offset = offset1 }, \
{ .type = iom2, .offset = offset2 }, \
{ .type = iom3, .offset = offset3 }, \
}, \
.drv = { \
{ .drv_type = drv0, .offset = -1 }, \
{ .drv_type = drv1, .offset = -1 }, \
{ .drv_type = drv2, .offset = -1 }, \
{ .drv_type = drv3, .offset = -1 }, \
}, \
.pull_type[0] = pull0, \
.pull_type[1] = pull1, \
.pull_type[2] = pull2, \
.pull_type[3] = pull3, \
}
#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
{ \
.bank_num = ID, \
@@ -1120,6 +1172,13 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
else
regmap = info->regmap_base;
if (ctrl->type == RK3506) {
if (bank->bank_num == 1)
regmap = info->regmap_ioc1;
else if (bank->bank_num == 4)
return 0;
}
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
@@ -1239,6 +1298,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
else
regmap = info->regmap_base;
if (ctrl->type == RK3506) {
if (bank->bank_num == 1)
regmap = info->regmap_ioc1;
else if (bank->bank_num == 4)
return 0;
}
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
@@ -2003,6 +2069,262 @@ static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RK3506_DRV_BITS_PER_PIN 8
#define RK3506_DRV_PINS_PER_REG 2
#define RK3506_DRV_GPIO0_A_OFFSET 0x100
#define RK3506_DRV_GPIO0_D_OFFSET 0x830
#define RK3506_DRV_GPIO1_OFFSET 0x140
#define RK3506_DRV_GPIO2_OFFSET 0x180
#define RK3506_DRV_GPIO3_OFFSET 0x1c0
#define RK3506_DRV_GPIO4_OFFSET 0x840
static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int ret = 0;
switch (bank->bank_num) {
case 0:
*regmap = info->regmap_pmu;
if (pin_num > 24) {
ret = -EINVAL;
} else if (pin_num < 24) {
*reg = RK3506_DRV_GPIO0_A_OFFSET;
} else {
*reg = RK3506_DRV_GPIO0_D_OFFSET;
*bit = 3;
return 0;
}
break;
case 1:
*regmap = info->regmap_ioc1;
if (pin_num < 28)
*reg = RK3506_DRV_GPIO1_OFFSET;
else
ret = -EINVAL;
break;
case 2:
*regmap = info->regmap_base;
if (pin_num < 17)
*reg = RK3506_DRV_GPIO2_OFFSET;
else
ret = -EINVAL;
break;
case 3:
*regmap = info->regmap_base;
if (pin_num < 15)
*reg = RK3506_DRV_GPIO3_OFFSET;
else
ret = -EINVAL;
break;
case 4:
*regmap = info->regmap_base;
if (pin_num < 8 || pin_num > 11) {
ret = -EINVAL;
} else {
*reg = RK3506_DRV_GPIO4_OFFSET;
*bit = 10;
return 0;
}
break;
default:
ret = -EINVAL;
break;
}
if (ret) {
dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
return ret;
}
*reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RK3506_DRV_PINS_PER_REG;
*bit *= RK3506_DRV_BITS_PER_PIN;
return 0;
}
#define RK3506_PULL_BITS_PER_PIN 2
#define RK3506_PULL_PINS_PER_REG 8
#define RK3506_PULL_GPIO0_A_OFFSET 0x200
#define RK3506_PULL_GPIO0_D_OFFSET 0x830
#define RK3506_PULL_GPIO1_OFFSET 0x210
#define RK3506_PULL_GPIO2_OFFSET 0x220
#define RK3506_PULL_GPIO3_OFFSET 0x230
#define RK3506_PULL_GPIO4_OFFSET 0x840
static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int ret = 0;
switch (bank->bank_num) {
case 0:
*regmap = info->regmap_pmu;
if (pin_num > 24) {
ret = -EINVAL;
} else if (pin_num < 24) {
*reg = RK3506_PULL_GPIO0_A_OFFSET;
} else {
*reg = RK3506_PULL_GPIO0_D_OFFSET;
*bit = 5;
return 0;
}
break;
case 1:
*regmap = info->regmap_ioc1;
if (pin_num < 28)
*reg = RK3506_PULL_GPIO1_OFFSET;
else
ret = -EINVAL;
break;
case 2:
*regmap = info->regmap_base;
if (pin_num < 17)
*reg = RK3506_PULL_GPIO2_OFFSET;
else
ret = -EINVAL;
break;
case 3:
*regmap = info->regmap_base;
if (pin_num < 15)
*reg = RK3506_PULL_GPIO3_OFFSET;
else
ret = -EINVAL;
break;
case 4:
*regmap = info->regmap_base;
if (pin_num < 8 || pin_num > 11) {
ret = -EINVAL;
} else {
*reg = RK3506_PULL_GPIO4_OFFSET;
*bit = 13;
return 0;
}
break;
default:
ret = -EINVAL;
break;
}
if (ret) {
dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
return ret;
}
*reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3506_PULL_PINS_PER_REG;
*bit *= RK3506_PULL_BITS_PER_PIN;
return 0;
}
#define RK3506_SMT_BITS_PER_PIN 1
#define RK3506_SMT_PINS_PER_REG 8
#define RK3506_SMT_GPIO0_A_OFFSET 0x400
#define RK3506_SMT_GPIO0_D_OFFSET 0x830
#define RK3506_SMT_GPIO1_OFFSET 0x410
#define RK3506_SMT_GPIO2_OFFSET 0x420
#define RK3506_SMT_GPIO3_OFFSET 0x430
#define RK3506_SMT_GPIO4_OFFSET 0x840
static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int ret = 0;
switch (bank->bank_num) {
case 0:
*regmap = info->regmap_pmu;
if (pin_num > 24) {
ret = -EINVAL;
} else if (pin_num < 24) {
*reg = RK3506_SMT_GPIO0_A_OFFSET;
} else {
*reg = RK3506_SMT_GPIO0_D_OFFSET;
*bit = 9;
return 0;
}
break;
case 1:
*regmap = info->regmap_ioc1;
if (pin_num < 28)
*reg = RK3506_SMT_GPIO1_OFFSET;
else
ret = -EINVAL;
break;
case 2:
*regmap = info->regmap_base;
if (pin_num < 17)
*reg = RK3506_SMT_GPIO2_OFFSET;
else
ret = -EINVAL;
break;
case 3:
*regmap = info->regmap_base;
if (pin_num < 15)
*reg = RK3506_SMT_GPIO3_OFFSET;
else
ret = -EINVAL;
break;
case 4:
*regmap = info->regmap_base;
if (pin_num < 8 || pin_num > 11) {
ret = -EINVAL;
} else {
*reg = RK3506_SMT_GPIO4_OFFSET;
*bit = 8;
return 0;
}
break;
default:
ret = -EINVAL;
break;
}
if (ret) {
dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
return ret;
}
*reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4);
*bit = pin_num % RK3506_SMT_PINS_PER_REG;
*bit *= RK3506_SMT_BITS_PER_PIN;
return 0;
}
#define RK3528_DRV_BITS_PER_PIN 8
#define RK3528_DRV_PINS_PER_REG 2
#define RK3528_DRV_GPIO0_OFFSET 0x100
@@ -2749,7 +3071,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
rmask_bits = RK3588_DRV_BITS_PER_PIN;
ret = strength;
goto config;
} else if (ctrl->type == RK3528 ||
} else if (ctrl->type == RK3506 ||
ctrl->type == RK3528 ||
ctrl->type == RK3562 ||
ctrl->type == RK3568) {
rmask_bits = RK3568_DRV_BITS_PER_PIN;
@@ -2828,12 +3151,37 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
case DRV_TYPE_IO_1V8_ONLY:
rmask_bits = RK3288_DRV_BITS_PER_PIN;
break;
case DRV_TYPE_IO_LEVEL_2_BIT:
ret = regmap_read(regmap, reg, &data);
if (ret)
return ret;
data >>= bit;
return data & 0x3;
case DRV_TYPE_IO_LEVEL_8_BIT:
ret = regmap_read(regmap, reg, &data);
if (ret)
return ret;
data >>= bit;
data &= (1 << 8) - 1;
ret = hweight8(data);
if (ret > 0)
return ret - 1;
else
return -EINVAL;
default:
dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
return -EINVAL;
}
config:
if (ctrl->type == RK3506) {
if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
rmask_bits = 2;
ret = strength;
}
}
/* enable the write to the equivalent lower bits */
data = ((1 << rmask_bits) - 1) << (bit + 16);
rmask = data | (data >> 16);
@@ -2957,6 +3305,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3328:
case RK3368:
case RK3399:
case RK3506:
case RK3528:
case RK3562:
case RK3568:
@@ -3077,6 +3426,10 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
break;
}
if (ctrl->type == RK3506)
if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4)
return data & 0x3;
return data & 0x1;
}
@@ -3112,6 +3465,14 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
break;
}
if (ctrl->type == RK3506) {
if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
data = 0x3 << (bit + 16);
rmask = data | (data >> 16);
data |= ((enable ? 0x3 : 0) << bit);
}
}
return regmap_update_bits(regmap, reg, rmask, data);
}
@@ -3227,6 +3588,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
case RK3328:
case RK3368:
case RK3399:
case RK3506:
case RK3528:
case RK3562:
case RK3568:
@@ -3880,13 +4242,10 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
}
/* try to find the optional reference to the pmu syscon */
node = of_parse_phandle(np, "rockchip,pmu", 0);
if (node) {
info->regmap_pmu = syscon_node_to_regmap(node);
of_node_put(node);
if (IS_ERR(info->regmap_pmu))
return PTR_ERR(info->regmap_pmu);
}
info->regmap_pmu = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,pmu");
/* try to find the optional reference to the ioc1 syscon */
info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1");
ret = rockchip_pinctrl_register(pdev, info);
if (ret)
@@ -4350,6 +4709,71 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
};
static struct rockchip_pin_bank rk3506_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(0, 32, "gpio0",
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_2BIT | IOMUX_SOURCE_PMU,
0x0, 0x8, 0x10, 0x830,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_2_BIT,
0, 0, 0, 1),
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x20, 0x28, 0x30, 0x38,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT),
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x40, 0x48, 0x50, 0x58,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT),
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x60, 0x68, 0x70, 0x78,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT),
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(4, 32, "gpio4",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x80, 0x88, 0x90, 0x98,
DRV_TYPE_IO_LEVEL_2_BIT,
DRV_TYPE_IO_LEVEL_2_BIT,
DRV_TYPE_IO_LEVEL_2_BIT,
DRV_TYPE_IO_LEVEL_2_BIT,
1, 1, 1, 1),
};
static struct rockchip_pin_ctrl rk3506_pin_ctrl __maybe_unused = {
.pin_banks = rk3506_pin_banks,
.nr_banks = ARRAY_SIZE(rk3506_pin_banks),
.label = "RK3506-GPIO",
.type = RK3506,
.pull_calc_reg = rk3506_calc_pull_reg_and_bit,
.drv_calc_reg = rk3506_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk3506_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk3528_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
IOMUX_WIDTH_4BIT,
@@ -4560,6 +4984,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &rk3368_pin_ctrl },
{ .compatible = "rockchip,rk3399-pinctrl",
.data = &rk3399_pin_ctrl },
{ .compatible = "rockchip,rk3506-pinctrl",
.data = &rk3506_pin_ctrl },
{ .compatible = "rockchip,rk3528-pinctrl",
.data = &rk3528_pin_ctrl },
{ .compatible = "rockchip,rk3562-pinctrl",
drivers/pinctrl/pinctrl-rockchip.h
+4
View File
@@ -196,6 +196,7 @@ enum rockchip_pinctrl_type {
RK3328,
RK3368,
RK3399,
RK3506,
RK3528,
RK3562,
RK3568,
@@ -260,6 +261,8 @@ enum rockchip_pin_drv_type {
DRV_TYPE_IO_1V8_ONLY,
DRV_TYPE_IO_1V8_3V0_AUTO,
DRV_TYPE_IO_3V3_ONLY,
DRV_TYPE_IO_LEVEL_2_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_MAX
};
@@ -458,6 +461,7 @@ struct rockchip_pinctrl {
int reg_size;
struct regmap *regmap_pull;
struct regmap *regmap_pmu;
struct regmap *regmap_ioc1;
struct device *dev;
struct rockchip_pin_ctrl *ctrl;
struct pinctrl_desc pctl;
drivers/pinctrl/pinctrl-scmi.c
-2
View File
@@ -40,8 +40,6 @@ struct scmi_pinctrl {
struct pinctrl_desc pctl_desc;
struct pinfunction *functions;
unsigned int nr_functions;
struct pinctrl_pin_desc *pins;
unsigned int nr_pins;
};
static int pinctrl_scmi_get_groups_count(struct pinctrl_dev *pctldev)
drivers/pinctrl/pinctrl-single.c
+4 -3
View File
@@ -485,7 +485,8 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
struct pcs_function *func;
enum pin_config_param param;
unsigned offset = 0, data = 0, i, j, ret;
unsigned offset = 0, data = 0, i, j;
int ret;
ret = pcs_get_function(pctldev, pin, &func);
if (ret)
@@ -549,9 +550,9 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
{
struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
struct pcs_function *func;
unsigned offset = 0, shift = 0, i, data, ret;
unsigned offset = 0, shift = 0, i, data;
u32 arg;
int j;
int j, ret;
enum pin_config_param param;
ret = pcs_get_function(pctldev, pin, &func);
drivers/pinctrl/qcom/Kconfig.msm
+8
View File
@@ -92,6 +92,14 @@ config PINCTRL_IPQ9574
Qualcomm Technologies Inc. IPQ9574 platform. Select this for
IPQ9574.
config PINCTRL_KAANAPALI
tristate "Qualcomm Technologies Inc Kaanapali pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc Kaanapali platform.
config PINCTRL_MSM8226
tristate "Qualcomm 8226 pin controller driver"
depends on ARM || COMPILE_TEST
drivers/pinctrl/qcom/Makefile
+1
View File
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o
obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o
obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
drivers/pinctrl/qcom/pinctrl-glymur.c
+3 -3
View File
@@ -1316,7 +1316,7 @@ static const char *const wcn_sw_ctrl_groups[] = {
};
static const struct pinfunction glymur_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_GPIO_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(resout_gpio_n),
MSM_PIN_FUNCTION(aoss_cti),
MSM_PIN_FUNCTION(asc_cci),
@@ -1342,7 +1342,7 @@ static const struct pinfunction glymur_functions[] = {
MSM_PIN_FUNCTION(edp0_hot),
MSM_PIN_FUNCTION(edp0_lcd),
MSM_PIN_FUNCTION(edp1_lcd),
MSM_PIN_FUNCTION(egpio),
MSM_GPIO_PIN_FUNCTION(egpio),
MSM_PIN_FUNCTION(eusb_ac_en),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
@@ -1743,7 +1743,7 @@ static const struct msm_pinctrl_soc_data glymur_tlmm = {
};
static const struct of_device_id glymur_tlmm_of_match[] = {
{ .compatible = "qcom,glymur-tlmm", .data = &glymur_tlmm },
{ .compatible = "qcom,glymur-tlmm", },
{ }
};
drivers/pinctrl/qcom/pinctrl-kaanapali.c
+1803
View File
File diff suppressed because it is too large. Load diff
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+9
View File
@@ -42,6 +42,8 @@
#define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
#define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2 0x12
#define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3 0x13
#define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2_CLK 0x14
#define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3_CLK 0x15
#define PMIC_MPP_REG_RT_STS 0x10
#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
@@ -852,11 +854,13 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
pad->lv_mv_type = true;
break;
case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2:
case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2_CLK:
pad->num_sources = 2;
pad->have_buffer = true;
pad->lv_mv_type = true;
break;
case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3:
case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3_CLK:
pad->num_sources = 3;
pad->have_buffer = true;
pad->lv_mv_type = true;
@@ -1239,7 +1243,11 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 },
{ .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmh0101-gpio", .data = (void *)18 },
{ .compatible = "qcom,pmh0104-gpio", .data = (void *)8 },
{ .compatible = "qcom,pmh0110-gpio", .data = (void *)14 },
{ .compatible = "qcom,pmi632-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
@@ -1248,6 +1256,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pmiv0104-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 },
{ .compatible = "qcom,pmk8850-gpio", .data = (void *)8 },
{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmm8654au-gpio", .data = (void *) 12 },
/* pmp8074 has 12 GPIOs with holes on 1 and 12 */
drivers/pinctrl/renesas/pfc-emev2.c
-1
View File
@@ -666,7 +666,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART2_TX, SEL_UART_1_0_01),
};
#define EMEV_MUX_PIN(name, pin, mark) \
static const unsigned int name##_pins[] = { pin }; \
static const unsigned int name##_mux[] = { mark##_MARK }
drivers/pinctrl/renesas/pfc-r8a73a4.c
-2
View File
@@ -85,7 +85,6 @@
/* Port320 - Port329 */ \
PORT_10(320, fn, pfx##32, sfx)
enum {
PINMUX_RESERVED = 0,
@@ -227,7 +226,6 @@ enum {
PINMUX_MARK_BEGIN,
#define F1(a) a##_MARK
#define F2(a) a##_MARK
#define F3(a) a##_MARK
drivers/pinctrl/renesas/pfc-r8a7778.c
-1
View File
@@ -1994,7 +1994,6 @@ static const char * const scif5_groups[] = {
"scif5_data_b",
};
static const char * const sdhi0_groups[] = {
"sdhi0_cd",
"sdhi0_ctrl",
drivers/pinctrl/renesas/pfc-r8a77951.c
-1
View File
@@ -249,7 +249,6 @@
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
drivers/pinctrl/renesas/pfc-r8a7796.c
-1
View File
@@ -254,7 +254,6 @@
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
drivers/pinctrl/renesas/pfc-r8a77965.c
-1
View File
@@ -254,7 +254,6 @@
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
drivers/pinctrl/renesas/pfc-r8a77970.c
-1
View File
@@ -159,7 +159,6 @@
#define GPSR5_1 FM(QSPI0_MOSI_IO0)
#define GPSR5_0 FM(QSPI0_SPCLK)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
drivers/pinctrl/renesas/pfc-r8a77980.c
-1
View File
@@ -193,7 +193,6 @@
#define GPSR5_1 FM(QSPI0_MOSI_IO0)
#define GPSR5_0 FM(QSPI0_SPCLK)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
drivers/pinctrl/renesas/pfc-r8a77995.c
-2
View File
@@ -427,7 +427,6 @@ FM(IP12_31_28) IP12_31_28 \
#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
#define PINMUX_MOD_SELS \
\
MOD_SEL1_31 \
@@ -2869,7 +2868,6 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ }
};
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
switch (pin) {
drivers/pinctrl/renesas/pfc-r8a779f0.c
-1
View File
@@ -652,7 +652,6 @@ static const unsigned int i2c5_mux[] = {
SDA5_MARK, SCL5_MARK,
};
/* - INTC-EX ---------------------------------------------------------------- */
static const unsigned int intc_ex_irq0_pins[] = {
/* IRQ0 */
drivers/pinctrl/renesas/pfc-r8a779g0.c
+33 -67
View File
@@ -352,7 +352,7 @@
#define IP1SR2_3_0 FM(TPU0TO0_A) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_15_12 FM(CANFD0_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -471,55 +471,55 @@
#define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_19_16 FM(AVB1_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_27_24 FM(AVB1_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_31_28 FM(AVB1_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_3_0 FM(AVB1_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_7_4 FM(AVB1_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_19_16 FM(AVB1_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_23_20 FM(AVB1_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_27_24 FM(AVB1_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_31_28 FM(AVB1_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_3_0 FM(AVB1_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_7_4 FM(AVB1_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_11_8 FM(AVB1_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_15_12 FM(AVB1_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR7 */
/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_15_12 FM(AVB0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_19_16 FM(AVB0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_27_24 FM(AVB0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_31_28 FM(AVB0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_3_0 FM(AVB0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_15_12 FM(AVB0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_19_16 FM(AVB0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_31_28 FM(AVB0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_3_0 FM(AVB0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_7_4 FM(AVB0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_11_8 FM(AVB0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_15_12 FM(AVB0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_19_16 FM(AVB0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR8 */
/* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -925,7 +925,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B),
PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A),
@@ -1076,118 +1075,85 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
/* IP1SR6 */
PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC),
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0),
PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
/* IP2SR6 */
PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
/* IP0SR7 */
PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),
PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),
PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),
PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),
PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),
PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),
PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),
PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),
PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),
/* IP1SR7 */
PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),
PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),
PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),
PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),
PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),
PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),
PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),
/* IP2SR7 */
PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),
PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),
PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0),
PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0),
PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC),
PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC),
PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL),
PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),
/* IP0SR8 */
PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
drivers/pinctrl/renesas/pfc-r8a779h0.c
+2 -5
View File
@@ -259,7 +259,6 @@
#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
/* SR0 */
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -340,7 +339,7 @@
#define IP1SR2_3_0 FM(TPU0TO0_A) F_(0, 0) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_15_12 FM(CANFD0_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -479,7 +478,7 @@
/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -866,7 +865,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B),
PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A),
@@ -1124,7 +1122,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),
PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),
PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),
PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
drivers/pinctrl/renesas/pfc-sh7723.c
-1
View File
@@ -182,7 +182,6 @@ enum {
PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
PSA15_PSA14_FN1, PSA15_PSA14_FN2,
PSA13_PSA12_FN1, PSA13_PSA12_FN2,
PSA11_PSA10_FN1, PSA11_PSA10_FN2,
drivers/pinctrl/renesas/pfc-sh7724.c
-1
View File
@@ -210,7 +210,6 @@ enum {
PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
PSA15_0, PSA15_1,
PSA14_0, PSA14_1,
PSA13_0, PSA13_1,
drivers/pinctrl/renesas/pfc-sh7734.c
-1
View File
@@ -664,7 +664,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
/* IPSR1 */
PINMUX_IPSR_GPSR(IP1_1_0, A16),
PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM),
drivers/pinctrl/renesas/pinctrl-rza1.c
+3 -4
View File
@@ -526,7 +526,6 @@ static inline int rza1_pinmux_get_swio(unsigned int port,
const struct rza1_swio_pin *swio_pin;
unsigned int i;
for (i = 0; i < table->npins; ++i) {
swio_pin = &table->pins[i];
if (swio_pin->port == port && swio_pin->pin == pin &&
@@ -669,7 +668,7 @@ static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
* @mux_conf: pin multiplexing descriptor
*/
static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
struct rza1_mux_conf *mux_conf)
const struct rza1_mux_conf *mux_conf)
{
struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
unsigned int pin = mux_conf->pin;
@@ -1119,7 +1118,7 @@ static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
unsigned int group)
{
struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
struct rza1_mux_conf *mux_confs;
const struct rza1_mux_conf *mux_confs;
const struct function_desc *func;
struct group_desc *grp;
int i;
@@ -1132,7 +1131,7 @@ static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
if (!func)
return -EINVAL;
mux_confs = (struct rza1_mux_conf *)func->data;
mux_confs = (const struct rza1_mux_conf *)func->data;
for (i = 0; i < grp->grp.npins; ++i) {
int ret;
Loaded 100 of 116 files, more files were not shown because too many files have changed in this diff. Show more