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Merge 86b405ad8d ("Merge tag 'landlock-6.11-rc1-houdini-fix' of git://git.kernel.org/pub/scm/linux/kernel/git/mic/linux") into android-mainline

Browse Source 
Steps on the way to v6.11-rc1

Signed-off-by: Lee Jones <joneslee@google.com>
Change-Id: I3015e19e792a4a36488938fa90826f95e9ece5fb
This commit is contained in:
Lee Jones
2024-08-21 16:57:14 +01:00
parent 80654ca6dc 86b405ad8d
commit 9942878d42
42 changed files with 286 additions and 202 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
+2 -3
View File
@@ -120,9 +120,8 @@ patternProperties:
description:
Positive input can be connected to pins AIN1 to AIN16 by choosing the
appropriate value from 1 to 16. Negative input is connected to AINCOM.
items:
minimum: 1
maximum: 16
minimum: 1
maximum: 16
oneOf:
- required:
Documentation/devicetree/bindings/trivial-devices.yaml
+3 -1
View File
@@ -328,7 +328,9 @@ properties:
- renesas,hs3001
# Renesas ISL29501 time-of-flight sensor
- renesas,isl29501
# Rohm DH2228FV
# Rohm BH2228FV 8 channel DAC
- rohm,bh2228fv
# Rohm DH2228FV - This device does not exist, use rohm,bh2228fv instead.
- rohm,dh2228fv
# S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
- samsung,24ad0xd1
Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
+1
View File
@@ -21,6 +21,7 @@ properties:
- amlogic,t7-wdt
- items:
- enum:
- amlogic,a4-wdt
- amlogic,c3-wdt
- amlogic,s4-wdt
- const: amlogic,t7-wdt
arch/powerpc/sysdev/xive/native.c
+1 -3
View File
@@ -559,9 +559,7 @@ bool __init xive_native_init(void)
struct device_node *np;
struct resource r;
void __iomem *tima;
struct property *prop;
u8 max_prio = 7;
const __be32 *p;
u32 val, cpu;
s64 rc;
@@ -592,7 +590,7 @@ bool __init xive_native_init(void)
max_prio = val - 1;
/* Iterate the EQ sizes and pick one */
of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
of_property_for_each_u32(np, "ibm,xive-eq-sizes", val) {
xive_queue_shift = val;
if (val == PAGE_SHIFT)
break;
arch/powerpc/sysdev/xive/spapr.c
+1 -2
View File
@@ -814,7 +814,6 @@ bool __init xive_spapr_init(void)
struct device_node *np;
struct resource r;
void __iomem *tima;
struct property *prop;
u8 max_prio;
u32 val;
u32 len;
@@ -866,7 +865,7 @@ bool __init xive_spapr_init(void)
}
/* Iterate the EQ sizes and pick one */
of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
of_property_for_each_u32(np, "ibm,xive-eq-sizes", val) {
xive_queue_shift = val;
if (val == PAGE_SHIFT)
break;
drivers/base/regmap/regcache-maple.c
+2 -1
View File
@@ -110,7 +110,8 @@ static int regcache_maple_drop(struct regmap *map, unsigned int min,
struct maple_tree *mt = map->cache;
MA_STATE(mas, mt, min, max);
unsigned long *entry, *lower, *upper;
unsigned long lower_index, lower_last;
/* initialized to work around false-positive -Wuninitialized warning */
unsigned long lower_index = 0, lower_last = 0;
unsigned long upper_index, upper_last;
int ret = 0;
drivers/bus/ti-sysc.c
+1 -3
View File
@@ -2291,11 +2291,9 @@ static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
const char *name)
{
struct device_node *np = ddata->dev->of_node;
struct property *prop;
const __be32 *p;
u32 val;
of_property_for_each_u32(np, name, prop, p, val) {
of_property_for_each_u32(np, name, val) {
if (val >= SYSC_NR_IDLEMODES) {
dev_err(ddata->dev, "invalid idlemode: %i\n", val);
return -EINVAL;
drivers/clk/clk-conf.c
+1 -3
View File
@@ -81,13 +81,11 @@ err:
static int __set_clk_rates(struct device_node *node, bool clk_supplier)
{
struct of_phandle_args clkspec;
struct property *prop;
const __be32 *cur;
int rc, index = 0;
struct clk *clk;
u32 rate;
of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) {
of_property_for_each_u32(node, "assigned-clock-rates", rate) {
if (rate) {
rc = of_parse_phandle_with_args(node, "assigned-clocks",
"#clock-cells", index, &clkspec);
drivers/clk/clk-si5351.c
+26 -17
View File
@@ -1175,8 +1175,8 @@ static int si5351_dt_parse(struct i2c_client *client,
{
struct device_node *child, *np = client->dev.of_node;
struct si5351_platform_data *pdata;
struct property *prop;
const __be32 *p;
u32 array[4];
int sz, i;
int num = 0;
u32 val;
@@ -1191,20 +1191,24 @@ static int si5351_dt_parse(struct i2c_client *client,
* property silabs,pll-source : <num src>, [<..>]
* allow to selectively set pll source
*/
of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) {
sz = of_property_read_variable_u32_array(np, "silabs,pll-source", array, 2, 4);
sz = (sz == -EINVAL) ? 0 : sz; /* Missing property is OK */
if (sz < 0)
return dev_err_probe(&client->dev, sz, "invalid pll-source\n");
if (sz % 2)
return dev_err_probe(&client->dev, -EINVAL,
"missing pll-source for pll %d\n", array[sz - 1]);
for (i = 0; i < sz; i += 2) {
num = array[i];
val = array[i + 1];
if (num >= 2) {
dev_err(&client->dev,
"invalid pll %d on pll-source prop\n", num);
return -EINVAL;
}
p = of_prop_next_u32(prop, p, &val);
if (!p) {
dev_err(&client->dev,
"missing pll-source for pll %d\n", num);
return -EINVAL;
}
switch (val) {
case 0:
pdata->pll_src[num] = SI5351_PLL_SRC_XTAL;
@@ -1232,19 +1236,24 @@ static int si5351_dt_parse(struct i2c_client *client,
pdata->pll_reset[0] = true;
pdata->pll_reset[1] = true;
of_property_for_each_u32(np, "silabs,pll-reset-mode", prop, p, num) {
sz = of_property_read_variable_u32_array(np, "silabs,pll-reset-mode", array, 2, 4);
sz = (sz == -EINVAL) ? 0 : sz; /* Missing property is OK */
if (sz < 0)
return dev_err_probe(&client->dev, sz, "invalid pll-reset-mode\n");
if (sz % 2)
return dev_err_probe(&client->dev, -EINVAL,
"missing pll-reset-mode for pll %d\n", array[sz - 1]);
for (i = 0; i < sz; i += 2) {
num = array[i];
val = array[i + 1];
if (num >= 2) {
dev_err(&client->dev,
"invalid pll %d on pll-reset-mode prop\n", num);
return -EINVAL;
}
p = of_prop_next_u32(prop, p, &val);
if (!p) {
dev_err(&client->dev,
"missing pll-reset-mode for pll %d\n", num);
return -EINVAL;
}
switch (val) {
case 0:
drivers/clk/clk.c
+5 -7
View File
@@ -5429,9 +5429,8 @@ EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
const char *of_clk_get_parent_name(const struct device_node *np, int index)
{
struct of_phandle_args clkspec;
struct property *prop;
const char *clk_name;
const __be32 *vp;
bool found = false;
u32 pv;
int rc;
int count;
@@ -5448,15 +5447,16 @@ const char *of_clk_get_parent_name(const struct device_node *np, int index)
/* if there is an indices property, use it to transfer the index
* specified into an array offset for the clock-output-names property.
*/
of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
of_property_for_each_u32(clkspec.np, "clock-indices", pv) {
if (index == pv) {
index = count;
found = true;
break;
}
count++;
}
/* We went off the end of 'clock-indices' without finding it */
if (prop && !vp)
if (of_property_present(clkspec.np, "clock-indices") && !found)
return NULL;
if (of_property_read_string_index(clkspec.np, "clock-output-names",
@@ -5569,14 +5569,12 @@ static int parent_ready(struct device_node *np)
int of_clk_detect_critical(struct device_node *np, int index,
unsigned long *flags)
{
struct property *prop;
const __be32 *cur;
uint32_t idx;
if (!np || !flags)
return -EINVAL;
of_property_for_each_u32(np, "clock-critical", prop, cur, idx)
of_property_for_each_u32(np, "clock-critical", idx)
if (index == idx)
*flags |= CLK_IS_CRITICAL;
drivers/clk/davinci/da8xx-cfgchip.c
+2 -2
View File
@@ -508,7 +508,7 @@ da8xx_cfgchip_register_usb0_clk48(struct device *dev,
const char * const parent_names[] = { "usb_refclkin", "pll0_auxclk" };
struct clk *fck_clk;
struct da8xx_usb0_clk48 *usb0;
struct clk_init_data init;
struct clk_init_data init = {};
int ret;
fck_clk = devm_clk_get(dev, "fck");
@@ -583,7 +583,7 @@ da8xx_cfgchip_register_usb1_clk48(struct device *dev,
{
const char * const parent_names[] = { "usb0_clk48", "usb_refclkin" };
struct da8xx_usb1_clk48 *usb1;
struct clk_init_data init;
struct clk_init_data init = {};
int ret;
usb1 = devm_kzalloc(dev, sizeof(*usb1), GFP_KERNEL);
drivers/clk/qcom/common.c
+1 -3
View File
@@ -227,11 +227,9 @@ EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
{
struct device_node *np = dev->of_node;
struct property *prop;
const __be32 *p;
u32 i;
of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
of_property_for_each_u32(np, "protected-clocks", i) {
if (i >= cc->num_rclks)
continue;
drivers/clk/samsung/clk-exynos4.c
+7 -6
View File
@@ -1040,19 +1040,20 @@ static unsigned long __init exynos4_get_xom(void)
static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
{
struct samsung_fixed_rate_clock fclk;
struct clk *clk;
unsigned long finpll_f = 24000000;
unsigned long finpll_f;
unsigned int parent;
char *parent_name;
unsigned int xom = exynos4_get_xom();
parent_name = xom & 1 ? "xusbxti" : "xxti";
clk = clk_get(NULL, parent_name);
if (IS_ERR(clk)) {
parent = xom & 1 ? CLK_XUSBXTI : CLK_XXTI;
finpll_f = clk_hw_get_rate(ctx->clk_data.hws[parent]);
if (!finpll_f) {
pr_err("%s: failed to lookup parent clock %s, assuming "
"fin_pll clock frequency is 24MHz\n", __func__,
parent_name);
} else {
finpll_f = clk_get_rate(clk);
finpll_f = 24000000;
}
fclk.id = CLK_FIN_PLL;
drivers/clk/sophgo/clk-sg2042-pll.c
+1 -1
View File
@@ -387,7 +387,7 @@ static int sg2042_clk_pll_set_rate(struct clk_hw *hw,
struct sg2042_pll_clock *pll = to_sg2042_pll_clk(hw);
struct sg2042_pll_ctrl pctrl_table;
unsigned long flags;
u32 value;
u32 value = 0;
int ret;
spin_lock_irqsave(pll->lock, flags);
drivers/clk/sunxi/clk-simple-gates.c
+1 -3
View File
@@ -21,11 +21,9 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
{
struct clk_onecell_data *clk_data;
const char *clk_parent, *clk_name;
struct property *prop;
struct resource res;
void __iomem *clk_reg;
void __iomem *reg;
const __be32 *p;
int number, i = 0, j;
u8 clk_bit;
u32 index;
@@ -47,7 +45,7 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
if (!clk_data->clks)
goto err_free_data;
of_property_for_each_u32(node, "clock-indices", prop, p, index) {
of_property_for_each_u32(node, "clock-indices", index) {
of_property_read_string_index(node, "clock-output-names",
i, &clk_name);
drivers/clk/sunxi/clk-sun8i-bus-gates.c
+1 -3
View File
@@ -24,11 +24,9 @@ static void __init sun8i_h3_bus_gates_init(struct device_node *node)
const char *parents[PARENT_MAX];
struct clk_onecell_data *clk_data;
const char *clk_name;
struct property *prop;
struct resource res;
void __iomem *clk_reg;
void __iomem *reg;
const __be32 *p;
int number, i;
u8 clk_bit;
int index;
@@ -58,7 +56,7 @@ static void __init sun8i_h3_bus_gates_init(struct device_node *node)
goto err_free_data;
i = 0;
of_property_for_each_u32(node, "clock-indices", prop, p, index) {
of_property_for_each_u32(node, "clock-indices", index) {
of_property_read_string_index(node, "clock-output-names",
i, &clk_name);
drivers/clk/thead/Kconfig
+1
View File
@@ -3,6 +3,7 @@
config CLK_THEAD_TH1520_AP
bool "T-HEAD TH1520 AP clock support"
depends on ARCH_THEAD || COMPILE_TEST
depends on 64BIT
default ARCH_THEAD
select REGMAP_MMIO
help
drivers/clocksource/samsung_pwm_timer.c
+1 -3
View File
@@ -418,8 +418,6 @@ void __init samsung_pwm_clocksource_init(void __iomem *base,
static int __init samsung_pwm_alloc(struct device_node *np,
const struct samsung_pwm_variant *variant)
{
struct property *prop;
const __be32 *cur;
u32 val;
int i, ret;
@@ -427,7 +425,7 @@ static int __init samsung_pwm_alloc(struct device_node *np,
for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
pwm.irq[i] = irq_of_parse_and_map(np, i);
of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
of_property_for_each_u32(np, "samsung,pwm-outputs", val) {
if (val >= SAMSUNG_PWM_NUM) {
pr_warn("%s: invalid channel index in samsung,pwm-outputs property\n", __func__);
continue;
drivers/gpio/gpio-brcmstb.c
+1 -4
View File
@@ -591,8 +591,6 @@ static int brcmstb_gpio_probe(struct platform_device *pdev)
void __iomem *reg_base;
struct brcmstb_gpio_priv *priv;
struct resource *res;
struct property *prop;
const __be32 *p;
u32 bank_width;
int num_banks = 0;
int num_gpios = 0;
@@ -636,8 +634,7 @@ static int brcmstb_gpio_probe(struct platform_device *pdev)
flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
#endif
of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
bank_width) {
of_property_for_each_u32(np, "brcm,gpio-bank-widths", bank_width) {
struct brcmstb_gpio_bank *bank;
struct gpio_chip *gc;
drivers/gpio/gpio-virtuser.c
+1 -1
View File
@@ -805,7 +805,7 @@ static int gpio_virtuser_dbgfs_init_line_attrs(struct device *dev,
return -ENOMEM;
data->ad.desc = desc;
sprintf(data->consumer, id);
strscpy(data->consumer, id);
atomic_set(&data->irq, 0);
atomic_set(&data->irq_count, 0);
drivers/iio/adc/ti_am335x_adc.c
+1 -3
View File
@@ -564,13 +564,11 @@ static int tiadc_parse_dt(struct platform_device *pdev,
struct tiadc_device *adc_dev)
{
struct device_node *node = pdev->dev.of_node;
struct property *prop;
const __be32 *cur;
int channels = 0;
u32 val;
int i;
of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
of_property_for_each_u32(node, "ti,adc-channels", val) {
adc_dev->channel_line[channels] = val;
/* Set Default values for optional DT parameters */
drivers/iommu/amd/io_pgtable.c
+3 -3
View File
@@ -588,9 +588,9 @@ static struct io_pgtable *v1_alloc_pgtable(struct io_pgtable_cfg *cfg, void *coo
{
struct amd_io_pgtable *pgtable = io_pgtable_cfg_to_data(cfg);
cfg->pgsize_bitmap = AMD_IOMMU_PGSIZES,
cfg->ias = IOMMU_IN_ADDR_BIT_SIZE,
cfg->oas = IOMMU_OUT_ADDR_BIT_SIZE,
cfg->pgsize_bitmap = AMD_IOMMU_PGSIZES;
cfg->ias = IOMMU_IN_ADDR_BIT_SIZE;
cfg->oas = IOMMU_OUT_ADDR_BIT_SIZE;
cfg->tlb = &v1_flush_ops;
pgtable->iop.ops.map_pages = iommu_v1_map_pages;
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
+1 -1
View File
@@ -277,7 +277,7 @@ static int nvidia_smmu_init_context(struct arm_smmu_domain *smmu_domain,
*/
if (of_device_is_compatible(np, "nvidia,tegra234-smmu") ||
of_device_is_compatible(np, "nvidia,tegra194-smmu")) {
smmu->pgsize_bitmap = PAGE_SIZE;
smmu->pgsize_bitmap &= GENMASK(PAGE_SHIFT, 0);
pgtbl_cfg->pgsize_bitmap = smmu->pgsize_bitmap;
}
drivers/iommu/sprd-iommu.c
+1 -1
View File
@@ -232,8 +232,8 @@ static void sprd_iommu_cleanup(struct sprd_iommu_domain *dom)
pgt_size = sprd_iommu_pgt_size(&dom->domain);
dma_free_coherent(dom->sdev->dev, pgt_size, dom->pgt_va, dom->pgt_pa);
dom->sdev = NULL;
sprd_iommu_hw_en(dom->sdev, false);
dom->sdev = NULL;
}
static void sprd_iommu_domain_free(struct iommu_domain *domain)
drivers/irqchip/irq-atmel-aic-common.c
+1 -3
View File
@@ -111,8 +111,6 @@ static void __init aic_common_ext_irq_of_init(struct irq_domain *domain)
struct device_node *node = irq_domain_get_of_node(domain);
struct irq_chip_generic *gc;
struct aic_chip_data *aic;
struct property *prop;
const __be32 *p;
u32 hwirq;
gc = irq_get_domain_generic_chip(domain, 0);
@@ -120,7 +118,7 @@ static void __init aic_common_ext_irq_of_init(struct irq_domain *domain)
aic = gc->private;
aic->ext_irqs |= 1;
of_property_for_each_u32(node, "atmel,external-irqs", prop, p, hwirq) {
of_property_for_each_u32(node, "atmel,external-irqs", hwirq) {
gc = irq_get_domain_generic_chip(domain, hwirq);
if (!gc) {
pr_warn("AIC: external irq %d >= %d skip it\n",
drivers/irqchip/irq-pic32-evic.c
+1 -3
View File
@@ -190,13 +190,11 @@ static void __init pic32_ext_irq_of_init(struct irq_domain *domain)
{
struct device_node *node = irq_domain_get_of_node(domain);
struct evic_chip_data *priv = domain->host_data;
struct property *prop;
const __le32 *p;
u32 hwirq;
int i = 0;
const char *pname = "microchip,external-irqs";
of_property_for_each_u32(node, pname, prop, p, hwirq) {
of_property_for_each_u32(node, pname, hwirq) {
if (i >= ARRAY_SIZE(priv->ext_irqs)) {
pr_warn("More than %d external irq, skip rest\n",
ARRAY_SIZE(priv->ext_irqs));
drivers/mfd/ti_am335x_tscadc.c
+1 -3
View File
@@ -119,8 +119,6 @@ static int ti_tscadc_probe(struct platform_device *pdev)
struct clk *clk;
struct device_node *node;
struct mfd_cell *cell;
struct property *prop;
const __be32 *cur;
bool use_tsc = false, use_mag = false;
u32 val;
int err;
@@ -167,7 +165,7 @@ static int ti_tscadc_probe(struct platform_device *pdev)
}
node = of_get_child_by_name(pdev->dev.of_node, "adc");
of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
of_property_for_each_u32(node, "ti,adc-channels", val) {
adc_channels++;
if (val > 7) {
dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
drivers/pinctrl/nxp/pinctrl-s32cc.c
+1 -3
View File
@@ -730,9 +730,7 @@ static int s32_pinctrl_parse_groups(struct device_node *np,
struct s32_pin_group *grp,
struct s32_pinctrl_soc_info *info)
{
const __be32 *p;
struct device *dev;
struct property *prop;
unsigned int *pins, *sss;
int i, npins;
u32 pinmux;
@@ -763,7 +761,7 @@ static int s32_pinctrl_parse_groups(struct device_node *np,
return -ENOMEM;
i = 0;
of_property_for_each_u32(np, "pinmux", prop, p, pinmux) {
of_property_for_each_u32(np, "pinmux", pinmux) {
pins[i] = get_pin_no(pinmux);
sss[i] = get_pin_func(pinmux);
drivers/pinctrl/pinctrl-k210.c
+1 -3
View File
@@ -763,8 +763,6 @@ static int k210_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
unsigned int *reserved_maps,
unsigned int *num_maps)
{
struct property *prop;
const __be32 *p;
int ret, pinmux_groups;
u32 pinmux_group;
unsigned long *configs = NULL;
@@ -797,7 +795,7 @@ static int k210_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
if (ret < 0)
goto exit;
of_property_for_each_u32(np, "pinmux", prop, p, pinmux_group) {
of_property_for_each_u32(np, "pinmux", pinmux_group) {
const char *group_name, *func_name;
u32 pin = FIELD_GET(K210_PG_PIN, pinmux_group);
u32 func = FIELD_GET(K210_PG_FUNC, pinmux_group);
drivers/pwm/pwm-samsung.c
+1 -3
View File
@@ -510,8 +510,6 @@ static int pwm_samsung_parse_dt(struct pwm_chip *chip)
struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
struct device_node *np = pwmchip_parent(chip)->of_node;
const struct of_device_id *match;
struct property *prop;
const __be32 *cur;
u32 val;
match = of_match_node(samsung_pwm_matches, np);
@@ -520,7 +518,7 @@ static int pwm_samsung_parse_dt(struct pwm_chip *chip)
memcpy(&our_chip->variant, match->data, sizeof(our_chip->variant));
of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
of_property_for_each_u32(np, "samsung,pwm-outputs", val) {
if (val >= SAMSUNG_PWM_NUM) {
dev_err(pwmchip_parent(chip),
"%s: invalid channel index in samsung,pwm-outputs property\n",
drivers/regulator/Kconfig
+2 -2
View File
@@ -1661,10 +1661,10 @@ config REGULATOR_UNIPHIER
config REGULATOR_RZG2L_VBCTRL
tristate "Renesas RZ/G2L USB VBUS regulator driver"
depends on ARCH_RZG2L || COMPILE_TEST
depends on RESET_RZG2L_USBPHY_CTRL || COMPILE_TEST
depends on OF
select REGMAP_MMIO
default ARCH_RZG2L
default RESET_RZG2L_USBPHY_CTRL
help
Support for VBUS regulators implemented on Renesas RZ/G2L SoCs.
drivers/spi/spi-microchip-core.c
+110 -80
View File
@@ -75,6 +75,7 @@
#define REG_CONTROL (0x00)
#define REG_FRAME_SIZE (0x04)
#define FRAME_SIZE_MASK GENMASK(5, 0)
#define REG_STATUS (0x08)
#define REG_INT_CLEAR (0x0c)
#define REG_RX_DATA (0x10)
@@ -89,6 +90,9 @@
#define REG_RIS (0x24)
#define REG_CONTROL2 (0x28)
#define REG_COMMAND (0x2c)
#define COMMAND_CLRFRAMECNT BIT(4)
#define COMMAND_TXFIFORST BIT(3)
#define COMMAND_RXFIFORST BIT(2)
#define REG_PKTSIZE (0x30)
#define REG_CMD_SIZE (0x34)
#define REG_HWSTATUS (0x38)
@@ -103,10 +107,11 @@ struct mchp_corespi {
u8 *rx_buf;
u32 clk_gen; /* divider for spi output clock generated by the controller */
u32 clk_mode;
u32 pending_slave_select;
int irq;
int tx_len;
int rx_len;
int pending;
int n_bytes;
};
static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg)
@@ -130,113 +135,126 @@ static inline void mchp_corespi_disable(struct mchp_corespi *spi)
static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi)
{
u8 data;
int fifo_max, i = 0;
while (spi->rx_len >= spi->n_bytes && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)) {
u32 data = mchp_corespi_read(spi, REG_RX_DATA);
fifo_max = min(spi->rx_len, FIFO_DEPTH);
spi->rx_len -= spi->n_bytes;
while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)) {
data = mchp_corespi_read(spi, REG_RX_DATA);
if (!spi->rx_buf)
continue;
if (spi->rx_buf)
*spi->rx_buf++ = data;
i++;
if (spi->n_bytes == 4)
*((u32 *)spi->rx_buf) = data;
else if (spi->n_bytes == 2)
*((u16 *)spi->rx_buf) = data;
else
*spi->rx_buf = data;
spi->rx_buf += spi->n_bytes;
}
spi->rx_len -= i;
spi->pending -= i;
}
static void mchp_corespi_enable_ints(struct mchp_corespi *spi)
{
u32 control, mask = INT_ENABLE_MASK;
u32 control = mchp_corespi_read(spi, REG_CONTROL);
mchp_corespi_disable(spi);
control = mchp_corespi_read(spi, REG_CONTROL);
control |= mask;
mchp_corespi_write(spi, REG_CONTROL, control);
control |= CONTROL_ENABLE;
control |= INT_ENABLE_MASK;
mchp_corespi_write(spi, REG_CONTROL, control);
}
static void mchp_corespi_disable_ints(struct mchp_corespi *spi)
{
u32 control, mask = INT_ENABLE_MASK;
u32 control = mchp_corespi_read(spi, REG_CONTROL);
mchp_corespi_disable(spi);
control = mchp_corespi_read(spi, REG_CONTROL);
control &= ~mask;
mchp_corespi_write(spi, REG_CONTROL, control);
control |= CONTROL_ENABLE;
control &= ~INT_ENABLE_MASK;
mchp_corespi_write(spi, REG_CONTROL, control);
}
static inline void mchp_corespi_set_xfer_size(struct mchp_corespi *spi, int len)
{
u32 control;
u16 lenpart;
u32 lenpart;
u32 frames = mchp_corespi_read(spi, REG_FRAMESUP);
/*
* Disable the SPI controller. Writes to transfer length have
* no effect when the controller is enabled.
* Writing to FRAMECNT in REG_CONTROL will reset the frame count, taking
* a shortcut requires an explicit clear.
*/
mchp_corespi_disable(spi);
if (frames == len) {
mchp_corespi_write(spi, REG_COMMAND, COMMAND_CLRFRAMECNT);
return;
}
/*
* The lower 16 bits of the frame count are stored in the control reg
* for legacy reasons, but the upper 16 written to a different register:
* FRAMESUP. While both the upper and lower bits can be *READ* from the
* FRAMESUP register, writing to the lower 16 bits is a NOP
* FRAMESUP register, writing to the lower 16 bits is (supposedly) a NOP.
*
* The driver used to disable the controller while modifying the frame
* count, and mask off the lower 16 bits of len while writing to
* FRAMES_UP. When the driver was changed to disable the controller as
* infrequently as possible, it was discovered that the logic of
* lenpart = len & 0xffff_0000
* write(REG_FRAMESUP, lenpart)
* would actually write zeros into the lower 16 bits on an mpfs250t-es,
* despite documentation stating these bits were read-only.
* Writing len unmasked into FRAMES_UP ensures those bits aren't zeroed
* on an mpfs250t-es and will be a NOP for the lower 16 bits on hardware
* that matches the documentation.
*/
lenpart = len & 0xffff;
control = mchp_corespi_read(spi, REG_CONTROL);
control &= ~CONTROL_FRAMECNT_MASK;
control |= lenpart << CONTROL_FRAMECNT_SHIFT;
mchp_corespi_write(spi, REG_CONTROL, control);
lenpart = len & 0xffff0000;
mchp_corespi_write(spi, REG_FRAMESUP, lenpart);
control |= CONTROL_ENABLE;
mchp_corespi_write(spi, REG_CONTROL, control);
mchp_corespi_write(spi, REG_FRAMESUP, len);
}
static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi)
{
u8 byte;
int fifo_max, i = 0;
fifo_max = min(spi->tx_len, FIFO_DEPTH);
fifo_max = DIV_ROUND_UP(min(spi->tx_len, FIFO_DEPTH), spi->n_bytes);
mchp_corespi_set_xfer_size(spi, fifo_max);
while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) {
byte = spi->tx_buf ? *spi->tx_buf++ : 0xaa;
mchp_corespi_write(spi, REG_TX_DATA, byte);
u32 word;
if (spi->n_bytes == 4)
word = spi->tx_buf ? *((u32 *)spi->tx_buf) : 0xaa;
else if (spi->n_bytes == 2)
word = spi->tx_buf ? *((u16 *)spi->tx_buf) : 0xaa;
else
word = spi->tx_buf ? *spi->tx_buf : 0xaa;
mchp_corespi_write(spi, REG_TX_DATA, word);
if (spi->tx_buf)
spi->tx_buf += spi->n_bytes;
i++;
}
spi->tx_len -= i;
spi->pending += i;
spi->tx_len -= i * spi->n_bytes;
}
static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, int bt)
{
u32 frame_size = mchp_corespi_read(spi, REG_FRAME_SIZE);
u32 control;
if ((frame_size & FRAME_SIZE_MASK) == bt)
return;
/*
* Disable the SPI controller. Writes to the frame size have
* no effect when the controller is enabled.
*/
mchp_corespi_disable(spi);
control = mchp_corespi_read(spi, REG_CONTROL);
control &= ~CONTROL_ENABLE;
mchp_corespi_write(spi, REG_CONTROL, control);
mchp_corespi_write(spi, REG_FRAME_SIZE, bt);
control = mchp_corespi_read(spi, REG_CONTROL);
control |= CONTROL_ENABLE;
mchp_corespi_write(spi, REG_CONTROL, control);
}
@@ -249,8 +267,18 @@ static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
reg &= ~BIT(spi_get_chipselect(spi, 0));
reg |= !disable << spi_get_chipselect(spi, 0);
corespi->pending_slave_select = reg;
mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
/*
* Only deassert chip select immediately. Writing to some registers
* requires the controller to be disabled, which results in the
* output pins being tristated and can cause the SCLK and MOSI lines
* to transition. Therefore asserting the chip select is deferred
* until just before writing to the TX FIFO, to ensure the device
* doesn't see any spurious clock transitions whilst CS is enabled.
*/
if (((spi->mode & SPI_CS_HIGH) == 0) == disable)
mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
}
static int mchp_corespi_setup(struct spi_device *spi)
@@ -269,6 +297,7 @@ static int mchp_corespi_setup(struct spi_device *spi)
if (spi->mode & SPI_CS_HIGH) {
reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
reg |= BIT(spi_get_chipselect(spi, 0));
corespi->pending_slave_select = reg;
mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
}
return 0;
@@ -279,17 +308,13 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *
unsigned long clk_hz;
u32 control = mchp_corespi_read(spi, REG_CONTROL);
control |= CONTROL_MASTER;
control &= ~CONTROL_ENABLE;
mchp_corespi_write(spi, REG_CONTROL, control);
control |= CONTROL_MASTER;
control &= ~CONTROL_MODE_MASK;
control |= MOTOROLA_MODE;
mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
/* max. possible spi clock rate is the apb clock rate */
clk_hz = clk_get_rate(spi->clk);
host->max_speed_hz = clk_hz;
/*
* The controller must be configured so that it doesn't remove Chip
* Select until the entire message has been transferred, even if at
@@ -298,11 +323,16 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *
* BIGFIFO mode is also enabled, which sets the fifo depth to 32 frames
* for the 8 bit transfers that this driver uses.
*/
control = mchp_corespi_read(spi, REG_CONTROL);
control |= CONTROL_SPS | CONTROL_BIGFIFO;
mchp_corespi_write(spi, REG_CONTROL, control);
mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
/* max. possible spi clock rate is the apb clock rate */
clk_hz = clk_get_rate(spi->clk);
host->max_speed_hz = clk_hz;
mchp_corespi_enable_ints(spi);
/*
@@ -310,7 +340,8 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *
* select is relinquished to the hardware. SSELOUT is enabled too so we
* can deal with active high targets.
*/
mchp_corespi_write(spi, REG_SLAVE_SELECT, SSELOUT | SSEL_DIRECT);
spi->pending_slave_select = SSELOUT | SSEL_DIRECT;
mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);
control = mchp_corespi_read(spi, REG_CONTROL);
@@ -324,8 +355,6 @@ static inline void mchp_corespi_set_clk_gen(struct mchp_corespi *spi)
{
u32 control;
mchp_corespi_disable(spi);
control = mchp_corespi_read(spi, REG_CONTROL);
if (spi->clk_mode)
control |= CONTROL_CLKMODE;
@@ -334,12 +363,12 @@ static inline void mchp_corespi_set_clk_gen(struct mchp_corespi *spi)
mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen);
mchp_corespi_write(spi, REG_CONTROL, control);
mchp_corespi_write(spi, REG_CONTROL, control | CONTROL_ENABLE);
}
static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int mode)
{
u32 control, mode_val;
u32 mode_val;
u32 control = mchp_corespi_read(spi, REG_CONTROL);
switch (mode & SPI_MODE_X_MASK) {
case SPI_MODE_0:
@@ -357,12 +386,13 @@ static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int
}
/*
* Disable the SPI controller. Writes to the frame size have
* Disable the SPI controller. Writes to the frame protocol have
* no effect when the controller is enabled.
*/
mchp_corespi_disable(spi);
control = mchp_corespi_read(spi, REG_CONTROL);
control &= ~CONTROL_ENABLE;
mchp_corespi_write(spi, REG_CONTROL, control);
control &= ~(SPI_MODE_X_MASK << MODE_X_MASK_SHIFT);
control |= mode_val;
@@ -383,21 +413,18 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)
if (intfield == 0)
return IRQ_NONE;
if (intfield & INT_TXDONE) {
if (intfield & INT_TXDONE)
mchp_corespi_write(spi, REG_INT_CLEAR, INT_TXDONE);
if (intfield & INT_RXRDY) {
mchp_corespi_write(spi, REG_INT_CLEAR, INT_RXRDY);
if (spi->rx_len)
mchp_corespi_read_fifo(spi);
if (spi->tx_len)
mchp_corespi_write_fifo(spi);
if (!spi->rx_len)
finalise = true;
}
if (intfield & INT_RXRDY)
mchp_corespi_write(spi, REG_INT_CLEAR, INT_RXRDY);
if (!spi->rx_len && !spi->tx_len)
finalise = true;
if (intfield & INT_RX_CHANNEL_OVERFLOW) {
mchp_corespi_write(spi, REG_INT_CLEAR, INT_RX_CHANNEL_OVERFLOW);
@@ -477,13 +504,17 @@ static int mchp_corespi_transfer_one(struct spi_controller *host,
spi->rx_buf = xfer->rx_buf;
spi->tx_len = xfer->len;
spi->rx_len = xfer->len;
spi->pending = 0;
spi->n_bytes = roundup_pow_of_two(DIV_ROUND_UP(xfer->bits_per_word, BITS_PER_BYTE));
mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH)
? FIFO_DEPTH : spi->tx_len);
mchp_corespi_set_framesize(spi, xfer->bits_per_word);
if (spi->tx_len)
mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST);
mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);
while (spi->tx_len)
mchp_corespi_write_fifo(spi);
return 1;
}
@@ -493,7 +524,6 @@ static int mchp_corespi_prepare_message(struct spi_controller *host,
struct spi_device *spi_dev = msg->spi;
struct mchp_corespi *spi = spi_controller_get_devdata(host);
mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
mchp_corespi_set_mode(spi, spi_dev->mode);
return 0;
@@ -521,7 +551,7 @@ static int mchp_corespi_probe(struct platform_device *pdev)
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
host->use_gpio_descriptors = true;
host->setup = mchp_corespi_setup;
host->bits_per_word_mask = SPI_BPW_MASK(8);
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
host->transfer_one = mchp_corespi_transfer_one;
host->prepare_message = mchp_corespi_prepare_message;
host->set_cs = mchp_corespi_set_cs;
drivers/spi/spidev.c
+1
View File
@@ -734,6 +734,7 @@ static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "lwn,bk4", .data = &spidev_of_check },
{ .compatible = "menlo,m53cpld", .data = &spidev_of_check },
{ .compatible = "micron,spi-authenta", .data = &spidev_of_check },
{ .compatible = "rohm,bh2228fv", .data = &spidev_of_check },
{ .compatible = "rohm,dh2228fv", .data = &spidev_of_check },
{ .compatible = "semtech,sx1301", .data = &spidev_of_check },
{ .compatible = "silabs,em3581", .data = &spidev_of_check },
drivers/tty/sysrq.c
+1 -3
View File
@@ -774,8 +774,6 @@ static void sysrq_of_get_keyreset_config(void)
{
u32 key;
struct device_node *np;
struct property *prop;
const __be32 *p;
np = of_find_node_by_path("/chosen/linux,sysrq-reset-seq");
if (!np) {
@@ -786,7 +784,7 @@ static void sysrq_of_get_keyreset_config(void)
/* Reset in case a __weak definition was present */
sysrq_reset_seq_len = 0;
of_property_for_each_u32(np, "keyset", prop, p, key) {
of_property_for_each_u32(np, "keyset", key) {
if (key == KEY_RESERVED || key > KEY_MAX ||
sysrq_reset_seq_len == SYSRQ_KEY_RESET_MAX)
break;
drivers/usb/misc/usb251xb.c
+1 -3
View File
@@ -382,11 +382,9 @@ static void usb251xb_get_ports_field(struct usb251xb *hub,
bool ds_only, u8 *fld)
{
struct device *dev = hub->dev;
struct property *prop;
const __be32 *p;
u32 port;
of_property_for_each_u32(dev->of_node, prop_name, prop, p, port) {
of_property_for_each_u32(dev->of_node, prop_name, port) {
if ((port >= ds_only ? 1 : 0) && (port <= port_cnt))
*fld |= BIT(port);
else
include/linux/firewire.h
+2 -3
View File
@@ -462,9 +462,8 @@ struct fw_iso_packet {
/* rx: Sync bit, wait for matching sy */
u32 tag:2; /* tx: Tag in packet header */
u32 sy:4; /* tx: Sy in packet header */
u32 header_length:8; /* Length of immediate header */
/* tx: Top of 1394 isoch. data_block */
u32 header[] __counted_by(header_length);
u32 header_length:8; /* Size of immediate header */
u32 header[]; /* tx: Top of 1394 isoch. data_block */
};
#define FW_ISO_CONTEXT_TRANSMIT 0
include/linux/of.h
+7 -8
View File
@@ -430,11 +430,9 @@ extern int of_detach_node(struct device_node *);
#define of_match_ptr(_ptr) (_ptr)
/*
* struct property *prop;
* const __be32 *p;
* u32 u;
*
* of_property_for_each_u32(np, "propname", prop, p, u)
* of_property_for_each_u32(np, "propname", u)
* printk("U32 value: %x\n", u);
*/
const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
@@ -1431,11 +1429,12 @@ static inline int of_property_read_s32(const struct device_node *np,
err == 0; \
err = of_phandle_iterator_next(it))
#define of_property_for_each_u32(np, propname, prop, p, u) \
for (prop = of_find_property(np, propname, NULL), \
p = of_prop_next_u32(prop, NULL, &u); \
p; \
p = of_prop_next_u32(prop, p, &u))
#define of_property_for_each_u32(np, propname, u) \
for (struct {struct property *prop; const __be32 *item; } _it = \
{of_find_property(np, propname, NULL), \
of_prop_next_u32(_it.prop, NULL, &u)}; \
_it.item; \
_it.item = of_prop_next_u32(_it.prop, _it.item, &u))
#define of_property_for_each_string(np, propname, prop, s) \
for (prop = of_find_property(np, propname, NULL), \
security/landlock/cred.c
+9 -2
View File
@@ -14,8 +14,8 @@
#include "ruleset.h"
#include "setup.h"
static int hook_cred_prepare(struct cred *const new,
const struct cred *const old, const gfp_t gfp)
static void hook_cred_transfer(struct cred *const new,
const struct cred *const old)
{
struct landlock_ruleset *const old_dom = landlock_cred(old)->domain;
@@ -23,6 +23,12 @@ static int hook_cred_prepare(struct cred *const new,
landlock_get_ruleset(old_dom);
landlock_cred(new)->domain = old_dom;
}
}
static int hook_cred_prepare(struct cred *const new,
const struct cred *const old, const gfp_t gfp)
{
hook_cred_transfer(new, old);
return 0;
}
@@ -36,6 +42,7 @@ static void hook_cred_free(struct cred *const cred)
static struct security_hook_list landlock_hooks[] __ro_after_init = {
LSM_HOOK_INIT(cred_prepare, hook_cred_prepare),
LSM_HOOK_INIT(cred_transfer, hook_cred_transfer),
LSM_HOOK_INIT(cred_free, hook_cred_free),
};
sound/firewire/amdtp-stream.c
+1 -2
View File
@@ -1180,8 +1180,7 @@ static void process_rx_packets(struct fw_iso_context *context, u32 tstamp, size_
(void)fw_card_read_cycle_time(fw_parent_device(s->unit)->card, &curr_cycle_time);
for (i = 0; i < packets; ++i) {
DEFINE_FLEX(struct fw_iso_packet, template, header,
header_length, CIP_HEADER_QUADLETS);
DEFINE_RAW_FLEX(struct fw_iso_packet, template, header, CIP_HEADER_QUADLETS);
bool sched_irq = false;
build_it_pkt_header(s, desc->cycle, template, pkt_header_length,
sound/soc/codecs/arizona.c
+5 -7
View File
@@ -2786,15 +2786,13 @@ int arizona_of_get_audio_pdata(struct arizona *arizona)
{
struct arizona_pdata *pdata = &arizona->pdata;
struct device_node *np = arizona->dev->of_node;
struct property *prop;
const __be32 *cur;
u32 val;
u32 pdm_val[ARIZONA_MAX_PDM_SPK];
int ret;
int count = 0;
count = 0;
of_property_for_each_u32(np, "wlf,inmode", prop, cur, val) {
of_property_for_each_u32(np, "wlf,inmode", val) {
if (count == ARRAY_SIZE(pdata->inmode))
break;
@@ -2803,7 +2801,7 @@ int arizona_of_get_audio_pdata(struct arizona *arizona)
}
count = 0;
of_property_for_each_u32(np, "wlf,dmic-ref", prop, cur, val) {
of_property_for_each_u32(np, "wlf,dmic-ref", val) {
if (count == ARRAY_SIZE(pdata->dmic_ref))
break;
@@ -2812,7 +2810,7 @@ int arizona_of_get_audio_pdata(struct arizona *arizona)
}
count = 0;
of_property_for_each_u32(np, "wlf,out-mono", prop, cur, val) {
of_property_for_each_u32(np, "wlf,out-mono", val) {
if (count == ARRAY_SIZE(pdata->out_mono))
break;
@@ -2821,7 +2819,7 @@ int arizona_of_get_audio_pdata(struct arizona *arizona)
}
count = 0;
of_property_for_each_u32(np, "wlf,max-channels-clocked", prop, cur, val) {
of_property_for_each_u32(np, "wlf,max-channels-clocked", val) {
if (count == ARRAY_SIZE(pdata->max_channels_clocked))
break;
@@ -2830,7 +2828,7 @@ int arizona_of_get_audio_pdata(struct arizona *arizona)
}
count = 0;
of_property_for_each_u32(np, "wlf,out-volume-limit", prop, cur, val) {
of_property_for_each_u32(np, "wlf,out-volume-limit", val) {
if (count == ARRAY_SIZE(pdata->out_vol_limit))
break;
tools/testing/selftests/landlock/base_test.c
+74
View File
@@ -9,6 +9,7 @@
#define _GNU_SOURCE
#include <errno.h>
#include <fcntl.h>
#include <linux/keyctl.h>
#include <linux/landlock.h>
#include <string.h>
#include <sys/prctl.h>
@@ -326,4 +327,77 @@ TEST(ruleset_fd_transfer)
ASSERT_EQ(EXIT_SUCCESS, WEXITSTATUS(status));
}
TEST(cred_transfer)
{
struct landlock_ruleset_attr ruleset_attr = {
.handled_access_fs = LANDLOCK_ACCESS_FS_READ_DIR,
};
int ruleset_fd, dir_fd;
pid_t child;
int status;
drop_caps(_metadata);
dir_fd = open("/", O_RDONLY | O_DIRECTORY | O_CLOEXEC);
EXPECT_LE(0, dir_fd);
EXPECT_EQ(0, close(dir_fd));
/* Denies opening directories. */
ruleset_fd =
landlock_create_ruleset(&ruleset_attr, sizeof(ruleset_attr), 0);
ASSERT_LE(0, ruleset_fd);
EXPECT_EQ(0, prctl(PR_SET_NO_NEW_PRIVS, 1, 0, 0, 0));
ASSERT_EQ(0, landlock_restrict_self(ruleset_fd, 0));
EXPECT_EQ(0, close(ruleset_fd));
/* Checks ruleset enforcement. */
EXPECT_EQ(-1, open("/", O_RDONLY | O_DIRECTORY | O_CLOEXEC));
EXPECT_EQ(EACCES, errno);
/* Needed for KEYCTL_SESSION_TO_PARENT permission checks */
EXPECT_NE(-1, syscall(__NR_keyctl, KEYCTL_JOIN_SESSION_KEYRING, NULL, 0,
0, 0))
{
TH_LOG("Failed to join session keyring: %s", strerror(errno));
}
child = fork();
ASSERT_LE(0, child);
if (child == 0) {
/* Checks ruleset enforcement. */
EXPECT_EQ(-1, open("/", O_RDONLY | O_DIRECTORY | O_CLOEXEC));
EXPECT_EQ(EACCES, errno);
/*
* KEYCTL_SESSION_TO_PARENT is a no-op unless we have a
* different session keyring in the child, so make that happen.
*/
EXPECT_NE(-1, syscall(__NR_keyctl, KEYCTL_JOIN_SESSION_KEYRING,
NULL, 0, 0, 0));
/*
* KEYCTL_SESSION_TO_PARENT installs credentials on the parent
* that never go through the cred_prepare hook, this path uses
* cred_transfer instead.
*/
EXPECT_EQ(0, syscall(__NR_keyctl, KEYCTL_SESSION_TO_PARENT, 0,
0, 0, 0));
/* Re-checks ruleset enforcement. */
EXPECT_EQ(-1, open("/", O_RDONLY | O_DIRECTORY | O_CLOEXEC));
EXPECT_EQ(EACCES, errno);
_exit(_metadata->exit_code);
return;
}
EXPECT_EQ(child, waitpid(child, &status, 0));
EXPECT_EQ(1, WIFEXITED(status));
EXPECT_EQ(EXIT_SUCCESS, WEXITSTATUS(status));
/* Re-checks ruleset enforcement. */
EXPECT_EQ(-1, open("/", O_RDONLY | O_DIRECTORY | O_CLOEXEC));
EXPECT_EQ(EACCES, errno);
}
TEST_HARNESS_MAIN
tools/testing/selftests/landlock/config
+1
View File
@@ -2,6 +2,7 @@ CONFIG_CGROUPS=y
CONFIG_CGROUP_SCHED=y
CONFIG_INET=y
CONFIG_IPV6=y
CONFIG_KEYS=y
CONFIG_NET=y
CONFIG_NET_NS=y
CONFIG_OVERLAY_FS=y