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net: phy: marvell10g: indicate 88X33x0 only port control registers

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Rename port control registers to indicate that they are valid only for
88X33x0, not for 88E21x0.

Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Marek Behún
2021-04-07 22:22:42 +02:00
committed by David S. Miller
parent 0d3755428d
commit 9893f31690
1 changed files with 7 additions and 7 deletions
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drivers/net/phy/marvell10g.c
+7 -7
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@@ -78,10 +78,10 @@ enum {
/* Vendor2 MMD registers */
MV_V2_PORT_CTRL = 0xf001,
MV_V2_PORT_CTRL_SWRST = BIT(15),
MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
/* Temperature control/read registers (88X3310 only) */
MV_V2_TEMP_CTRL = 0xf08a,
MV_V2_TEMP_CTRL_MASK = 0xc000,
@@ -268,7 +268,7 @@ static int mv3310_power_up(struct phy_device *phydev)
return ret;
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
MV_V2_PORT_CTRL_SWRST);
MV_V2_33X0_PORT_CTRL_SWRST);
}
static int mv3310_reset(struct phy_device *phydev, u32 unit)
@@ -479,8 +479,8 @@ static int mv3310_config_init(struct phy_device *phydev)
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
if (val < 0)
return val;
priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);
priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) ==
MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH);
/* Enable EDPD mode - saving 600mW */
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);