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drm/amd/display: Source minimum HBlank support

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[Why]
Some sink devices wish to have access to the minimum
HBlank supported by the ASIC.

[How]
Make the ASIC minimum HBlank available in Source
Device information address 0x340.

Signed-off-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ashley Thomas
2020-10-01 00:16:05 -07:00
committed by Alex Deucher
parent 2e7b43e629
commit 9248681f68
14 changed files with 49 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+2
View File
@@ -418,6 +418,8 @@ char *dc_status_to_str(enum dc_status status)
return "Fail clk below minimum";
case DC_FAIL_CLK_BELOW_CFG_REQUIRED:
return "Fail clk below required CFG (hard_min in PPLIB)";
case DC_NOT_SUPPORTED:
return "The operation is not supported.";
case DC_ERROR_UNEXPECTED:
return "Unexpected error";
}
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+32 -7
View File
@@ -17,16 +17,16 @@
#define DC_LOGGER \
link->ctx->logger
#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
/* maximum pre emphasis level allowed for each voltage swing level*/
static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
PRE_EMPHASIS_LEVEL3,
PRE_EMPHASIS_LEVEL2,
PRE_EMPHASIS_LEVEL1,
PRE_EMPHASIS_DISABLED };
/* maximum pre emphasis level allowed for each voltage swing level*/
static const enum dc_pre_emphasis
voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
PRE_EMPHASIS_LEVEL2,
PRE_EMPHASIS_LEVEL1,
PRE_EMPHASIS_DISABLED };
enum {
POST_LT_ADJ_REQ_LIMIT = 6,
@@ -4372,6 +4372,7 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
void dpcd_set_source_specific_data(struct dc_link *link)
{
if (!link->dc->vendor_signature.is_valid) {
enum dc_status result_write_min_hblank = DC_NOT_SUPPORTED;
struct dpcd_amd_signature amd_signature;
amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
@@ -4390,6 +4391,30 @@ void dpcd_set_source_specific_data(struct dc_link *link)
(uint8_t *)(&amd_signature),
sizeof(amd_signature));
if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
link->dc->caps.min_horizontal_blanking_period != 0) {
uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
result_write_min_hblank = core_link_write_dpcd(link,
DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
sizeof(hblank_size));
}
DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
"result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
result_write_min_hblank,
link->link_index,
link->ctx->dce_version,
DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
link->dc->caps.min_horizontal_blanking_period,
link->dpcd_caps.branch_dev_id,
link->dpcd_caps.branch_dev_name[0],
link->dpcd_caps.branch_dev_name[1],
link->dpcd_caps.branch_dev_name[2],
link->dpcd_caps.branch_dev_name[3],
link->dpcd_caps.branch_dev_name[4],
link->dpcd_caps.branch_dev_name[5]);
} else {
core_link_write_dpcd(link, DP_SOURCE_OUI,
link->dc->vendor_signature.data.raw,
drivers/gpu/drm/amd/display/dc/dc.h
+1
View File
@@ -156,6 +156,7 @@ struct dc_caps {
uint32_t dmdata_alloc_size;
unsigned int max_cursor_size;
unsigned int max_video_width;
unsigned int min_horizontal_blanking_period;
int linear_pitch_alignment;
bool dcc_const_color;
bool dynamic_audio;
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+1
View File
@@ -1066,6 +1066,7 @@ static bool dce100_resource_construct(
dc->caps.i2c_speed_in_khz = 40;
dc->caps.i2c_speed_in_khz = 40;
dc->caps.max_cursor_size = 128;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dual_link_dvi = true;
dc->caps.disable_dp_clk_share = true;
dc->caps.extended_aux_timeout_support = false;
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+1
View File
@@ -1368,6 +1368,7 @@ static bool dce110_resource_construct(
dc->caps.i2c_speed_in_khz = 40;
dc->caps.i2c_speed_in_khz_hdcp = 40;
dc->caps.max_cursor_size = 128;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.is_apu = true;
dc->caps.extended_aux_timeout_support = false;
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+1
View File
@@ -1235,6 +1235,7 @@ static bool dce112_resource_construct(
dc->caps.i2c_speed_in_khz = 100;
dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
dc->caps.max_cursor_size = 128;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dual_link_dvi = true;
dc->caps.extended_aux_timeout_support = false;
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+1
View File
@@ -1075,6 +1075,7 @@ static bool dce120_resource_construct(
dc->caps.i2c_speed_in_khz = 100;
dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
dc->caps.max_cursor_size = 128;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dual_link_dvi = true;
dc->caps.psp_setup_panel_mode = true;
dc->caps.extended_aux_timeout_support = false;
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+3
View File
@@ -965,6 +965,7 @@ static bool dce80_construct(
dc->caps.i2c_speed_in_khz = 40;
dc->caps.i2c_speed_in_khz_hdcp = 40;
dc->caps.max_cursor_size = 128;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dual_link_dvi = true;
dc->caps.extended_aux_timeout_support = false;
@@ -1164,6 +1165,7 @@ static bool dce81_construct(
dc->caps.i2c_speed_in_khz = 40;
dc->caps.i2c_speed_in_khz_hdcp = 40;
dc->caps.max_cursor_size = 128;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.is_apu = true;
/*************************************************
@@ -1362,6 +1364,7 @@ static bool dce83_construct(
dc->caps.i2c_speed_in_khz = 40;
dc->caps.i2c_speed_in_khz_hdcp = 40;
dc->caps.max_cursor_size = 128;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.is_apu = true;
/*************************************************
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+1
View File
@@ -1418,6 +1418,7 @@ static bool dcn10_resource_construct(
dc->caps.i2c_speed_in_khz = 100;
dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
dc->caps.max_cursor_size = 256;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.max_slave_planes = 1;
dc->caps.is_apu = true;
dc->caps.post_blend_color_processing = false;
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+1
View File
@@ -3813,6 +3813,7 @@ static bool dcn20_resource_construct(
dc->caps.i2c_speed_in_khz = 100;
dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
dc->caps.max_cursor_size = 256;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
dc->caps.max_slave_planes = 1;
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+1
View File
@@ -1930,6 +1930,7 @@ static bool dcn21_resource_construct(
dc->caps.i2c_speed_in_khz = 100;
dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
dc->caps.max_cursor_size = 256;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
dc->caps.max_slave_planes = 1;
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+1
View File
@@ -2606,6 +2606,7 @@ static bool dcn30_resource_construct(
dc->caps.i2c_speed_in_khz = 100;
dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
dc->caps.max_cursor_size = 256;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
dc->caps.max_slave_planes = 1;
drivers/gpu/drm/amd/display/dc/inc/core_status.h
+2
View File
@@ -50,6 +50,8 @@ enum dc_status {
DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/
DC_FAIL_CLK_BELOW_CFG_REQUIRED = 23, /*THIS IS hard_min in PPLIB*/
DC_NOT_SUPPORTED = 24,
DC_ERROR_UNEXPECTED = -1
};
drivers/gpu/drm/amd/display/include/dpcd_defs.h
+1
View File
@@ -156,5 +156,6 @@ enum dpcd_psr_sink_states {
#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK 0x326
#define DP_SOURCE_BACKLIGHT_CONTROL 0x32E
#define DP_SOURCE_BACKLIGHT_ENABLE 0x32F
#define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED 0x340
#endif /* __DAL_DPCD_DEFS_H__ */