soc: tegra: pmc: add bootrom command support
This commit is contained in:
Azkali Manad
@@ -133,6 +133,22 @@
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#define PMC_RST_STATUS_LP0 4
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#define PMC_RST_STATUS_AOTAG 5
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/* Bootrom comand register */
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#define PMC_REG_8bit_MASK 0xFF
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#define PMC_REG_16bit_MASK 0xFFFF
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#define PMC_BR_COMMAND_I2C_ADD_MASK 0x7F
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#define PMC_BR_COMMAND_WR_COMMANDS_MASK 0x3F
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#define PMC_BR_COMMAND_WR_COMMANDS_SHIFT 8
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#define PMC_BR_COMMAND_OPERAND_SHIFT 15
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#define PMC_BR_COMMAND_CSUM_MASK 0xFF
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#define PMC_BR_COMMAND_CSUM_SHIFT 16
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#define PMC_BR_COMMAND_PMUX_MASK 0x7
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#define PMC_BR_COMMAND_PMUX_SHIFT 24
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#define PMC_BR_COMMAND_CTRL_ID_MASK 0x7
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#define PMC_BR_COMMAND_CTRL_ID_SHIFT 27
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#define PMC_BR_COMMAND_CTRL_TYPE_SHIFT 30
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#define PMC_BR_COMMAND_RST_EN_SHIFT 31
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#define IO_DPD_REQ 0x1b8
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#define IO_DPD_REQ_CODE_IDLE (0U << 30)
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#define IO_DPD_REQ_CODE_OFF (1U << 30)
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@@ -163,6 +179,9 @@
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#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
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#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
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/* Scratch 250: Bootrom i2c command base */
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#define PMC_BR_COMMAND_BASE 0x908
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#define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
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#define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
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@@ -346,6 +365,7 @@ struct tegra_pmc_soc {
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bool has_tsense_reset;
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bool has_gpu_clamps;
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bool has_bootrom_command;
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bool needs_mbist_war;
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bool has_impl_33v_pwr;
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bool maybe_tz_only;
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@@ -485,13 +505,37 @@ to_powergate(struct generic_pm_domain *domain)
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return container_of(domain, struct tegra_powergate, genpd);
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}
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/* Bootrom commands structures */
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struct tegra_bootrom_block {
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const char *name;
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int address;
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bool reg_8bits;
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bool data_8bits;
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bool i2c_controller;
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int controller_id;
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bool enable_reset;
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int ncommands;
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u32 *commands;
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};
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struct tegra_bootrom_commands {
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u32 command_retry_count;
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u32 delay_between_commands;
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u32 wait_before_bus_clear;
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struct tegra_bootrom_block *blocks;
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int nblocks;
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};
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static struct tegra_bootrom_commands *br_rst_commands;
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static struct tegra_bootrom_commands *br_off_commands;
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static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
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{
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struct arm_smccc_res res;
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if (pmc->tz_only) {
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arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
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0, 0, 0, &res);
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arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset,
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0, 0, 0, 0, 0, &res);
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if (res.a0) {
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if (pmc->dev)
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dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
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@@ -501,7 +545,7 @@ static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
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res.a0);
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}
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return res.a1;
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return (u32)res.a1;
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}
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return readl(pmc->base + offset);
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@@ -1133,6 +1177,324 @@ static void tegra_pmc_program_reboot_reason(const char *cmd)
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tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
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}
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/* PMC Bootrom commands */
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static int tegra_pmc_parse_bootrom_cmd(struct device *dev,
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struct device_node *np,
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struct tegra_bootrom_commands **br_cmds)
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{
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struct device_node *child;
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struct tegra_bootrom_commands *bcommands;
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int *command_ptr;
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struct tegra_bootrom_block *block;
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int nblocks;
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u32 reg, data, pval;
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u32 *wr_commands;
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int count, nblock, ncommands, i, data_shift;
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int ret;
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int sz_bcommand, sz_blocks;
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nblocks = of_get_available_child_count(np);
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if (!nblocks) {
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dev_info(dev, "PMC: No Bootrom Command\n");
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return -ENOENT;
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}
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count = 0;
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for_each_available_child_of_node(np, child) {
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ret = of_property_count_u32_elems(child,
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"nvidia,write-commands");
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if (ret < 0) {
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dev_err(dev, "PMC: Node %s does not have write-commnds\n",
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child->full_name);
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return -EINVAL;
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}
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count += ret / 2;
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}
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sz_bcommand = (sizeof(*bcommands) + 0x3) & ~0x3;
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sz_blocks = (sizeof(*block) + 0x3) & ~0x3;
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bcommands = devm_kzalloc(dev, sz_bcommand + nblocks * sz_blocks +
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count * sizeof(u32), GFP_KERNEL);
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if (!bcommands)
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return -ENOMEM;
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bcommands->nblocks = nblocks;
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bcommands->blocks = (void *)bcommands + sz_bcommand;
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command_ptr = (void *)bcommands->blocks + nblocks * sz_blocks;
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of_property_read_u32(np, "nvidia,command-retries-count",
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&bcommands->command_retry_count);
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of_property_read_u32(np, "nvidia,delay-between-commands-us",
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&bcommands->delay_between_commands);
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ret = of_property_read_u32(np, "nvidia,wait-before-start-bus-clear-us",
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&bcommands->wait_before_bus_clear);
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if (ret < 0)
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of_property_read_u32(np, "nvidia,wait-start-bus-clear-us",
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&bcommands->wait_before_bus_clear);
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nblock = 0;
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for_each_available_child_of_node(np, child) {
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block = &bcommands->blocks[nblock];
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ret = of_property_read_u32(child, "reg", &pval);
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if (ret) {
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dev_err(dev, "PMC: Reg property missing on block %s\n",
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child->name);
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return ret;
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}
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block->address = pval;
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of_property_read_string(child, "nvidia,command-names",
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&block->name);
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block->reg_8bits = !of_property_read_bool(child,
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"nvidia,enable-16bit-register");
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block->data_8bits = !of_property_read_bool(child,
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"nvidia,enable-16bit-data");
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block->i2c_controller = of_property_read_bool(child,
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"nvidia,controller-type-i2c");
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block->enable_reset = of_property_read_bool(child,
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"nvidia,enable-controller-reset");
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count = of_property_count_u32_elems(child,
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"nvidia,write-commands");
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ncommands = count / 2;
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block->commands = command_ptr;
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command_ptr += ncommands;
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wr_commands = block->commands;
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data_shift = (block->data_8bits) ? 8 : 16;
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for (i = 0; i < ncommands; ++i) {
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of_property_read_u32_index(child,
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"nvidia,write-commands",
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i * 2, ®);
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of_property_read_u32_index(child,
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"nvidia,write-commands",
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i * 2 + 1, &data);
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wr_commands[i] = (data << data_shift) | reg;
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}
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block->ncommands = ncommands;
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nblock++;
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}
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*br_cmds = bcommands;
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return 0;
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}
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static void tegra_pmc_write_bootrom_command(struct tegra_pmc *pmc,
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u32 command_offset, unsigned long val)
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{
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tegra_pmc_writel(pmc, val, command_offset + PMC_BR_COMMAND_BASE);
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}
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static int tegra_pmc_read_bootrom_cmd(struct device *dev,
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struct tegra_bootrom_commands **br_rst_cmds,
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struct tegra_bootrom_commands **br_off_cmds)
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{
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struct device_node *np = dev->of_node;
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struct device_node *br_np, *rst_np, *off_np;
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int ret;
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*br_rst_cmds = NULL;
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*br_off_cmds = NULL;
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br_np = of_find_node_by_name(np, "bootrom-commands");
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if (!br_np) {
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dev_info(dev, "PMC: Bootrom commmands not found\n");
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return -ENOENT;
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}
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rst_np = of_find_node_by_name(br_np, "reset-commands");
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if (!rst_np) {
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dev_info(dev, "PMC: bootrom-commands used for reset\n");
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rst_np = br_np;
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}
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ret = tegra_pmc_parse_bootrom_cmd(dev, rst_np, br_rst_cmds);
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if (ret < 0)
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return ret;
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if (rst_np == br_np)
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return 0;
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off_np = of_find_node_by_name(br_np, "power-off-commands");
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if (!off_np)
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return 0;
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ret = tegra_pmc_parse_bootrom_cmd(dev, off_np, br_off_cmds);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int tegra_pmc_configure_bootrom_scratch(
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struct device *dev,
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struct tegra_bootrom_commands *br_commands,
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struct tegra_br_cmd_cfg *bcfg, u32 bcfg_size)
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{
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struct tegra_pmc *pmc = dev_get_drvdata(dev);
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struct tegra_bootrom_block *block;
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int i, j, k;
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u32 cmd, tmp_cmd;
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int reg_offset = 1;
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int bcfg_idx = 0;
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u32 reg_data_mask, edit_data_mask;
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int cmd_pw;
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u32 block_add, block_val, csum;
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for (i = 0; i < br_commands->nblocks; ++i) {
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block = &br_commands->blocks[i];
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cmd = block->address & PMC_BR_COMMAND_I2C_ADD_MASK;
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cmd |= block->ncommands << PMC_BR_COMMAND_WR_COMMANDS_SHIFT;
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if (!block->reg_8bits || !block->data_8bits)
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cmd |= BIT(PMC_BR_COMMAND_OPERAND_SHIFT);
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if (block->enable_reset)
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cmd |= BIT(PMC_BR_COMMAND_RST_EN_SHIFT);
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cmd |= (block->controller_id & PMC_BR_COMMAND_CTRL_ID_MASK) <<
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PMC_BR_COMMAND_CTRL_ID_SHIFT;
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/* Checksum will be added after parsing from reg/data */
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tegra_pmc_write_bootrom_command(pmc, reg_offset * 4, cmd);
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block_add = reg_offset * 4;
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block_val = cmd;
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reg_offset++;
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cmd_pw = (block->reg_8bits && block->data_8bits) ? 2 : 1;
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reg_data_mask = (cmd_pw == 2) ? 0xFFFF : 0xFFFFFFFFUL;
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csum = 0;
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for (j = 0; j < block->ncommands; j++) {
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tmp_cmd = block->commands[j] & reg_data_mask;
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if (bcfg_idx < bcfg_size &&
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bcfg[bcfg_idx].dev == i &&
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bcfg[bcfg_idx].idx == j) {
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edit_data_mask = (cmd_pw == 2) ?
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0xFF00UL : 0xFFFF0000UL;
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tmp_cmd &= ~edit_data_mask;
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tmp_cmd |= (bcfg[bcfg_idx].val <<
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(cmd_pw == 2 ? 8 : 16)) & edit_data_mask;
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bcfg_idx++;
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}
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cmd = tmp_cmd;
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if (cmd_pw == 2) {
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j++;
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if (j == block->ncommands)
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goto reg_update;
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tmp_cmd = (block->commands[j] & reg_data_mask) << 16;
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if (bcfg_idx < bcfg_size &&
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bcfg[bcfg_idx].dev == i &&
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bcfg[bcfg_idx].idx == j) {
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edit_data_mask = 0xFF000000UL;
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tmp_cmd &= ~edit_data_mask;
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tmp_cmd |= (bcfg[bcfg_idx].val << 24) &
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edit_data_mask;
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bcfg_idx++;
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}
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cmd |= tmp_cmd;
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}
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reg_update:
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tegra_pmc_write_bootrom_command(pmc, reg_offset * 4, cmd);
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for (k = 0; k < 4; ++k)
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csum += (cmd >> (k * 8)) & 0xFF;
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reg_offset++;
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}
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for (k = 0; k < 4; ++k)
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csum += (block_val >> (k * 8)) & 0xFF;
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csum = 0x100 - csum;
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block_val = (block_val & 0xFF00FFFF) | ((csum & 0xFF) << 16);
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tegra_pmc_write_bootrom_command(pmc, block_add, block_val);
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}
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cmd = br_commands->command_retry_count & 0x7;
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cmd |= (br_commands->delay_between_commands & 0x1F) << 3;
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cmd |= (br_commands->nblocks & 0x7) << 8;
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cmd |= (br_commands->wait_before_bus_clear & 0x1F) << 11;
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tegra_pmc_write_bootrom_command(pmc, 0, cmd);
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return 0;
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}
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int tegra_pmc_edit_bootrom_scratch_poff(struct device *dev,
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struct tegra_br_cmd_cfg *bcfg,
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u32 bcfg_size)
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{
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if (br_off_commands) {
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tegra_pmc_configure_bootrom_scratch(dev, br_off_commands,
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bcfg, bcfg_size);
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return 0;
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}
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return -EINVAL;
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}
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int tegra_pmc_edit_bootrom_scratch_reset(struct device *dev,
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struct tegra_br_cmd_cfg *bcfg,
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u32 bcfg_size)
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{
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if (br_rst_commands) {
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tegra_pmc_configure_bootrom_scratch(dev, br_rst_commands,
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bcfg, bcfg_size);
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return 0;
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}
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return -EINVAL;
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}
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static int tegra_pmc_init_bootrom_power_off_cmd(struct device *dev)
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{
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int ret;
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if (!br_off_commands) {
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dev_info(dev, "PMC: Power Off Command not available\n");
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return 0;
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}
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ret = tegra_pmc_configure_bootrom_scratch(dev, br_off_commands, NULL, 0);
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if (ret < 0) {
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dev_err(dev, "PMC: Failed to configure power-off command: %d\n",
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ret);
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return ret;
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}
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dev_info(dev, "PMC: Successfully configure power-off commands\n");
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return 0;
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}
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static int tegra_pmc_init_bootrom_cmds(struct device *dev)
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{
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int ret;
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ret = tegra_pmc_read_bootrom_cmd(dev, &br_rst_commands,
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&br_off_commands);
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if (ret < 0) {
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if (ret == -ENOENT)
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ret = 0;
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else
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dev_info(dev,
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"PMC: Failed to read bootrom cmd: %d\n", ret);
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return ret;
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}
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/* if (br_off_commands)
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set_soc_specific_power_off(tegra_pmc_soc_power_off); */
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ret = tegra_pmc_configure_bootrom_scratch(dev, br_rst_commands, NULL, 0);
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if (ret < 0) {
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dev_info(dev, "PMC: Failed to write bootrom scratch register: %d\n",
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ret);
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return ret;
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}
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dev_info(dev, "PMC: Successfully configure bootrom reset commands\n");
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return 0;
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}
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static int tegra_pmc_reboot_notify(struct notifier_block *this,
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unsigned long action, void *data)
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{
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@@ -1165,16 +1527,24 @@ static int tegra_pmc_restart_handler(struct sys_off_data *data)
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static int tegra_pmc_power_off_handler(struct sys_off_data *data)
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{
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/*
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* Reboot Nexus 7 into special bootloader mode if USB cable is
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* connected in order to display battery status and power off.
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*/
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/* Handle special case devices */
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if (of_machine_is_compatible("asus,grouper") &&
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power_supply_is_system_supplied()) {
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/**
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* Reboot Nexus 7 into special bootloader mode if USB cable is
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* connected in order to display battery status and power off.
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*/
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const u32 go_to_charger_mode = 0xa5a55a5a;
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tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37);
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tegra_pmc_restart();
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} else if (pmc->soc->has_bootrom_command) {
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/**
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* Configure PMC power off cmds for special-case devices with
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* brom commands for reset.
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*/
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tegra_pmc_init_bootrom_power_off_cmd(pmc->dev);
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tegra_pmc_restart();
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}
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return NOTIFY_DONE;
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@@ -3010,6 +3380,9 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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if (err < 0)
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goto cleanup_powergates;
|
||||
|
||||
if (pmc->soc->has_bootrom_command)
|
||||
tegra_pmc_init_bootrom_cmds(&pdev->dev);
|
||||
|
||||
mutex_lock(&pmc->powergates_lock);
|
||||
iounmap(pmc->base);
|
||||
pmc->base = base;
|
||||
@@ -3723,6 +4096,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
|
||||
.needs_mbist_war = true,
|
||||
.has_impl_33v_pwr = false,
|
||||
.maybe_tz_only = true,
|
||||
.has_bootrom_command = false,
|
||||
.num_io_pads = ARRAY_SIZE(tegra210_io_pads),
|
||||
.io_pads = tegra210_io_pads,
|
||||
.num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
|
||||
@@ -3843,6 +4217,7 @@ static const struct tegra_pmc_soc tegra210b01_pmc_soc = {
|
||||
.needs_mbist_war = true,
|
||||
.has_impl_33v_pwr = false,
|
||||
.maybe_tz_only = true,
|
||||
.has_bootrom_command = true,
|
||||
.num_io_pads = ARRAY_SIZE(tegra210b01_io_pads),
|
||||
.io_pads = tegra210b01_io_pads,
|
||||
.num_pin_descs = ARRAY_SIZE(tegra210b01_pin_descs),
|
||||
|
||||
@@ -227,6 +227,18 @@ static inline enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
struct tegra_br_cmd_cfg {
|
||||
u32 dev;
|
||||
u32 idx;
|
||||
u32 val;
|
||||
};
|
||||
|
||||
int tegra_pmc_edit_bootrom_scratch_poff(struct device *dev,
|
||||
struct tegra_br_cmd_cfg *bcfg,
|
||||
u32 bcfg_size);
|
||||
int tegra_pmc_edit_bootrom_scratch_reset(struct device *dev,
|
||||
struct tegra_br_cmd_cfg *bcfg,
|
||||
u32 bcfg_size);
|
||||
void tegra_pmc_r2p_setup(const char *cmd, bool panic_occurred);
|
||||
|
||||
#endif /* __SOC_TEGRA_PMC_H__ */
|
||||
|
||||
Reference in New Issue
Block a user