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@@ -83,13 +83,9 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
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serdes_phy_addr = intel_priv->mdio_adhoc_addr;
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/* assert clk_req */
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data = mdiobus_read(priv->mii, serdes_phy_addr,
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SERDES_GCR0);
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data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
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data |= SERDES_PLL_CLK;
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mdiobus_write(priv->mii, serdes_phy_addr,
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SERDES_GCR0, data);
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mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
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/* check for clk_ack assertion */
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data = serdes_status_poll(priv, serdes_phy_addr,
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@@ -103,13 +99,9 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
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}
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/* assert lane reset */
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data = mdiobus_read(priv->mii, serdes_phy_addr,
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SERDES_GCR0);
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data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
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data |= SERDES_RST;
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mdiobus_write(priv->mii, serdes_phy_addr,
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SERDES_GCR0, data);
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mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
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/* check for assert lane reset reflection */
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data = serdes_status_poll(priv, serdes_phy_addr,
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@@ -123,14 +115,12 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
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}
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/* move power state to P0 */
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data = mdiobus_read(priv->mii, serdes_phy_addr,
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SERDES_GCR0);
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data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
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data &= ~SERDES_PWR_ST_MASK;
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data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
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mdiobus_write(priv->mii, serdes_phy_addr,
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SERDES_GCR0, data);
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mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
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/* Check for P0 state */
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data = serdes_status_poll(priv, serdes_phy_addr,
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@@ -159,14 +149,12 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
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serdes_phy_addr = intel_priv->mdio_adhoc_addr;
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/* move power state to P3 */
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data = mdiobus_read(priv->mii, serdes_phy_addr,
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SERDES_GCR0);
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data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
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data &= ~SERDES_PWR_ST_MASK;
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data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
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mdiobus_write(priv->mii, serdes_phy_addr,
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SERDES_GCR0, data);
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mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
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/* Check for P3 state */
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data = serdes_status_poll(priv, serdes_phy_addr,
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@@ -180,13 +168,9 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
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}
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/* de-assert clk_req */
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data = mdiobus_read(priv->mii, serdes_phy_addr,
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SERDES_GCR0);
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data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
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data &= ~SERDES_PLL_CLK;
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mdiobus_write(priv->mii, serdes_phy_addr,
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SERDES_GCR0, data);
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mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
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/* check for clk_ack de-assert */
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data = serdes_status_poll(priv, serdes_phy_addr,
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@@ -200,13 +184,9 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
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}
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/* de-assert lane reset */
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data = mdiobus_read(priv->mii, serdes_phy_addr,
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SERDES_GCR0);
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data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
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data &= ~SERDES_RST;
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mdiobus_write(priv->mii, serdes_phy_addr,
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SERDES_GCR0, data);
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mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
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/* check for de-assert lane reset reflection */
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data = serdes_status_poll(priv, serdes_phy_addr,
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@@ -252,6 +232,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat)
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static int intel_mgbe_common_data(struct pci_dev *pdev,
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struct plat_stmmacenet_data *plat)
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{
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int ret;
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int i;
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plat->clk_csr = 5;
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@@ -324,7 +305,12 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
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dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
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plat->stmmac_clk = NULL;
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}
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clk_prepare_enable(plat->stmmac_clk);
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ret = clk_prepare_enable(plat->stmmac_clk);
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if (ret) {
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clk_unregister_fixed_rate(plat->stmmac_clk);
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return ret;
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}
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/* Set default value for multicast hash bins */
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plat->multicast_filter_bins = HASH_TABLE_SIZE;
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@@ -341,16 +327,11 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
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static int ehl_common_data(struct pci_dev *pdev,
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struct plat_stmmacenet_data *plat)
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{
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int ret;
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plat->rx_queues_to_use = 8;
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plat->tx_queues_to_use = 8;
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plat->clk_ptp_rate = 200000000;
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ret = intel_mgbe_common_data(pdev, plat);
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if (ret)
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return ret;
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return 0;
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return intel_mgbe_common_data(pdev, plat);
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}
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static int ehl_sgmii_data(struct pci_dev *pdev,
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@@ -366,7 +347,7 @@ static int ehl_sgmii_data(struct pci_dev *pdev,
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return ehl_common_data(pdev, plat);
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}
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static struct stmmac_pci_info ehl_sgmii1g_pci_info = {
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static struct stmmac_pci_info ehl_sgmii1g_info = {
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.setup = ehl_sgmii_data,
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};
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@@ -380,7 +361,7 @@ static int ehl_rgmii_data(struct pci_dev *pdev,
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return ehl_common_data(pdev, plat);
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}
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static struct stmmac_pci_info ehl_rgmii1g_pci_info = {
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static struct stmmac_pci_info ehl_rgmii1g_info = {
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.setup = ehl_rgmii_data,
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};
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@@ -399,7 +380,7 @@ static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
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return ehl_pse0_common_data(pdev, plat);
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}
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static struct stmmac_pci_info ehl_pse0_rgmii1g_pci_info = {
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static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
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.setup = ehl_pse0_rgmii1g_data,
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};
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@@ -412,7 +393,7 @@ static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
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return ehl_pse0_common_data(pdev, plat);
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}
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static struct stmmac_pci_info ehl_pse0_sgmii1g_pci_info = {
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static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
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.setup = ehl_pse0_sgmii1g_data,
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};
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@@ -431,7 +412,7 @@ static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
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return ehl_pse1_common_data(pdev, plat);
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}
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static struct stmmac_pci_info ehl_pse1_rgmii1g_pci_info = {
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static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
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.setup = ehl_pse1_rgmii1g_data,
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};
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@@ -444,23 +425,18 @@ static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
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return ehl_pse1_common_data(pdev, plat);
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}
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static struct stmmac_pci_info ehl_pse1_sgmii1g_pci_info = {
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static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
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.setup = ehl_pse1_sgmii1g_data,
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};
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static int tgl_common_data(struct pci_dev *pdev,
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struct plat_stmmacenet_data *plat)
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{
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int ret;
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plat->rx_queues_to_use = 6;
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plat->tx_queues_to_use = 4;
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plat->clk_ptp_rate = 200000000;
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ret = intel_mgbe_common_data(pdev, plat);
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if (ret)
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return ret;
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return 0;
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return intel_mgbe_common_data(pdev, plat);
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}
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static int tgl_sgmii_data(struct pci_dev *pdev,
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@@ -474,7 +450,7 @@ static int tgl_sgmii_data(struct pci_dev *pdev,
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return tgl_common_data(pdev, plat);
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}
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static struct stmmac_pci_info tgl_sgmii1g_pci_info = {
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static struct stmmac_pci_info tgl_sgmii1g_info = {
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.setup = tgl_sgmii_data,
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};
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@@ -577,7 +553,7 @@ static int quark_default_data(struct pci_dev *pdev,
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return 0;
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}
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static const struct stmmac_pci_info quark_pci_info = {
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static const struct stmmac_pci_info quark_info = {
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.setup = quark_default_data,
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};
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@@ -600,11 +576,9 @@ static int intel_eth_pci_probe(struct pci_dev *pdev,
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struct intel_priv_data *intel_priv;
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struct plat_stmmacenet_data *plat;
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struct stmmac_resources res;
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int i;
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int ret;
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intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv),
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GFP_KERNEL);
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intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
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if (!intel_priv)
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return -ENOMEM;
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@@ -631,15 +605,9 @@ static int intel_eth_pci_probe(struct pci_dev *pdev,
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return ret;
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}
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/* Get the base address of device */
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for (i = 0; i < PCI_STD_NUM_BARS; i++) {
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if (pci_resource_len(pdev, i) == 0)
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continue;
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ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev));
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if (ret)
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return ret;
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break;
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}
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ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
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if (ret)
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return ret;
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pci_set_master(pdev);
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@@ -650,14 +618,23 @@ static int intel_eth_pci_probe(struct pci_dev *pdev,
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if (ret)
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return ret;
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pci_enable_msi(pdev);
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ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
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if (ret < 0)
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return ret;
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memset(&res, 0, sizeof(res));
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res.addr = pcim_iomap_table(pdev)[i];
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res.wol_irq = pdev->irq;
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res.irq = pdev->irq;
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res.addr = pcim_iomap_table(pdev)[0];
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res.wol_irq = pci_irq_vector(pdev, 0);
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res.irq = pci_irq_vector(pdev, 0);
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return stmmac_dvr_probe(&pdev->dev, plat, &res);
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ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
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if (ret) {
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pci_free_irq_vectors(pdev);
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clk_disable_unprepare(plat->stmmac_clk);
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clk_unregister_fixed_rate(plat->stmmac_clk);
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}
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return ret;
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}
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/**
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@@ -671,19 +648,15 @@ static void intel_eth_pci_remove(struct pci_dev *pdev)
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{
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struct net_device *ndev = dev_get_drvdata(&pdev->dev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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int i;
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stmmac_dvr_remove(&pdev->dev);
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if (priv->plat->stmmac_clk)
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clk_unregister_fixed_rate(priv->plat->stmmac_clk);
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pci_free_irq_vectors(pdev);
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for (i = 0; i < PCI_STD_NUM_BARS; i++) {
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if (pci_resource_len(pdev, i) == 0)
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continue;
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pcim_iounmap_regions(pdev, BIT(i));
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break;
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}
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clk_disable_unprepare(priv->plat->stmmac_clk);
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clk_unregister_fixed_rate(priv->plat->stmmac_clk);
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pcim_iounmap_regions(pdev, BIT(0));
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pci_disable_device(pdev);
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}
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@@ -742,26 +715,19 @@ static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
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#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
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static const struct pci_device_id intel_eth_pci_id_table[] = {
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{ PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID,
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&ehl_pse0_rgmii1g_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID,
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&ehl_pse0_sgmii1g_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID,
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&ehl_pse0_sgmii1g_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID,
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&ehl_pse1_rgmii1g_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID,
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&ehl_pse1_sgmii1g_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID,
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&ehl_pse1_sgmii1g_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) },
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{ PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) },
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{}
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};
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MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
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static struct pci_driver intel_eth_pci_driver = {
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