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Merge tag 'ti-k3-dt-for-v6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt

Browse Source 
TI K3 device tree updates for v6.12

Generic Fixups/Cleanups:

- AM62, AM62A, AM64, AM65, AM62P: ESM node cleanups
- J784s4, J721s2, J721e, AM65: FSS (Flash subsystem) fixups for ranges
- j721e/j7200/j721s2/am68/am69 SK/SoM, IOT2050: Disable of R5F lockstep
- j721e/j7200/j721s2/am68/am69 reserve GP timers for firmware usage.
- Misc device tree warning fixups: Serdes simple-mfd fixes for
  am654-serdes-ctrl; rename of gpio-hog nodes; mux-controller node names

SoC Specific features and Fixes:

New boards:
- AM67A/J722s based BeagleBoard.org Foundation's BeagleY-AI

AM62:
- Thermal throttling enabled

AM62A:
- Add E5010 JPEG encoder

AM62P:
- gpio-reserved ranges
- SK: drop cts/rts for wakeup_uart0 firmware console pinmux

J722s: (AM62P variant)
- IPC/Remote proc for C7x and R5F
- gpio-reserved ranges
- EVM: Add main_uart5 description and CAN support.

AM64x:
- adc description fixes for dtbs_check warnings
- tqma64xxl and phyboard-electra: Add PRUSS ICSSG capability
- CPSW Ethernet is now disabled by default at SoC level and enabled explicitly
  at board level.
- USB property to add fall back to j721e

AM65x:
- IOT2050: Add overlays for M.2, add Eth phy LED description
- idk: Fixes for DMA causing dtbs_check warning, Add MCAN

J721e:
- SK and beagleboneai64: Fixes for inverted C6x carveouts

J721s2:
- AM68-SK: Fixes for mmc clkb internal mux, ospi partition for uboot.backup
  alignment fixup.

J784s4:
- WDT clock ID fix.
- EVM: Use 4 lanes for PCIe0.

* tag 'ti-k3-dt-for-v6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (57 commits)
  arm64: dts: ti: k3-j722s-evm: Enable Inter-Processor Communication
  arm64: dts: ti: k3-j722s-main: Add R5F and C7x remote processor nodes
  arm64: dts: ti: k3-am68-sk-som: Update Partition info for OSPI Flash
  arm64: dts: ti: Add k3-am67a-beagley-ai
  dt-bindings: arm: ti: Add BeagleY-AI
  arm64: dts: ti: iot2050: Declare Ethernet PHY leds
  arm64: dts: ti: k3-am65: Add ESM nodes
  arm64: dts: ti: k3-am64: Add more ESM interrupt sources
  arm64: dts: ti: k3-am62a: Add ESM nodes
  arm64: dts: ti: k3-am62: Add comments to ESM nodes
  arm64: dts: ti: k3-am62p: Fix ESM interrupt sources
  arm64: dts: ti: k3-am62p: Remove 'reserved' status for ESM
  arm64: dts: ti: k3-j721s2-evm-gesi-exp-board: Rename gpio-hog node name
  arm64: dts: ti: k3-am642-evm-nand: Rename pinctrl node and gpio-hog names
  arm64: dts: ti: k3-am654-idk: Fix dtbs_check warning in ICSSG dmas
  arm64: dts: ti: k3-j784s4: Include entire FSS region in ranges
  arm64: dts: ti: k3-j721s2: Include entire FSS region in ranges
  arm64: dts: ti: k3-j721e: Include entire FSS region in ranges
  arm64: dts: ti: k3-am65: Include entire FSS region in ranges
  arm64: dts: ti: k3-am64: add USB fallback compatible to J721E
  ...

Link: https://lore.kernel.org/r/20240903155701.q7soxtplbkfofwxt@entering
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-09-05 10:14:45 +00:00
parent 5d9e36498b 5b035d14a5
commit 7b6eee4f0e
52 changed files with 1590 additions and 114 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/arm/ti/k3.yaml
+1
View File
@@ -140,6 +140,7 @@ properties:
- description: K3 J722S SoC and Boards
items:
- enum:
- beagle,am67a-beagley-ai
- ti,j722s-evm
- const: ti,j722s
Documentation/devicetree/bindings/soc/ti/ti,am654-serdes-ctrl.yaml
+2 -1
View File
@@ -14,6 +14,7 @@ properties:
items:
- const: ti,am654-serdes-ctrl
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
@@ -31,7 +32,7 @@ additionalProperties: false
examples:
- |
clock@4080 {
compatible = "ti,am654-serdes-ctrl", "syscon";
compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd";
reg = <0x4080 0x4>;
mux-controller {
arch/arm64/boot/dts/ti/Makefile
+7
View File
@@ -73,10 +73,16 @@ k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \
k3-am654-pcie-usb3.dtbo
k3-am654-evm-dtbs := k3-am654-base-board.dtb k3-am654-icssg2.dtbo
k3-am654-idk-dtbs := k3-am654-evm.dtb k3-am654-idk.dtbo k3-am654-pcie-usb2.dtbo
k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-dtbs := k3-am6548-iot2050-advanced-m2.dtb \
k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtbo
k3-am6548-iot2050-advanced-m2-bkey-usb3-dtbs := k3-am6548-iot2050-advanced-m2.dtb \
k3-am6548-iot2050-advanced-m2-bkey-usb3.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2-bkey-usb3.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-sm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
@@ -110,6 +116,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
# Boards with J722s SoC
dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
# Boards with J784s4 SoC
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+1
View File
@@ -241,6 +241,7 @@
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
/* Interrupt sources: rti0, rti1, rti15, wrti0, rti2, rti3 */
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
};
arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
+1
View File
@@ -19,6 +19,7 @@
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */
ti,esm-pins = <0>, <1>, <2>, <85>;
};
arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
+34
View File
@@ -12,12 +12,29 @@ thermal_zones: thermal-zones {
thermal-sensors = <&wkup_vtm0 0>;
trips {
main0_alert: main0-alert {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
main0_crit: main0-crit {
temperature = <105000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&main0_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
main1_thermal: main1-thermal {
@@ -26,11 +43,28 @@ thermal_zones: thermal-zones {
thermal-sensors = <&wkup_vtm0 1>;
trips {
main1_alert: main1-alert {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
main1_crit: main1-crit {
temperature = <105000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&main1_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
arch/arm64/boot/dts/ti/k3-am625.dtsi
+4
View File
@@ -50,6 +50,7 @@
next-level-cache = <&L2_0>;
operating-points-v2 = <&a53_opp_table>;
clocks = <&k3_clks 135 0>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -66,6 +67,7 @@
next-level-cache = <&L2_0>;
operating-points-v2 = <&a53_opp_table>;
clocks = <&k3_clks 136 0>;
#cooling-cells = <2>;
};
cpu2: cpu@2 {
@@ -82,6 +84,7 @@
next-level-cache = <&L2_0>;
operating-points-v2 = <&a53_opp_table>;
clocks = <&k3_clks 137 0>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
@@ -98,6 +101,7 @@
next-level-cache = <&L2_0>;
operating-points-v2 = <&a53_opp_table>;
clocks = <&k3_clks 138 0>;
#cooling-cells = <2>;
};
};
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
+18
View File
@@ -265,6 +265,14 @@
pinctrl-single,function-mask = <0xffffffff>;
};
main_esm: esm@420000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x420000 0x0 0x1000>;
bootph-pre-ram;
/* Interrupt sources: rti0, rti1, wrti0, rti4, rti2, rti3 */
ti,esm-pins = <192>, <193>, <195>, <204>, <209>, <210>;
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
@@ -1088,4 +1096,14 @@
clocks = <&k3_clks 204 2>;
power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
};
e5010: jpeg-encoder@fd20000 {
compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc";
reg = <0x00 0xfd20000 0x00 0x100>,
<0x00 0xfd20200 0x00 0x200>;
reg-names = "core", "mmu";
clocks = <&k3_clks 201 0>;
power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
};
arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
+8
View File
@@ -15,6 +15,14 @@
status = "disabled";
};
mcu_esm: esm@4100000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x4100000 0x0 0x1000>;
bootph-pre-ram;
/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */
ti,esm-pins = <0>, <1>, <2>, <85>;
};
/*
* The MCU domain timer interrupts are routed only to the ESM module,
* and not currently available for Linux. The MCU domain timers are
arch/arm64/boot/dts/ti/k3-am62a.dtsi
+2
View File
@@ -61,6 +61,8 @@
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
<0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */
<0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+2 -1
View File
@@ -260,8 +260,9 @@
main_esm: esm@420000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
bootph-pre-ram;
/* Interrupt sources: rti0, rti1, wrti0 rti2, rti3, rti15 */
ti,esm-pins = <224>, <225>, <227>, <241>, <242>, <248>;
};
main_timer0: timer@2400000 {
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
+2 -2
View File
@@ -26,9 +26,9 @@
mcu_esm: esm@4100000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>, <2>, <85>;
status = "reserved";
bootph-pre-ram;
/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0, wrti0 */
ti,esm-pins = <0>, <1>, <2>, <85>, <86>;
};
/*
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+1
View File
@@ -65,5 +65,6 @@
&main_gpio1 {
gpio-ranges = <&main_pmx0 0 94 32>, <&main_pmx0 42 137 5>,
<&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
gpio-reserved-ranges = <32 10>;
ti,ngpio = <52>;
};
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
-2
View File
@@ -645,8 +645,6 @@
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */
AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */
AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */
AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */
>;
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+6 -2
View File
@@ -389,7 +389,8 @@
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
ti,esm-pins = <160>, <161>;
/* Interrupt sources: rti0, rti1, rti8, rti9, rti10, rti11 */
ti,esm-pins = <160>, <161>, <162>, <163>, <164>, <165>;
};
main_uart0: serial@2800000 {
@@ -677,6 +678,7 @@
assigned-clock-parents = <&k3_clks 13 9>;
clock-names = "fck";
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
dmas = <&main_pktdma 0xC500 15>,
<&main_pktdma 0xC501 15>,
@@ -701,6 +703,7 @@
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
ti,syscon-efuse = <&main_conf 0x200>;
status = "disabled";
};
cpsw_port2: port@2 {
@@ -709,6 +712,7 @@
label = "port2";
phys = <&phy_gmii_sel 2>;
mac-address = [00 00 00 00 00 00];
status = "disabled";
};
};
@@ -759,7 +763,7 @@
};
usbss0: cdns-usb@f900000 {
compatible = "ti,am64-usb";
compatible = "ti,am64-usb", "ti,j721e-usb";
reg = <0x00 0xf900000 0x00 0x100>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
+2 -1
View File
@@ -158,6 +158,7 @@
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>;
/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */
ti,esm-pins = <0>, <1>, <2>, <85>;
};
};
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
+2 -4
View File
@@ -185,6 +185,7 @@
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&cpsw_rgmii1_pins_default>;
status = "okay";
};
&cpsw3g_mdio {
@@ -208,10 +209,7 @@
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw_port2 {
status = "disabled";
status = "okay";
};
&mailbox0_cluster2 {
arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso
+3 -3
View File
@@ -12,7 +12,7 @@
#include "k3-pinctrl.h"
&main_pmx0 {
gpmc0_pins_default: gpmc0-pins-default {
gpmc0_default_pins: gpmc0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */
@@ -50,7 +50,7 @@
};
&main_gpio0 {
gpio0-36 {
gpmc0-hog {
bootph-all;
gpio-hog;
gpios = <36 0>;
@@ -67,7 +67,7 @@
&gpmc0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&gpmc0_pins_default>;
pinctrl-0 = <&gpmc0_default_pins>;
#address-cells = <2>;
#size-cells = <1>;
arch/arm64/boot/dts/ti/k3-am642-evm.dts
+7
View File
@@ -616,17 +616,20 @@
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
status = "okay";
};
&cpsw_port1 {
bootph-all;
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
status = "okay";
};
&cpsw3g_mdio {
@@ -646,6 +649,10 @@
&tscadc0 {
/* ADC is reserved for R5 usage */
status = "reserved";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&ospi0 {
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
+146
View File
@@ -28,6 +28,8 @@
model = "PHYTEC phyBOARD-Electra-AM64x RDK";
aliases {
ethernet1 = &icssg0_emac0;
ethernet2 = &icssg0_emac1;
mmc1 = &sdhci1;
serial2 = &main_uart0;
serial3 = &main_uart1;
@@ -55,6 +57,73 @@
standby-gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>;
};
/* Dual Ethernet application node on PRU-ICSSG0 */
ethernet {
compatible = "ti,am642-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&icssg0_rgmii1_pins_default>, <&icssg0_rgmii2_pins_default>;
interrupt-parent = <&icssg0_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
sram = <&oc_sram>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
<&main_pktdma 0xc101 15>, /* egress slice 0 */
<&main_pktdma 0xc102 15>, /* egress slice 0 */
<&main_pktdma 0xc103 15>, /* egress slice 0 */
<&main_pktdma 0xc104 15>, /* egress slice 1 */
<&main_pktdma 0xc105 15>, /* egress slice 1 */
<&main_pktdma 0xc106 15>, /* egress slice 1 */
<&main_pktdma 0xc107 15>, /* egress slice 1 */
<&main_pktdma 0x4100 15>, /* ingress slice 0 */
<&main_pktdma 0x4101 15>; /* ingress slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1";
ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
ti,mii-g-rt = <&icssg0_mii_g_rt>;
ti,mii-rt = <&icssg0_mii_rt>;
ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
icssg0_emac0: port@0 {
reg = <0>;
phy-handle = <&icssg0_phy1>;
phy-mode = "rgmii-id";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
ti,syscon-rgmii-delay = <&main_conf 0x4100>;
};
icssg0_emac1: port@1 {
reg = <1>;
phy-handle = <&icssg0_phy2>;
phy-mode = "rgmii-id";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
ti,syscon-rgmii-delay = <&main_conf 0x4104>;
};
};
};
keys {
compatible = "gpio-keys";
autorepeat;
@@ -118,6 +187,12 @@
>;
};
clkout0_pins_default: clkout0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* (A19) EXT_REFCLK1.CLKOUT0 */
>;
};
gpio_keys_pins_default: gpio-keys-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */
@@ -125,6 +200,49 @@
>;
};
icssg0_mdio_pins_default: icssg0-mdio-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
AM64X_IOPAD(0x01A8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
AM64X_IOPAD(0x01AC, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
>;
};
icssg0_rgmii1_pins_default: icssg0-rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
AM64X_IOPAD(0x016c, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
AM64X_IOPAD(0x018c, PIN_OUTPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */
AM64X_IOPAD(0x0190, PIN_OUTPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */
AM64X_IOPAD(0x0194, PIN_OUTPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */
AM64X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */
AM64X_IOPAD(0x019c, PIN_OUTPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */
AM64X_IOPAD(0x01a0, PIN_OUTPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
>;
};
icssg0_rgmii2_pins_default: icssg0-rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01b0, PIN_INPUT, 2) /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
AM64X_IOPAD(0x01b4, PIN_INPUT, 2) /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
AM64X_IOPAD(0x01b8, PIN_INPUT, 2) /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
AM64X_IOPAD(0x01bc, PIN_INPUT, 2) /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
AM64X_IOPAD(0x01c0, PIN_INPUT, 2) /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
AM64X_IOPAD(0x01c8, PIN_INPUT, 2) /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
AM64X_IOPAD(0x01dc, PIN_OUTPUT, 2) /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_TD0 */
AM64X_IOPAD(0x01e0, PIN_OUTPUT, 2) /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_TD1 */
AM64X_IOPAD(0x01e4, PIN_OUTPUT, 2) /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_TD2 */
AM64X_IOPAD(0x01e8, PIN_OUTPUT, 2) /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_TD3 */
AM64X_IOPAD(0x01ec, PIN_OUTPUT, 2) /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_TX_CTL */
AM64X_IOPAD(0x01f0, PIN_OUTPUT, 2) /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */
@@ -198,6 +316,34 @@
};
};
&icssg0_mdio {
pinctrl-names = "default";
pinctrl-0 = <&icssg0_mdio_pins_default &clkout0_pins_default>;
status = "okay";
icssg0_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reset-gpios = <&main_gpio1 18 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
};
icssg0_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <0x2>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reset-gpios = <&main_gpio1 19 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
};
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
arch/arm64/boot/dts/ti/k3-am642-sk.dts
+3
View File
@@ -527,16 +527,19 @@
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
status = "okay";
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
status = "okay";
};
&cpsw3g_mdio {
arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
+2 -4
View File
@@ -177,6 +177,7 @@
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_default_pins>;
status = "okay";
};
&cpsw3g_mdio {
@@ -210,10 +211,7 @@
&cpsw_port1 {
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy0>;
};
&cpsw_port2 {
status = "disabled";
status = "okay";
};
&icssg1_mdio {
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
+100 -4
View File
@@ -24,6 +24,8 @@
aliases {
ethernet0 = &cpsw_port1;
ethernet1 = &icssg1_emac0;
ethernet2 = &icssg1_emac1;
i2c1 = &mcu_i2c0;
mmc1 = &sdhci1;
serial0 = &mcu_uart0;
@@ -71,6 +73,66 @@
};
};
icssg1_eth: icssg1-eth {
compatible = "ti,am642-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&pru_icssg1_rgmii1_pins>, <&pru_icssg1_rgmii2_pins>;
interrupt-parent = <&icssg1_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
<&main_pktdma 0xc201 15>, /* egress slice 0 */
<&main_pktdma 0xc202 15>, /* egress slice 0 */
<&main_pktdma 0xc203 15>, /* egress slice 0 */
<&main_pktdma 0xc204 15>, /* egress slice 1 */
<&main_pktdma 0xc205 15>, /* egress slice 1 */
<&main_pktdma 0xc206 15>, /* egress slice 1 */
<&main_pktdma 0xc207 15>, /* egress slice 1 */
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
<&main_pktdma 0x4201 15>; /* ingress slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1";
sram = <&oc_sram>;
firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
ti,mii-g-rt = <&icssg1_mii_g_rt>;
ti,mii-rt = <&icssg1_mii_rt>;
ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
icssg1_emac0: port@0 {
reg = <0>;
phy-handle = <&icssg1_phy0c>;
phy-mode = "rgmii-id";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
icssg1_emac1: port@1 {
reg = <1>;
phy-handle = <&icssg1_phy03>;
phy-mode = "rgmii-id";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
};
fan0: pwm-fan {
compatible = "pwm-fan";
pinctrl-names = "default";
@@ -119,15 +181,13 @@
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&cpsw_pins>;
status = "okay";
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
status = "disabled";
status = "okay";
};
&cpsw3g_mdio {
@@ -154,6 +214,42 @@
status = "okay";
};
&icssg1_mdio {
pinctrl-names = "default";
pinctrl-0 = <&pru_icssg1_mdio_pins>;
status = "okay";
/* phy-mode is fixed up to rgmii-rxid by prueth driver to account for
* the SoC integration, so the only rx-internal-delay and no
* tx-internal-delay is set for the PHYs.
*/
icssg1_phy03: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x3>;
reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
icssg1_phy0c: ethernet-phy@c {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0xc>;
reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&main_gpio0_digital_pins>,
arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi
-5
View File
@@ -9,11 +9,6 @@
* Common bits of the IOT2050 Basic and Advanced variants, PG2
*/
&mcu_r5fss0 {
/* lock-step mode not supported on PG2 boards */
ti,cluster-mode = <0>;
};
&main_pmx0 {
cp2102n_reset_pin_default: cp2102n-reset-default-pins {
pinctrl-single,pins = <
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+51
View File
@@ -627,11 +627,62 @@
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_SPEED_LAN;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_SPEED_LAN;
};
};
};
icssg0_eth1_phy: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_SPEED_LAN;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_SPEED_LAN;
};
};
};
};
&mcu_r5fss0 {
/* lock-step mode not supported on iot2050 boards */
ti,cluster-mode = <0>;
};
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+10 -2
View File
@@ -54,6 +54,14 @@
};
};
main_esm: esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x700000 0x00 0x1000>;
bootph-pre-ram;
/* Interrupt sources: rti0, rti1, rti2, rti3 */
ti,esm-pins = <224>, <225>, <226>, <227>;
};
serdes0: serdes@900000 {
compatible = "ti,phy-am654-serdes";
reg = <0x0 0x900000 0x0 0x2000>;
@@ -478,7 +486,7 @@
ranges = <0x0 0x0 0x00100000 0x1c000>;
serdes0_clk: clock@4080 {
compatible = "ti,am654-serdes-ctrl", "syscon";
compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd";
reg = <0x4080 0x4>;
serdes0_mux: mux-controller {
@@ -489,7 +497,7 @@
};
serdes1_clk: clock@4090 {
compatible = "ti,am654-serdes-ctrl", "syscon";
compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd";
reg = <0x4090 0x4>;
serdes1_mux: mux-controller {
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+12 -4
View File
@@ -292,13 +292,13 @@
ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
<0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
<0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */
<0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* OSPI0 Memory */
<0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */
<0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>, /* FSS data region 1 */
<0x4 0x00000000 0x4 0x00000000 0x4 0x00000000>; /* FSS data region 0/3 */
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
<0x5 0x00000000 0x1 0x00000000>;
interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
@@ -316,7 +316,7 @@
ospi1: spi@47050000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47050000 0x0 0x100>,
<0x7 0x00000000 0x1 0x00000000>;
<0x7 0x00000000 0x1 0x00000000>;
interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
@@ -440,6 +440,14 @@
};
};
mcu_esm: esm@40800000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x40800000 0x00 0x1000>;
bootph-pre-ram;
/* Interrupt sources: mrti0, mrti1 */
ti,esm-pins = <104>, <105>;
};
mcu_rti1: watchdog@40610000 {
compatible = "ti,j7-rti-wdt";
reg = <0x0 0x40610000 0x0 0x100>;
arch/arm64/boot/dts/ti/k3-am65.dtsi
+5 -7
View File
@@ -69,11 +69,10 @@
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>,
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
cbass_mcu: bus@28380000 {
compatible = "simple-bus";
@@ -89,9 +88,8 @@
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
cbass_wakeup: bus@42040000 {
compatible = "simple-bus";
arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
-5
View File
@@ -22,8 +22,3 @@
compatible = "siemens,iot2050-basic", "ti,am654";
model = "SIMATIC IOT2050 Basic";
};
&mcu_r5fss0 {
/* lock-step mode not supported on this board */
ti,cluster-mode = <0>;
};
arch/arm64/boot/dts/ti/k3-am654-idk.dtso
+63 -6
View File
@@ -8,6 +8,7 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-pinctrl.h"
@@ -58,9 +59,7 @@
<&main_udmap 0xc107>, /* egress slice 1 */
<&main_udmap 0x4100>, /* ingress slice 0 */
<&main_udmap 0x4101>, /* ingress slice 1 */
<&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
<&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
<&main_udmap 0x4101>; /* ingress slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1";
@@ -126,9 +125,7 @@
<&main_udmap 0xc207>, /* egress slice 1 */
<&main_udmap 0x4200>, /* ingress slice 0 */
<&main_udmap 0x4201>, /* ingress slice 1 */
<&main_udmap 0x4202>, /* mgmnt rsp slice 0 */
<&main_udmap 0x4203>; /* mgmnt rsp slice 1 */
<&main_udmap 0x4201>; /* ingress slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1";
@@ -154,6 +151,24 @@
};
};
};
transceiver1: can-phy0 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&mcan0_gpio_pins_default>;
standby-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
};
transceiver2: can-phy1 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&mcan1_gpio_pins_default>;
standby-gpios = <&main_gpio1 67 GPIO_ACTIVE_LOW>;
};
};
&main_pmx0 {
@@ -243,6 +258,34 @@
AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
>;
};
mcan0_gpio_pins_default: mcan0-gpio-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x023c, PIN_INPUT, 7) /* (V25) PRG0_PRU0_GPIO18:GPIO1_47 */
>;
};
mcan1_gpio_pins_default: mcan1-gpio-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x028c, PIN_INPUT, 7) /* (Y26) PRG0_PRU1_GPIO18.GPIO1_67 */
>;
};
};
&wkup_pmx0 {
mcu_mcan0_pins_default: mcu-mcan0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00ac, PIN_INPUT_PULLUP, 0) /* (W2) MCU_MCAN0_RX */
AM65X_WKUP_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (W1) MCU_MCAN0_TX */
>;
};
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00c4, PIN_INPUT_PULLUP, 1) /* (AD3) WKUP_GPIO0_5.MCU_MCAN1_RX */
AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT_PULLUP, 1) /* (AC3) WKUP_GPIO0_4.MCU_MCAN1_TX */
>;
};
};
&icssg0_mdio {
@@ -294,3 +337,17 @@
pinctrl-names = "default";
pinctrl-0 = <&icssg1_iep0_pins_default>;
};
&m_can0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
phys = <&transceiver1>;
status = "okay";
};
&m_can1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan1_pins_default>;
phys = <&transceiver2>;
status = "okay";
};
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
+27
View File
@@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0
/*
* IOT2050 M.2 variant, overlay for B-key PCIE0_LANE0 + E-key PCIE1_LANE0
* Copyright (c) Siemens AG, 2022-2024
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
&pcie0_rc {
num-lanes = <1>;
phys = <&serdes0 PHY_TYPE_PCIE 1>;
phy-names = "pcie-phy0";
reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie1_rc {
status = "okay";
};
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso
+47
View File
@@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0
/*
* IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0
* Copyright (c) Siemens AG, 2022-2024
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
&serdes0 {
assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
};
&pcie0_rc {
status = "disabled";
};
&pcie1_rc {
pinctrl-names = "default";
pinctrl-0 = <&minipcie_pins_default>;
num-lanes = <1>;
phys = <&serdes1 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy0";
reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&dwc3_0 {
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
phys = <&serdes0 PHY_TYPE_USB3 0>;
phy-names = "usb3-phy";
};
&usb0 {
maximum-speed = "super-speed";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts
+393
View File
@@ -0,0 +1,393 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* https://beagley-ai.org/
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2024 Robert Nelson, BeagleBoard.org Foundation
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-j722s.dtsi"
/ {
compatible = "beagle,am67a-beagley-ai", "ti,j722s";
model = "BeagleBoard.org BeagleY-AI";
aliases {
serial0 = &wkup_uart0;
serial2 = &main_uart0;
mmc1 = &sdhci1;
rtc0 = &rtc;
};
chosen {
stdout-path = &main_uart0;
};
memory@80000000 {
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
device_type = "memory";
bootph-pre-ram;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
no-map;
};
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
no-map;
};
wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
};
vsys_5v0: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
bootph-all;
};
vdd_3v3: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_5v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
pinctrl-names = "default";
pinctrl-0 = <&vdd_3v3_sd_pins_default>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpio = <&main_gpio1 50 GPIO_ACTIVE_HIGH>;
bootph-all;
};
vdd_sd_dv: regulator-4 {
compatible = "regulator-gpio";
regulator-name = "tlv71033";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_pins_default>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vsys_5v0>;
gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0>,
<3300000 0x1>;
bootph-all;
};
vsys_io_1v8: regulator-5 {
compatible = "regulator-fixed";
regulator-name = "vsys_io_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
vsys_io_1v2: regulator-6 {
compatible = "regulator-fixed";
regulator-name = "vsys_io_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_default>;
led-0 {
gpios = <&main_gpio0 11 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-1 {
gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
default-state = "on";
};
};
};
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */
J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */
>;
bootph-all;
};
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
>;
bootph-all;
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x0244, PIN_OUTPUT, 7) /* (A24) MMC1_SDWP.GPIO1_49 */
>;
bootph-all;
};
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */
J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */
J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */
J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */
J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */
J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */
J722S_IOPAD(0x0240, PIN_INPUT, 7) /* (B24) MMC1_SDCD.GPIO1_48 */
>;
bootph-all;
};
mdio_pins_default: mdio-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */
J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */
J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */
J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */
J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */
J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */
J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */
J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */
J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */
J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */
J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */
J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
>;
};
led_pins_default: led-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x002c, PIN_OUTPUT, 7) /* (K26) OSPI0_CSn0.GPIO0_11 */
J722S_IOPAD(0x0030, PIN_OUTPUT, 7) /* (K23) OSPI0_CSn1.GPIO0_12 */
>;
};
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (B23) EXTINTn */
>;
};
vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x0254, PIN_OUTPUT, 7) /* (E25) USB0_DRVVBUS.GPIO1_50 */
>;
};
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default>;
status = "okay";
};
&cpsw3g_mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins_default>;
status = "okay";
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
};
&main_gpio1 {
status = "okay";
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
bootph-all;
status = "okay";
};
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */
J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */
J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */
J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */
>;
bootph-all;
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */
J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */
>;
bootph-all;
};
};
&wkup_uart0 {
/* WKUP UART0 is used by Device Manager firmware */
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
bootph-all;
status = "reserved";
};
&wkup_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <100000>;
bootph-all;
status = "okay";
tps65219: pmic@30 {
compatible = "ti,tps65219";
reg = <0x30>;
buck1-supply = <&vsys_5v0>;
buck2-supply = <&vsys_5v0>;
buck3-supply = <&vsys_5v0>;
ldo1-supply = <&vdd_3v3>;
ldo3-supply = <&vdd_3v3>;
ldo4-supply = <&vdd_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
bootph-all;
system-power-controller;
ti,power-button;
regulators {
buck1_reg: buck1 {
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck2_reg: buck2 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-name = "VDDSHV5_SDIO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-allow-bypass;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-name = "VDD_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-name = "VDDA_PHY_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: ldo4 {
regulator-name = "VDDA_PLL_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
};
rtc: rtc@68 {
compatible = "dallas,ds1340";
reg = <0x68>;
};
};
&sdhci1 {
/* SD/MMC */
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
disable-wp;
cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
cd-debounce-delay-ms = <100>;
bootph-all;
ti,fails-without-test-cd;
status = "okay";
};
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+1
View File
@@ -204,6 +204,7 @@
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
+35 -2
View File
@@ -215,9 +215,9 @@
reg = <0x680000 0x40000>;
};
partition@740000 {
partition@6c0000 {
label = "ospi.env.backup";
reg = <0x740000 0x40000>;
reg = <0x6c0000 0x40000>;
};
partition@800000 {
@@ -302,6 +302,39 @@
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0 {
ti,cluster-mode = <0>;
};
&main_r5fss1 {
ti,cluster-mode = <0>;
};
/* Timers are used by Remoteproc firmware */
&main_timer0 {
status = "reserved";
};
&main_timer1 {
status = "reserved";
};
&main_timer2 {
status = "reserved";
};
&main_timer3 {
status = "reserved";
};
&main_timer4 {
status = "reserved";
};
&main_timer5 {
status = "reserved";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
arch/arm64/boot/dts/ti/k3-am69-sk.dts
+53
View File
@@ -979,6 +979,59 @@
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0 {
ti,cluster-mode = <0>;
};
&main_r5fss1 {
ti,cluster-mode = <0>;
};
/* Timers are used by Remoteproc firmware */
&main_timer0 {
status = "reserved";
};
&main_timer1 {
status = "reserved";
};
&main_timer2 {
status = "reserved";
};
&main_timer3 {
status = "reserved";
};
&main_timer4 {
status = "reserved";
};
&main_timer5 {
status = "reserved";
};
&main_timer6 {
status = "reserved";
};
&main_timer7 {
status = "reserved";
};
&main_timer8 {
status = "reserved";
};
&main_timer9 {
status = "reserved";
};
&main_r5fss2 {
ti,cluster-mode = <0>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+19 -2
View File
@@ -84,13 +84,13 @@
};
};
mux0: mux-controller {
mux0: mux-controller-0 {
compatible = "gpio-mux";
#mux-state-cells = <1>;
mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
};
mux1: mux-controller {
mux1: mux-controller-1 {
compatible = "gpio-mux";
#mux-state-cells = <1>;
mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
@@ -262,6 +262,23 @@
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0 {
ti,cluster-mode = <0>;
};
/* Timers are used by Remoteproc firmware */
&main_timer0 {
status = "reserved";
};
&main_timer1 {
status = "reserved";
};
&main_timer2 {
status = "reserved";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
+2 -2
View File
@@ -123,7 +123,7 @@
no-map;
};
c66_1_dma_memory_region: c66-dma-memory@a6000000 {
c66_0_dma_memory_region: c66-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x100000>;
no-map;
@@ -135,7 +135,7 @@
no-map;
};
c66_0_dma_memory_region: c66-dma-memory@a7000000 {
c66_1_dma_memory_region: c66-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x100000>;
no-map;
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+5 -5
View File
@@ -354,8 +354,8 @@
<0x0 0x47034000 0x0 0x47034000 0x0 0x100>, /* HBMC Control */
<0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
<0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */
<0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* HBMC/OSPI0 Memory */
<0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */
<0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>, /* FSS data region 1 */
<0x4 0x00000000 0x4 0x00000000 0x4 0x00000000>; /* FSS data region 0/3 */
hbmc_mux: mux-controller@47000004 {
compatible = "reg-mux";
@@ -367,7 +367,7 @@
hbmc: hyperbus@47034000 {
compatible = "ti,am654-hbmc";
reg = <0x00 0x47034000 0x00 0x100>,
<0x05 0x00000000 0x01 0x0000000>;
<0x05 0x00000000 0x01 0x00000000>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 102 0>;
assigned-clocks = <&k3_clks 102 5>;
@@ -381,7 +381,7 @@
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
<0x5 0x00000000 0x1 0x00000000>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
@@ -399,7 +399,7 @@
ospi1: spi@47050000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47050000 0x0 0x100>,
<0x7 0x00000000 0x1 0x00000000>;
<0x7 0x00000000 0x1 0x00000000>;
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+39 -2
View File
@@ -120,7 +120,7 @@
no-map;
};
c66_1_dma_memory_region: c66-dma-memory@a6000000 {
c66_0_dma_memory_region: c66-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x100000>;
no-map;
@@ -132,7 +132,7 @@
no-map;
};
c66_0_dma_memory_region: c66-dma-memory@a7000000 {
c66_1_dma_memory_region: c66-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x100000>;
no-map;
@@ -1311,6 +1311,43 @@
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0 {
ti,cluster-mode = <0>;
};
&main_r5fss1 {
ti,cluster-mode = <0>;
};
/* Timers are used by Remoteproc firmware */
&main_timer0 {
status = "reserved";
};
&main_timer1 {
status = "reserved";
};
&main_timer2 {
status = "reserved";
};
&main_timer12 {
status = "reserved";
};
&main_timer13 {
status = "reserved";
};
&main_timer14 {
status = "reserved";
};
&main_timer15 {
status = "reserved";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+37
View File
@@ -561,6 +561,43 @@
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0 {
ti,cluster-mode = <0>;
};
&main_r5fss1 {
ti,cluster-mode = <0>;
};
/* Timers are used by Remoteproc firmware */
&main_timer0 {
status = "reserved";
};
&main_timer1 {
status = "reserved";
};
&main_timer2 {
status = "reserved";
};
&main_timer12 {
status = "reserved";
};
&main_timer13 {
status = "reserved";
};
&main_timer14 {
status = "reserved";
};
&main_timer15 {
status = "reserved";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
arch/arm64/boot/dts/ti/k3-j721e.dtsi
+3 -5
View File
@@ -145,8 +145,7 @@
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
cbass_mcu_wakeup: bus@28380000 {
compatible = "simple-bus";
@@ -162,9 +161,8 @@
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
};
};
arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
+1 -1
View File
@@ -48,7 +48,7 @@
};
&exp1 {
p15 {
p15-hog {
/* P15 - EXP_MUX2 */
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+2 -2
View File
@@ -622,8 +622,8 @@
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+35 -2
View File
@@ -134,13 +134,13 @@
};
};
mux0: mux-controller {
mux0: mux-controller-0 {
compatible = "gpio-mux";
#mux-state-cells = <1>;
mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
};
mux1: mux-controller {
mux1: mux-controller-1 {
compatible = "gpio-mux";
#mux-state-cells = <1>;
mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
@@ -516,6 +516,39 @@
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0 {
ti,cluster-mode = <0>;
};
&main_r5fss1 {
ti,cluster-mode = <0>;
};
/* Timers are used by Remoteproc firmware */
&main_timer0 {
status = "reserved";
};
&main_timer1 {
status = "reserved";
};
&main_timer2 {
status = "reserved";
};
&main_timer3 {
status = "reserved";
};
&main_timer4 {
status = "reserved";
};
&main_timer5 {
status = "reserved";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
arch/arm64/boot/dts/ti/k3-j721s2.dtsi
+3 -5
View File
@@ -141,8 +141,7 @@
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
cbass_mcu_wakeup: bus@28380000 {
compatible = "simple-bus";
@@ -158,9 +157,8 @@
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
};
arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+246
View File
@@ -20,6 +20,7 @@
aliases {
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart5;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
@@ -51,12 +52,71 @@
no-map;
};
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
c7x_0_dma_memory_region: c7x-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
c7x_0_memory_region: c7x-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
c7x_1_dma_memory_region: c7x-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
c7x_1_memory_region: c7x-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x1c00000>;
alignment = <0x1000>;
no-map;
};
};
vmain_pd: regulator-0 {
@@ -162,10 +222,39 @@
clocks = <&audio_refclk1>;
};
};
transceiver0: can-phy0 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
standby-gpios = <&mcu_gpio0 12 GPIO_ACTIVE_HIGH>;
};
transceiver1: can-phy1 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
};
transceiver2: can-phy2 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp1 17 GPIO_ACTIVE_HIGH>;
};
};
&main_pmx0 {
main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x1dc, PIN_INPUT, 0) /* (C22) MCAN0_RX */
J722S_IOPAD(0x1d8, PIN_OUTPUT, 0) /*(D22) MCAN0_TX */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */
@@ -182,6 +271,13 @@
bootph-all;
};
main_uart5_pins_default: main-uart5-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x0108, PIN_INPUT, 3) /* (J27) UART5_RXD */
J722S_IOPAD(0x010c, PIN_OUTPUT, 3) /* (H27) UART5_TXD */
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */
@@ -301,8 +397,35 @@
bootph-all;
};
&main_uart5 {
/* MAIN UART 5 is used by System firmware */
pinctrl-names = "default";
pinctrl-0 = <&main_uart5_pins_default>;
status = "reserved";
};
&mcu_pmx0 {
mcu_mcan0_pins_default: mcu-mcan0-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */
J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */
>;
};
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */
J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */
>;
};
mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x0030, PIN_OUTPUT, 7) /* (C3) MCU_GPIO0_12 */
>;
};
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */
@@ -494,6 +617,104 @@
bootph-all;
};
&mailbox0_cluster0 {
status = "okay";
mbox_wkup_r5_0: mbox-wkup-r5-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
};
&mailbox0_cluster1 {
status = "okay";
mbox_mcu_r5_0: mbox-mcu-r5-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
};
&mailbox0_cluster2 {
status = "okay";
mbox_c7x_0: mbox-c7x-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
};
&mailbox0_cluster3 {
status = "okay";
mbox_main_r5_0: mbox-main-r5-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c7x_1: mbox-c7x-1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
/* Timers are used by Remoteproc firmware */
&main_timer0 {
status = "reserved";
};
&main_timer1 {
status = "reserved";
};
&main_timer2 {
status = "reserved";
};
&wkup_r5fss0 {
status = "okay";
};
&wkup_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>;
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
<&wkup_r5fss0_core0_memory_region>;
};
&mcu_r5fss0 {
status = "okay";
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&main_r5fss0 {
status = "okay";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&c7x_0 {
mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
memory-region = <&c7x_0_dma_memory_region>,
<&c7x_0_memory_region>;
status = "okay";
};
&c7x_1 {
mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
memory-region = <&c7x_1_dma_memory_region>,
<&c7x_1_memory_region>;
status = "okay";
};
&serdes_ln_ctrl {
idle-states = <J722S_SERDES0_LANE0_USB>,
<J722S_SERDES1_LANE0_PCIE0_LANE0>;
@@ -566,3 +787,28 @@
0 0 0 0
>;
};
&mcu_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
phys = <&transceiver0>;
status = "okay";
};
&mcu_mcan1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan1_pins_default>;
phys = <&transceiver1>;
status = "okay";
};
&main_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&transceiver2>;
status = "okay";
};
&mcu_gpio0 {
status = "okay";
};
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+62
View File
@@ -153,6 +153,67 @@
dr_mode = "otg";
};
};
main_r5fss0: r5fss@78400000 {
compatible = "ti,am62-r5fss";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x78400000 0x00 0x78400000 0x8000>,
<0x78500000 0x00 0x78500000 0x8000>;
power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
main_r5fss0_core0: r5f@78400000 {
compatible = "ti,am62-r5f";
reg = <0x78400000 0x00008000>,
<0x78500000 0x00008000>;
reg-names = "atcm", "btcm";
resets = <&k3_reset 262 1>;
firmware-name = "j722s-main-r5f0_0-fw";
ti,sci = <&dmsc>;
ti,sci-dev-id = <262>;
ti,sci-proc-ids = <0x04 0xff>;
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
c7x_0: dsp@7e000000 {
compatible = "ti,am62a-c7xv-dsp";
reg = <0x00 0x7e000000 0x00 0x00200000>;
reg-names = "l2sram";
resets = <&k3_reset 208 1>;
firmware-name = "j722s-c71_0-fw";
ti,sci = <&dmsc>;
ti,sci-dev-id = <208>;
ti,sci-proc-ids = <0x30 0xff>;
status = "disabled";
};
c7x_1: dsp@7e200000 {
compatible = "ti,am62a-c7xv-dsp";
reg = <0x00 0x7e200000 0x00 0x00200000>;
reg-names = "l2sram";
resets = <&k3_reset 268 1>;
firmware-name = "j722s-c71_1-fw";
ti,sci = <&dmsc>;
ti,sci-dev-id = <268>;
ti,sci-proc-ids = <0x31 0xff>;
status = "disabled";
};
};
/* MCU domain overrides */
&mcu_r5fss0_core0 {
firmware-name = "j722s-mcu-r5f0_0-fw";
};
/* Wakeup domain overrides */
&wkup_r5fss0_core0 {
firmware-name = "j722s-wkup-r5f0_0-fw";
};
&main_conf {
@@ -214,5 +275,6 @@
&main_gpio1 {
gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
<&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
gpio-reserved-ranges = <0 7>, <32 10>;
ti,ngpio = <73>;
};
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+56 -2
View File
@@ -1154,6 +1154,59 @@
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0 {
ti,cluster-mode = <0>;
};
&main_r5fss1 {
ti,cluster-mode = <0>;
};
&main_r5fss2 {
ti,cluster-mode = <0>;
};
/* Timers are used by Remoteproc firmware */
&main_timer0 {
status = "reserved";
};
&main_timer1 {
status = "reserved";
};
&main_timer2 {
status = "reserved";
};
&main_timer3 {
status = "reserved";
};
&main_timer4 {
status = "reserved";
};
&main_timer5 {
status = "reserved";
};
&main_timer6 {
status = "reserved";
};
&main_timer7 {
status = "reserved";
};
&main_timer8 {
status = "reserved";
};
&main_timer9 {
status = "reserved";
};
&main_r5fss0_core0 {
status = "okay";
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
@@ -1407,10 +1460,11 @@
serdes1_pcie0_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
cdns,num-lanes = <4>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>,
<&serdes_wiz1 3>, <&serdes_wiz1 4>;
};
};
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+19 -19
View File
@@ -2429,7 +2429,7 @@
watchdog0: watchdog@2200000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2200000 0x00 0x100>;
clocks = <&k3_clks 348 1>;
clocks = <&k3_clks 348 0>;
power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 348 0>;
assigned-clock-parents = <&k3_clks 348 4>;
@@ -2438,7 +2438,7 @@
watchdog1: watchdog@2210000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2210000 0x00 0x100>;
clocks = <&k3_clks 349 1>;
clocks = <&k3_clks 349 0>;
power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 349 0>;
assigned-clock-parents = <&k3_clks 349 4>;
@@ -2447,7 +2447,7 @@
watchdog2: watchdog@2220000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2220000 0x00 0x100>;
clocks = <&k3_clks 350 1>;
clocks = <&k3_clks 350 0>;
power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 350 0>;
assigned-clock-parents = <&k3_clks 350 4>;
@@ -2456,7 +2456,7 @@
watchdog3: watchdog@2230000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2230000 0x00 0x100>;
clocks = <&k3_clks 351 1>;
clocks = <&k3_clks 351 0>;
power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 351 0>;
assigned-clock-parents = <&k3_clks 351 4>;
@@ -2465,7 +2465,7 @@
watchdog4: watchdog@2240000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2240000 0x00 0x100>;
clocks = <&k3_clks 352 1>;
clocks = <&k3_clks 352 0>;
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 352 0>;
assigned-clock-parents = <&k3_clks 352 4>;
@@ -2474,7 +2474,7 @@
watchdog5: watchdog@2250000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2250000 0x00 0x100>;
clocks = <&k3_clks 353 1>;
clocks = <&k3_clks 353 0>;
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 353 0>;
assigned-clock-parents = <&k3_clks 353 4>;
@@ -2483,7 +2483,7 @@
watchdog6: watchdog@2260000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2260000 0x00 0x100>;
clocks = <&k3_clks 354 1>;
clocks = <&k3_clks 354 0>;
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 354 0>;
assigned-clock-parents = <&k3_clks 354 4>;
@@ -2492,7 +2492,7 @@
watchdog7: watchdog@2270000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2270000 0x00 0x100>;
clocks = <&k3_clks 355 1>;
clocks = <&k3_clks 355 0>;
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 355 0>;
assigned-clock-parents = <&k3_clks 355 4>;
@@ -2506,7 +2506,7 @@
watchdog8: watchdog@22f0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x22f0000 0x00 0x100>;
clocks = <&k3_clks 360 1>;
clocks = <&k3_clks 360 0>;
power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 360 0>;
assigned-clock-parents = <&k3_clks 360 4>;
@@ -2517,7 +2517,7 @@
watchdog9: watchdog@2300000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2300000 0x00 0x100>;
clocks = <&k3_clks 356 1>;
clocks = <&k3_clks 356 0>;
power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 356 0>;
assigned-clock-parents = <&k3_clks 356 4>;
@@ -2528,7 +2528,7 @@
watchdog10: watchdog@2310000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2310000 0x00 0x100>;
clocks = <&k3_clks 357 1>;
clocks = <&k3_clks 357 0>;
power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 357 0>;
assigned-clock-parents = <&k3_clks 357 4>;
@@ -2539,7 +2539,7 @@
watchdog11: watchdog@2320000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2320000 0x00 0x100>;
clocks = <&k3_clks 358 1>;
clocks = <&k3_clks 358 0>;
power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 358 0>;
assigned-clock-parents = <&k3_clks 358 4>;
@@ -2550,7 +2550,7 @@
watchdog12: watchdog@2330000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2330000 0x00 0x100>;
clocks = <&k3_clks 359 1>;
clocks = <&k3_clks 359 0>;
power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 359 0>;
assigned-clock-parents = <&k3_clks 359 4>;
@@ -2561,7 +2561,7 @@
watchdog13: watchdog@23c0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23c0000 0x00 0x100>;
clocks = <&k3_clks 361 1>;
clocks = <&k3_clks 361 0>;
power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 361 0>;
assigned-clock-parents = <&k3_clks 361 4>;
@@ -2572,7 +2572,7 @@
watchdog14: watchdog@23d0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23d0000 0x00 0x100>;
clocks = <&k3_clks 362 1>;
clocks = <&k3_clks 362 0>;
power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 362 0>;
assigned-clock-parents = <&k3_clks 362 4>;
@@ -2583,7 +2583,7 @@
watchdog15: watchdog@23e0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23e0000 0x00 0x100>;
clocks = <&k3_clks 363 1>;
clocks = <&k3_clks 363 0>;
power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 363 0>;
assigned-clock-parents = <&k3_clks 363 4>;
@@ -2594,7 +2594,7 @@
watchdog16: watchdog@23f0000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x23f0000 0x00 0x100>;
clocks = <&k3_clks 364 1>;
clocks = <&k3_clks 364 0>;
power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 364 0>;
assigned-clock-parents = <&k3_clks 364 4>;
@@ -2605,7 +2605,7 @@
watchdog17: watchdog@2540000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2540000 0x00 0x100>;
clocks = <&k3_clks 365 1>;
clocks = <&k3_clks 365 0>;
power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 365 0>;
assigned-clock-parents = <&k3_clks 366 4>;
@@ -2616,7 +2616,7 @@
watchdog18: watchdog@2550000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2550000 0x00 0x100>;
clocks = <&k3_clks 366 1>;
clocks = <&k3_clks 366 0>;
power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 366 0>;
assigned-clock-parents = <&k3_clks 366 4>;
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+7 -7
View File
@@ -678,16 +678,16 @@
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
<0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
<0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */
<0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* OSPI0 Memory */
<0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */
ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00000100>, /* FSS Control */
<0x00 0x47040000 0x00 0x47040000 0x00 0x00000100>, /* OSPI0 Control */
<0x00 0x47050000 0x00 0x47050000 0x00 0x00000100>, /* OSPI1 Control */
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x47040000 0x00 0x100>,
<0x05 0x0000000 0x01 0x0000000>;
<0x05 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
@@ -705,7 +705,7 @@
ospi1: spi@47050000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x47050000 0x00 0x100>,
<0x07 0x0000000 0x01 0x0000000>;
<0x07 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
arch/arm64/boot/dts/ti/k3-j784s4.dtsi
+3 -5
View File
@@ -271,8 +271,7 @@
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
cbass_mcu_wakeup: bus@28380000 {
bootph-all;
@@ -289,9 +288,8 @@
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
};
};