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Merge tag 'dt64-cleanup-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt

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Minor improvements in ARM64 DTS for v6.12

1. APM: correct node name to match bindings.
2. Spreadtrum: correct node names to match bindings, order properties to
   match DTS coding style and put SPDX identifier at top of the file as
   expected usually.

* tag 'dt64-cleanup-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
  arm64: dts: sprd: move/add SPDX license to top of the file
  arm64: dts: sprd: reorder clock-names after clocks
  arm64: dts: sprd: rename SDHCI and fuel gauge nodes to match bindings
  arm64: dts: apm: storm: Rename menetphy@3 to ethernet-phy@3

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-09-11 08:06:01 +00:00
parent 15eb92636c a4b3f197bc
commit 765fbe81d7
10 changed files with 37 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/apm/apm-storm.dtsi
+1 -1
View File
@@ -997,7 +997,7 @@
compatible = "apm,xgene-mdio";
#address-cells = <1>;
#size-cells = <0>;
menetphy: menetphy@3 {
menetphy: ethernet-phy@3 {
compatible = "ethernet-phy-id001c.c915";
reg = <0x3>;
};
arch/arm64/boot/dts/sprd/sc2731.dtsi
+2 -3
View File
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Spreadtrum SC2731 PMIC dts file
*
* Copyright (C) 2018, Spreadtrum Communications Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
&adi_bus {
@@ -95,7 +94,7 @@
nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
};
fgu@a00 {
fuel-gauge@a00 {
compatible = "sprd,sc2731-fgu";
reg = <0xa00>;
bat-detect-gpio = <&pmic_eic 9 GPIO_ACTIVE_HIGH>;
arch/arm64/boot/dts/sprd/sc9836-openphone.dts
+1 -2
View File
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
* Spreadtrum SC9836 openphone board DTS file
*
* Copyright (C) 2014, Spreadtrum Communications Inc.
*
* This file is licensed under a dual GPLv2 or X11 license.
*/
/dts-v1/;
arch/arm64/boot/dts/sprd/sc9836.dtsi
+1 -2
View File
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
* Spreadtrum SC9836 SoC DTS file
*
* Copyright (C) 2014, Spreadtrum Communications Inc.
*
* This file is licensed under a dual GPLv2 or X11 license.
*/
#include "sharkl64.dtsi"
arch/arm64/boot/dts/sprd/sc9860.dtsi
+1 -2
View File
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Spreadtrum SC9860 SoC
*
* Copyright (C) 2016, Spreadtrum Communications Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
arch/arm64/boot/dts/sprd/sc9863a.dtsi
+4 -4
View File
@@ -551,14 +551,14 @@
#size-cells = <2>;
ranges;
sdio0: sdio@20300000 {
sdio0: mmc@20300000 {
compatible = "sprd,sdhci-r11";
reg = <0 0x20300000 0 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sdio", "enable";
clocks = <&aon_clk CLK_SDIO0_2X>,
<&apahb_gate CLK_SDIO0_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&aon_clk CLK_SDIO0_2X>;
assigned-clock-parents = <&rpll CLK_RPLL_390M>;
@@ -567,14 +567,14 @@
no-mmc;
};
sdio3: sdio@20600000 {
sdio3: mmc@20600000 {
compatible = "sprd,sdhci-r11";
reg = <0 0x20600000 0 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sdio", "enable";
clocks = <&aon_clk CLK_EMMC_2X>,
<&apahb_gate CLK_EMMC_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&aon_clk CLK_EMMC_2X>;
assigned-clock-parents = <&rpll CLK_RPLL_390M>;
arch/arm64/boot/dts/sprd/sharkl64.dtsi
+1 -2
View File
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
* Spreadtrum Sharkl64 platform DTS file
*
* Copyright (C) 2014, Spreadtrum Communications Inc.
*
* This file is licensed under a dual GPLv2 or X11 license.
*/
/ {
arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
+1 -2
View File
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Spreadtrum SP9860g board
*
* Copyright (C) 2017, Spreadtrum Communications Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
arch/arm64/boot/dts/sprd/ums512.dtsi
+2 -2
View File
@@ -849,9 +849,9 @@
compatible = "sprd,sdhci-r11";
reg = <0x1100000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sdio", "enable";
clocks = <&ap_clk CLK_SDIO0_2X>,
<&apapb_gate CLK_SDIO0_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
assigned-clock-parents = <&pll1 CLK_RPLL>;
status = "disabled";
@@ -861,9 +861,9 @@
compatible = "sprd,sdhci-r11";
reg = <0x1400000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sdio", "enable";
clocks = <&ap_clk CLK_EMMC_2X>,
<&apapb_gate CLK_EMMC_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&ap_clk CLK_EMMC_2X>;
assigned-clock-parents = <&pll1 CLK_RPLL>;
status = "disabled";
arch/arm64/boot/dts/sprd/whale2.dtsi
+23 -20
View File
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Spreadtrum Whale2 platform peripherals
*
* Copyright (C) 2016, Spreadtrum Communications Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/clock/sprd,sc9860-clk.h>
@@ -75,9 +74,10 @@
"sprd,sc9836-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "enable", "uart", "source";
clocks = <&apapb_gate CLK_UART0_EB>,
<&ap_clk CLK_UART0>, <&ext_26m>;
<&ap_clk CLK_UART0>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
@@ -86,9 +86,10 @@
"sprd,sc9836-uart";
reg = <0x100000 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "enable", "uart", "source";
clocks = <&apapb_gate CLK_UART1_EB>,
<&ap_clk CLK_UART1>, <&ext_26m>;
<&ap_clk CLK_UART1>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
@@ -97,9 +98,10 @@
"sprd,sc9836-uart";
reg = <0x200000 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "enable", "uart", "source";
clocks = <&apapb_gate CLK_UART2_EB>,
<&ap_clk CLK_UART2>, <&ext_26m>;
<&ap_clk CLK_UART2>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
@@ -108,9 +110,10 @@
"sprd,sc9836-uart";
reg = <0x300000 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "enable", "uart", "source";
clocks = <&apapb_gate CLK_UART3_EB>,
<&ap_clk CLK_UART3>, <&ext_26m>;
<&ap_clk CLK_UART3>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
};
@@ -129,19 +132,19 @@
/* For backwards compatibility: */
#dma-channels = <32>;
dma-channels = <32>;
clock-names = "enable";
clocks = <&apahb_gate CLK_DMA_EB>;
clock-names = "enable";
};
sdio3: sdio@50430000 {
sdio3: mmc@50430000 {
compatible = "sprd,sdhci-r11";
reg = <0 0x50430000 0 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sdio", "enable", "2x_enable";
clocks = <&aon_prediv CLK_EMMC_2X>,
<&apahb_gate CLK_EMMC_EB>,
<&aon_gate CLK_EMMC_2X_EN>;
<&apahb_gate CLK_EMMC_EB>,
<&aon_gate CLK_EMMC_2X_EN>;
clock-names = "sdio", "enable", "2x_enable";
assigned-clocks = <&aon_prediv CLK_EMMC_2X>;
assigned-clock-parents = <&clk_l0_409m6>;
@@ -194,8 +197,8 @@
compatible = "sprd,hwspinlock-r3p0";
reg = <0 0x40500000 0 0x1000>;
#hwlock-cells = <1>;
clock-names = "enable";
clocks = <&aon_gate CLK_SPLK_EB>;
clock-names = "enable";
};
eic_debounce: gpio@40210000 {
@@ -258,9 +261,9 @@
reg = <0 0x40310000 0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <12>;
clock-names = "enable", "rtc_enable";
clocks = <&aon_gate CLK_APCPU_WDG_EB>,
<&aon_gate CLK_AP_WDG_RTC_EB>;
<&aon_gate CLK_AP_WDG_RTC_EB>;
clock-names = "enable", "rtc_enable";
};
};
@@ -277,9 +280,9 @@
/* For backwards compatibility: */
#dma-channels = <32>;
dma-channels = <32>;
clock-names = "enable", "ashb_eb";
clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>,
<&agcp_gate CLK_AGCP_AP_ASHB_EB>;
<&agcp_gate CLK_AGCP_AP_ASHB_EB>;
clock-names = "enable", "ashb_eb";
};
};
};