soc: tegra: Add support for DFLL Vmin CVB

Added Vmin coefficients to CPU DFLL CVB table, and updated Vmin
calculations during OPP table build accordingly. Changed build function
signature to return final Vmin.

Bug 1906940

Change-Id: I6e19266f865e9a3dda21c9e0f7178feece055ddf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565468
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>

drivers/clk/tegra/clk-tegra124-dfll-fcpu.c

@@ -680,6 +680,7 @@ static struct cvb_table tegra210b01_cpu_cvb_tables[] = {
 		.process_id = -1,
 		.max_millivolts = 1120,
 		CPUB01_CVB_TABLE,
+		.vmin_coefficients = { 620000, 0, 0 },
 		.cpu_dfll_data = {
 			.tune0_low = 0x0000ffcf,
 			.tune1_low = 0x012207ff,
@@ -693,6 +694,7 @@ static struct cvb_table tegra210b01_cpu_cvb_tables[] = {
 		.process_id = 1,
 		.max_millivolts = 1120,
 		CPUB01_CVB_TABLE_SLT_B1,
+		.vmin_coefficients = { 600000, 0, 0 },
 		.cpu_dfll_data = {
 			.tune0_low = 0x0000ffa0,
 			.tune0_high = 0x0000ffff,
@@ -706,6 +708,7 @@ static struct cvb_table tegra210b01_cpu_cvb_tables[] = {
 		.process_id = 0,
 		.max_millivolts = 1120,
 		CPUB01_CVB_TABLE_SLT_B0,
+		.vmin_coefficients = { 600000, 0, 0 },
 		.cpu_dfll_data = {
 			.tune0_low = 0x0000ff90,
 			.tune0_high = 0x0000ffff,
@@ -719,6 +722,7 @@ static struct cvb_table tegra210b01_cpu_cvb_tables[] = {
 		.process_id = -1,
 		.max_millivolts = 1120,
 		CPUB01_CVB_TABLE,
+		.vmin_coefficients = { 620000, 0, 0 },
 		.cpu_dfll_data = {
 			.tune0_low = 0x0000ffcf,
 			.tune1_low = 0x012207ff,
@@ -850,7 +854,8 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
 	soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables,
 					   fcpu_data->cpu_cvb_tables_size,
 					   &align, process_id, speedo_id,
-					   speedo_value, soc->max_freq);
+					   speedo_value, soc->max_freq,
+					   &soc->min_millivolts);
 	soc->alignment = align;
 
 	if (IS_ERR(soc->cvb)) {

drivers/clk/tegra/cvb.c

@@ -54,13 +54,18 @@ static int round_voltage(int mv, const struct rail_alignment *align, int up)
 
 static int build_opp_table(struct device *dev, const struct cvb_table *table,
 			   struct rail_alignment *align,
-			   int speedo_value, unsigned long max_freq)
+			   int speedo_value, unsigned long max_freq, int *vmin)
 {
 	int i, ret, dfll_mv, min_mv, max_mv;
 
 	min_mv = round_voltage(table->min_millivolts, align, UP);
 	max_mv = round_voltage(table->max_millivolts, align, DOWN);
 
+	dfll_mv = get_cvb_voltage(
+		speedo_value, table->speedo_scale, &table->vmin_coefficients);
+	dfll_mv = round_cvb_voltage(dfll_mv, table->voltage_scale, align);
+	min_mv = max(min_mv, dfll_mv);
+
 	for (i = 0; i < MAX_DVFS_FREQS; i++) {
 		const struct cvb_table_freq_entry *entry = &table->entries[i];
 
@@ -78,6 +83,9 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table,
 			return ret;
 	}
 
+	if (vmin)
+		*vmin = min_mv;
+
 	return 0;
 }
 
@@ -90,7 +98,8 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table,
  * @process_id: process id of the HW module
  * @speedo_id: speedo id of the HW module
  * @speedo_value: speedo value of the HW module
- * @max_freq: highest safe clock rate
+ * @max_rate: highest safe clock rate
+ * @vmin: final minimum voltage returned to the caller
  *
  * On Tegra, a CVB table encodes the relationship between operating voltage
  * and safe maximal frequency for a given module (e.g. GPU or CPU). This
@@ -103,7 +112,7 @@ const struct cvb_table *
 tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables,
 			size_t count, struct rail_alignment *align,
 			int process_id, int speedo_id, int speedo_value,
-			unsigned long max_freq)
+			unsigned long max_freq, int *vmin)
 {
 	size_t i;
 	int ret;
@@ -118,7 +127,7 @@ tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables,
 			continue;
 
 		ret = build_opp_table(dev, table, align, speedo_value,
-				      max_freq);
+				      max_freq, vmin);
 		return ret ? ERR_PTR(ret) : table;
 	}
 

drivers/clk/tegra/cvb.h

@@ -48,13 +48,14 @@ struct cvb_table {
 	int voltage_scale;
 	struct cvb_table_freq_entry entries[MAX_DVFS_FREQS];
 	struct cvb_cpu_dfll_data cpu_dfll_data;
+	struct cvb_coefficients vmin_coefficients;
 };
 
 const struct cvb_table *
 tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *cvb_tables,
 			size_t count, struct rail_alignment *align,
 			int process_id, int speedo_id, int speedo_value,
-			unsigned long max_freq);
+			unsigned long max_freq, int *vmin);
 void tegra_cvb_remove_opp_table(struct device *dev,
 				const struct cvb_table *table,
 				unsigned long max_freq);