Merge tag 'mmc-v6.7-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC fixes from Ulf Hansson: "MMC core: - Fix releasing the host by canceling the delayed work - Fix pause retune on all RPMB partitions MMC host: - meson-mx-sdhc: Fix HW hang during card initialization - sdhci-sprd: Fix eMMC init failure after HW reset" * tag 'mmc-v6.7-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci-sprd: Fix eMMC init failure after hw reset mmc: core: Cancel delayed work before releasing host mmc: rpmb: fixes pause retune on all RPMB partitions. mmc: meson-mx-sdhc: Fix initialization frozen issue
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@@ -851,9 +851,10 @@ static const struct block_device_operations mmc_bdops = {
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static int mmc_blk_part_switch_pre(struct mmc_card *card,
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unsigned int part_type)
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{
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const unsigned int mask = EXT_CSD_PART_CONFIG_ACC_RPMB;
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int ret = 0;
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if (part_type == EXT_CSD_PART_CONFIG_ACC_RPMB) {
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if ((part_type & mask) == mask) {
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if (card->ext_csd.cmdq_en) {
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ret = mmc_cmdq_disable(card);
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if (ret)
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@@ -868,9 +869,10 @@ static int mmc_blk_part_switch_pre(struct mmc_card *card,
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static int mmc_blk_part_switch_post(struct mmc_card *card,
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unsigned int part_type)
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{
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const unsigned int mask = EXT_CSD_PART_CONFIG_ACC_RPMB;
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int ret = 0;
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if (part_type == EXT_CSD_PART_CONFIG_ACC_RPMB) {
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if ((part_type & mask) == mask) {
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mmc_retune_unpause(card->host);
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if (card->reenable_cmdq && !card->ext_csd.cmdq_en)
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ret = mmc_cmdq_enable(card);
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@@ -3145,4 +3147,3 @@ module_exit(mmc_blk_exit);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Multimedia Card (MMC) block device driver");
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@@ -692,6 +692,7 @@ EXPORT_SYMBOL(mmc_remove_host);
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*/
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void mmc_free_host(struct mmc_host *host)
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{
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cancel_delayed_work_sync(&host->detect);
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mmc_pwrseq_free(host);
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put_device(&host->class_dev);
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}
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@@ -269,7 +269,7 @@ static int meson_mx_sdhc_enable_clks(struct mmc_host *mmc)
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static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct meson_mx_sdhc_host *host = mmc_priv(mmc);
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u32 rx_clk_phase;
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u32 val, rx_clk_phase;
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int ret;
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meson_mx_sdhc_disable_clks(mmc);
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@@ -290,27 +290,11 @@ static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
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mmc->actual_clock = clk_get_rate(host->sd_clk);
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/*
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* according to Amlogic the following latching points are
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* selected with empirical values, there is no (known) formula
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* to calculate these.
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* Phase 90 should work in most cases. For data transmission,
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* meson_mx_sdhc_execute_tuning() will find a accurate value
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*/
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if (mmc->actual_clock > 100000000) {
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rx_clk_phase = 1;
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} else if (mmc->actual_clock > 45000000) {
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
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rx_clk_phase = 15;
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else
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rx_clk_phase = 11;
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} else if (mmc->actual_clock >= 25000000) {
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rx_clk_phase = 15;
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} else if (mmc->actual_clock > 5000000) {
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rx_clk_phase = 23;
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} else if (mmc->actual_clock > 1000000) {
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rx_clk_phase = 55;
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} else {
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rx_clk_phase = 1061;
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}
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regmap_read(host->regmap, MESON_SDHC_CLKC, &val);
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rx_clk_phase = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val) / 4;
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regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
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MESON_SDHC_CLK2_RX_CLK_PHASE,
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FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
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@@ -239,15 +239,19 @@ static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
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div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
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sdhci_enable_clk(host, div);
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val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
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mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
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/* Enable CLK_AUTO when the clock is greater than 400K. */
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if (clk > 400000) {
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val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
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mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
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SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
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if (mask != (val & mask)) {
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val |= mask;
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sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
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}
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} else {
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if (val & mask) {
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val &= ~mask;
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sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
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}
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}
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}
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