Merge tag 'tegra-for-5.19-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
soc/tegra: Changes for v5.19-rc1 This set of changes adds nvmem cell lookup entries for Tegra194 that are used to read calibration data from the SoC fuses, and updates the reset sources for Tegra234. Other than that, included is a minor build fix for a missing dependency that can be encountered very rarely in random config builds. Lastly some kerneldoc comments are added to avoid build warnings. * tag 'tegra-for-5.19-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Document core domain fields soc/tegra: pmc: Select REGMAP soc/tegra: pmc: Update Tegra234 reset sources soc/tegra: fuse: Add nvmem cell lookup entries for Tegra194 Link: https://lore.kernel.org/r/20220506143005.3916655-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@@ -146,6 +146,7 @@ config SOC_TEGRA_PMC
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select GENERIC_PINCONF
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select PM_OPP
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select PM_GENERIC_DOMAINS
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select REGMAP
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config SOC_TEGRA_POWERGATE_BPMP
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def_bool y
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/clk.h>
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@@ -162,7 +162,7 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "gcplex-config-fuse",
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.name = "gpu-gcplex-config-fuse",
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.offset = 0x1c8,
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.bytes = 4,
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.bit_offset = 0,
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@@ -186,13 +186,13 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "pdi0",
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.name = "gpu-pdi0",
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.offset = 0x300,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "pdi1",
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.name = "gpu-pdi1",
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.offset = 0x304,
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.bytes = 4,
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.bit_offset = 0,
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/device.h>
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@@ -344,6 +344,21 @@ static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = {
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.cell_name = "xusb-pad-calibration-ext",
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.dev_id = "3520000.padctl",
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.con_id = "calibration-ext",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "gpu-gcplex-config-fuse",
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.dev_id = "17000000.gpu",
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.con_id = "gcplex-config-fuse",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "gpu-pdi0",
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.dev_id = "17000000.gpu",
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.con_id = "pdi0",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "gpu-pdi1",
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.dev_id = "17000000.gpu",
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.con_id = "pdi1",
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},
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};
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+27
-8
@@ -394,6 +394,8 @@ struct tegra_pmc_soc {
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* @domain: IRQ domain provided by the PMC
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* @irq: chip implementation for the IRQ domain
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* @clk_nb: pclk clock changes handler
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* @core_domain_state_synced: flag marking the core domain's state as synced
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* @core_domain_registered: flag marking the core domain as registered
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*/
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struct tegra_pmc {
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struct device *dev;
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@@ -3766,7 +3768,7 @@ static const struct tegra_pmc_regs tegra234_pmc_regs = {
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};
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static const char * const tegra234_reset_sources[] = {
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"SYS_RESET_N",
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"SYS_RESET_N", /* 0x0 */
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"AOWDT",
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"BCCPLEXWDT",
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"BPMPWDT",
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@@ -3774,19 +3776,36 @@ static const char * const tegra234_reset_sources[] = {
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"SPEWDT",
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"APEWDT",
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"LCCPLEXWDT",
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"SENSOR",
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"AOTAG",
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"VFSENSOR",
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"SENSOR", /* 0x8 */
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NULL,
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NULL,
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"MAINSWRST",
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"SC7",
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"HSM",
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"CSITE",
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NULL,
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"RCEWDT",
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"PVA0WDT",
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"PVA1WDT",
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"L1A_ASYNC",
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NULL, /* 0x10 */
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NULL,
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NULL,
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"BPMPBOOT",
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"FUSECRC",
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"DCEWDT",
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"PSCWDT",
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"PSC",
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"CSITE_SW", /* 0x18 */
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"POD",
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"SCPM",
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"VREFRO_POWERBAD",
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"VMON",
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"FMON",
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"FSI_R5WDT",
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"FSI_THERM",
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"FSI_R52C0WDT", /* 0x20 */
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"FSI_R52C1WDT",
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"FSI_R52C2WDT",
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"FSI_R52C3WDT",
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"FSI_FMON",
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"FSI_VMON", /* 0x25 */
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};
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static const struct tegra_wake_event tegra234_wake_events[] = {
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