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arm64: dts: qcom: sm8450: Add OPP table support to PCIe

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PCIe host controller driver needs to choose the appropriate performance
state of RPMh power domain and interconnect bandwidth based on the PCIe
data rate.

Hence, add the OPP table support to specify RPMh performance states and
interconnect peak bandwidth.

It should be noted that the different link configurations may share the
same aggregate bandwidth, e.g., a 2.5 GT/s x2 link and a 5.0 GT/s x1
link have the same bandwidth and share the same OPP entry.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Link: https://lore.kernel.org/r/20240518-opp_support-v13-4-78c73edf50de@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krishna chaitanya chundru
2024-05-18 19:01:45 +05:30
committed by Bjorn Andersson
parent 42870599f9
commit 628388982c
1 changed files with 75 additions and 0 deletions
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arch/arm64/boot/dts/qcom/sm8450.dtsi
+75
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@@ -1851,8 +1851,35 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
operating-points-v2 = <&pcie0_opp_table>;
status = "disabled";
pcie0_opp_table: opp-table {
compatible = "operating-points-v2";
/* GEN 1 x1 */
opp-2500000 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
};
/* GEN 2 x1 */
opp-5000000 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
};
/* GEN 3 x1 */
opp-8000000 {
opp-hz = /bits/ 64 <8000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <984500 1>;
};
};
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -1984,8 +2011,56 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
operating-points-v2 = <&pcie1_opp_table>;
status = "disabled";
pcie1_opp_table: opp-table {
compatible = "operating-points-v2";
/* GEN 1 x1 */
opp-2500000 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
};
/* GEN 1 x2 and GEN 2 x1 */
opp-5000000 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
};
/* GEN 2 x2 */
opp-10000000 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
};
/* GEN 3 x1 */
opp-8000000 {
opp-hz = /bits/ 64 <8000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <984500 1>;
};
/* GEN 3 x2 and GEN 4 x1 */
opp-16000000 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <1969000 1>;
};
/* GEN 4 x2 */
opp-32000000 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <3938000 1>;
};
};
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;