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tegra: clk: correct divider algo

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Negative divider_ux1 values previously were resolved by extra checks and
caused undefined behavior with div1_5_not_allowed
This commit is contained in:
Thomas Makin
2025-12-27 03:08:14 +00:00
parent ea57749891
commit 60832e95c5
1 changed files with 2 additions and 5 deletions
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7
drivers/clk/tegra/clk-utils.c
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@@ -12,11 +12,11 @@
int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
u8 frac_width, u8 flags) u8 frac_width, u8 flags)
{ {
u64 divider_ux1 = parent_rate; s64 divider_ux1 = parent_rate;
int mul; int mul;
if (!rate) if (!rate)
return 0; return div_mask(width);
mul = 1 << frac_width; mul = 1 << frac_width;
@@ -31,9 +31,6 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
if (flags & TEGRA_DIVIDER_INT) if (flags & TEGRA_DIVIDER_INT)
divider_ux1 *= mul; divider_ux1 *= mul;
if (!div1_5_not_allowed && divider_ux1 < mul)
return 0;
divider_ux1 -= mul; divider_ux1 -= mul;
if (divider_ux1 > div_mask(width)) if (divider_ux1 > div_mask(width))