From 60832e95c5a2c45966e7a1e814ba23fb96c46d61 Mon Sep 17 00:00:00 2001 From: Thomas Makin Date: Sat, 27 Dec 2025 03:08:14 +0000 Subject: [PATCH] tegra: clk: correct divider algo Negative divider_ux1 values previously were resolved by extra checks and caused undefined behavior with div1_5_not_allowed --- drivers/clk/tegra/clk-utils.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/clk/tegra/clk-utils.c b/drivers/clk/tegra/clk-utils.c index 4283f314c513..6518ebc1295b 100644 --- a/drivers/clk/tegra/clk-utils.c +++ b/drivers/clk/tegra/clk-utils.c @@ -12,11 +12,11 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, u8 frac_width, u8 flags) { - u64 divider_ux1 = parent_rate; + s64 divider_ux1 = parent_rate; int mul; if (!rate) - return 0; + return div_mask(width); mul = 1 << frac_width; @@ -31,9 +31,6 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, if (flags & TEGRA_DIVIDER_INT) divider_ux1 *= mul; - if (!div1_5_not_allowed && divider_ux1 < mul) - return 0; - divider_ux1 -= mul; if (divider_ux1 > div_mask(width))