Merge tag 'renesas-dts-for-v6.12-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.12 (take two) - Add support for Ethernet TSN and PCIe on the R-Car V4H SoC and the White-Hawk (Single) development board, - Add display support for the RZ/G2UL SoC and the RZ/G2UL SMARC EVk board, - Add I2C support for the RZ/G3S SoC and the RZ/G3S SMARC EVK board, - Add support for HDMI audio on the RZ/G2L and RZ/G2LC SMARC EVK boards, - Add initial support for the RZ/V2H(P) (R9A09G057) SoC and the RZ/V2H EVK board, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.12-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits) arm64: dts: renesas: r8a779h0: Add family fallback for CSISP IP arm64: dts: renesas: r8a779a0: Add family fallback for CSISP IP arm64: dts: renesas: r8a779g0: Add family fallback for CSISP IP arm64: dts: renesas: r8a779h0: Add family fallback for VIN IP arm64: dts: renesas: r8a779a0: Add family fallback for VIN IP arm64: dts: renesas: r8a779g0: Add family fallback for VIN IP arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable watchdog arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable OSTM, I2C, and SDHI arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodes arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodes arm64: dts: renesas: r9a09g057: Add OSTM0-OSTM7 nodes arm64: dts: renesas: Add initial DTS for RZ/V2H EVK board arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC dt-bindings: soc: renesas: Document RZ/V2H EVK board dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG arm64: dts: renesas: r9a07g043u11-smarc: Enable DU arm64: dts: renesas: rzg2lc-smarc: Enable HDMI audio arm64: dts: renesas: rzg2l-smarc: Enable HDMI audio arm64: dts: renesas: r9a07g043u: Add DU node ... Link: https://lore.kernel.org/r/cover.1725374275.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-05 10:13:40 +00:00
parent 06b6879f0a cc41aa93bb
commit 5d9e36498b
25 changed files with 1617 additions and 83 deletions
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
+
+maintainers:
+  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+description:
+  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
+  and control of clock signals for the IP modules, generation and control of resets,
+  and control over booting, low power consumption and power supply domains.
+
+properties:
+  compatible:
+    const: renesas,r9a09g057-cpg
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: AUDIO_EXTAL clock input
+      - description: RTXIN clock input
+      - description: QEXTAL clock input
+
+  clock-names:
+    items:
+      - const: audio_extal
+      - const: rtxin
+      - const: qextal
+
+  '#clock-cells':
+    description: |
+      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+        and a core clock reference, as defined in
+        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
+      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+        a module number.  The module number is calculated as the CLKON register
+        offset index multiplied by 16, plus the actual bit in the register
+        used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
+        calculation is (1 * 16 + 3) = 0x13.
+    const: 2
+
+  '#power-domain-cells':
+    const: 0
+
+  '#reset-cells':
+    description:
+      The single reset specifier cell must be the reset number. The reset number
+      is calculated as the reset register offset index multiplied by 16, plus the
+      actual bit in the register used to reset the specific IP block. For example,
+      for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#power-domain-cells'
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@10420000 {
+        compatible = "renesas,r9a09g057-cpg";
+        reg = <0x10420000 0x10000>;
+        clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
+        clock-names = "audio_extal", "rtxin", "qextal";
+        #clock-cells = <2>;
+        #power-domain-cells = <0>;
+        #reset-cells = <1>;
+    };