drm/bridge: ps8640: Add double reset T4 and T5 to power-on sequence
The double reset power-on sequence is a workaround for the hardware flaw in some chip that SPI Clock output glitch and cause internal MPU unable to read firmware correctly. The sequence is suggested in ps8640 application note. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Rock Chiu <rock.chiu@paradetech.corp-partner.google.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220815093905.134164-1-hsinyi@chromium.org
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Douglas Anderson
parent
da09daf881
commit
55453c0914
@@ -375,6 +375,11 @@ static int __maybe_unused ps8640_resume(struct device *dev)
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gpiod_set_value(ps_bridge->gpio_reset, 1);
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usleep_range(2000, 2500);
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gpiod_set_value(ps_bridge->gpio_reset, 0);
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/* Double reset for T4 and T5 */
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msleep(50);
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gpiod_set_value(ps_bridge->gpio_reset, 1);
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msleep(50);
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gpiod_set_value(ps_bridge->gpio_reset, 0);
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/*
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* Mystery 200 ms delay for the "MCU to be ready". It's unclear if
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