Merge tag 'qcom-arm64-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v6.12 This introduces support for the following devices: - Lenovo Thinkpad T14s Gen 6 - Microsoft Surface Laptop 7 laptop - Lenovo A6000 - Lenovo A6010 - Samsung Galaxy J3, - Lenovo Vibe K5 (multiple variants) - LG G4 IPQ5332 global clock controller is marked as an interconnect-provider, and the USB interrupt triggers are corrected. Touchscreen description is added to the Samsung Galaxy Core Prime and Max, and touch keys are added to the Samsung Galaxy Grand Prime and Galaxy Tab A. Camera flash is added to BQ Aquaris M5 and X5. The SD-card slot is described for the QCM6490 IDP. For SA8775P CPU and LLCC bwmon is added, audio, compute and general purpose DSP remoteprocs are added, with FastRPC on audio and compute DSP. CPUidle states, capacity and DPC properties are added. On SC8180X definitions for the multiport USB controller is introduced, and enabled on the Lenovo Flex 5G to bring the camera to life. Power key definitions are added as well. The RGB camera sensor on the Lenovo ThinkPad X13s is described. PCIe pinconf properties are cleaned up on this and the CRD. The four USB Type-A ports found on the SA8295P ADP are enabled. The modem subsystem remoteproc is introduced on the SDX75 and enabled on the IDP device. Camera, display and GPU clock controllers are added for the SM4450 platform. On the F(x)tec Pro1X device, display, GPU, WiFi, RGB LED, SD-card, remoteprocs, USB3 SuperSpeed, touchscreen, IO-expander, hall switch, caps lock LED and camera button are introduced. The camera clock controller is added to SM8150, and the GPU-only "amd,imageon" compatible is dropped from the MTP device. Refgen regulator for the DSI nodes of SM8350 is described, and the display subsystem interconnect paths are corrected. The camera control interface controllers are described on both SM8550 and SM8650. The bluetooth node on on SM8550 QRD, SM8650 QRD and SM8650 HDK are transitioned to the power sequence description. WiFi is added to the SM8550 hardware development kit (HDK). On the X1 Elite platform, one more UART, a DisplayPort PHY, the USB multiport controller, a PCIe controller and PHY are added. Orientation switching is wired up for the USB+DP PHYs. RPMh statistics node is added. For the X1 Elite CRD the LID switch and the SDX65 modems are introduced. * tag 'qcom-arm64-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (120 commits) arm64: dts: qcom: x1e80100: Fix PHY for DP2 arm64: dts: qcom: qcm6490-idp: Add SD Card node arm64: dts: qcom: x1e80100: Add orientation-switch to all USB+DP QMP PHYs arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6 dt-bindings: arm: qcom: Add Lenovo ThinkPad T14s Gen 6 Revert "arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flash" arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devices arm64: dts: qcom: x1e80100: Add UART2 arm64: dts: qcom: x1e80100-pmics: Add PMC8380C PWM dt-bindings: arm: qcom: Add Surface Laptop 7 devices arm64: dts: qcom: sm8150-mtp: drop incorrect amd,imageon arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodes arm64: dts: qcom: x1e80100: Add USB Multiport controller arm64: dts: qcom: sa8775p: fix the fastrpc label arm64: dts: qcom: ipq5332: Add icc provider ability to gcc dt-bindings: interconnect: Add Qualcomm IPQ5332 support arm64: dts: qcom: sm8250: move lpass codec macros to use clks directly arm64: dts: qcom: msm8998: Add disabled support for LPASS iommu for Q6 dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions arm64: dts: qcom: msm8976: Add restart node ... Link: https://lore.kernel.org/r/20240904215752.24465-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -155,6 +155,11 @@ properties:
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- const: qcom,msm8926
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- const: qcom,msm8226
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- items:
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- enum:
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- wingtech,wt82918hd
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- const: qcom,msm8929
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- items:
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- enum:
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- huawei,kiwi
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@@ -162,6 +167,8 @@ properties:
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- samsung,a7
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- sony,kanuti-tulip
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- square,apq8039-t2
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- wingtech,wt82918
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- wingtech,wt82918hdhw39
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- const: qcom,msm8939
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- items:
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@@ -228,12 +235,15 @@ properties:
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- samsung,grandprimelte
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- samsung,gt510
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- samsung,gt58
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- samsung,j3ltetw
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- samsung,j5
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- samsung,j5x
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- samsung,rossa
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- samsung,serranove
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- thwc,uf896
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- thwc,ufi001c
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- wingtech,wt86518
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- wingtech,wt86528
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- wingtech,wt88047
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- yiming,uz801-v3
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- const: qcom,msm8916
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@@ -250,6 +260,7 @@ properties:
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- items:
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- enum:
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- lg,bullhead
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- lg,h815
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- microsoft,talkman
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- xiaomi,libra
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- const: qcom,msm8992
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@@ -1038,10 +1049,18 @@ properties:
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- qcom,sm8650-qrd
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- const: qcom,sm8650
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- items:
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- enum:
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- lenovo,thinkpad-t14s
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- const: qcom,x1e78100
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- const: qcom,x1e80100
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- items:
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- enum:
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- asus,vivobook-s15
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- lenovo,yoga-slim7x
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- microsoft,romulus13
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- microsoft,romulus15
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- qcom,x1e80100-crd
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- qcom,x1e80100-qcp
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- const: qcom,x1e80100
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@@ -31,6 +31,8 @@ properties:
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- description: USB PCIE wrapper pipe clock source
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'#power-domain-cells': false
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'#interconnect-cells':
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const: 1
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required:
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- compatible
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@@ -0,0 +1,63 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Camera Clock & Reset Controller on SM4450
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maintainers:
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- Ajit Pandey <quic_ajipan@quicinc.com>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm camera clock control module provides the clocks, resets and power
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domains on SM4450
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See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
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properties:
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compatible:
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const: qcom,sm4450-camcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Camera AHB clock source from GCC
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm4450-gcc.h>
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clock-controller@ade0000 {
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compatible = "qcom,sm4450-camcc";
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reg = <0x0ade0000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_CAMERA_AHB_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@@ -0,0 +1,71 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on SM4450
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maintainers:
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- Ajit Pandey <quic_ajipan@quicinc.com>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on SM4450
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See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
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properties:
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compatible:
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const: qcom,sm4450-dispcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Display AHB clock source from GCC
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- description: sleep clock source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm4450-gcc.h>
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clock-controller@af00000 {
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compatible = "qcom,sm4450-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
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<&dsi0_phy_pll_out_byteclk>,
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<&dsi0_phy_pll_out_dsiclk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@@ -0,0 +1,77 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Camera Clock & Reset Controller on SM8150
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maintainers:
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- Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
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description: |
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Qualcomm camera clock control module provides the clocks, resets and
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power domains on SM8150.
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See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
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properties:
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compatible:
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const: qcom,sm8150-camcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Camera AHB clock from GCC
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power-domains:
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maxItems: 1
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description:
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A phandle and PM domain specifier for the MMCX power domain.
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required-opps:
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maxItems: 1
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description:
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A phandle to an OPP node describing required MMCX performance point.
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- power-domains
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- required-opps
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8150.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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clock-controller@ad00000 {
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compatible = "qcom,sm8150-camcc";
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reg = <0x0ad00000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_CAMERA_AHB_CLK>;
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power-domains = <&rpmhpd SM8150_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@@ -14,6 +14,7 @@ description: |
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domains on Qualcomm SoCs.
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See also::
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include/dt-bindings/clock/qcom,sm4450-gpucc.h
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include/dt-bindings/clock/qcom,sm8450-gpucc.h
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include/dt-bindings/clock/qcom,sm8550-gpucc.h
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include/dt-bindings/reset/qcom,sm8450-gpucc.h
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@@ -23,6 +24,7 @@ description: |
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properties:
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compatible:
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enum:
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- qcom,sm4450-gpucc
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- qcom,sm8450-gpucc
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- qcom,sm8550-gpucc
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- qcom,sm8650-gpucc
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@@ -48,18 +48,24 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandmax.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandprimelte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt510.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt58.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j3ltetw.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5x.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-rossa.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt86518.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt86528.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8929-wingtech-wt82918hd.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8939-huawei-kiwi.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8939-longcheer-l9100.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8939-wingtech-wt82918.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8939-wingtech-wt82918hd.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb
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@@ -69,6 +75,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-kugo.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-suzu.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-h815.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8994-huawei-angler-rev-101.dtb
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@@ -261,7 +268,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
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dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb
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dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb
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dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
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dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb
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dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb
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dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb
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dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb
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@@ -7,6 +7,7 @@
|
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#include <dt-bindings/clock/qcom,apss-ipq.h>
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#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
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#include <dt-bindings/interconnect/qcom,ipq5332.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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|
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/ {
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@@ -208,6 +209,7 @@
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reg = <0x01800000 0x80000>;
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#clock-cells = <1>;
|
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#reset-cells = <1>;
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#interconnect-cells = <1>;
|
||||
clocks = <&xo_board>,
|
||||
<&sleep_clk>,
|
||||
<0>,
|
||||
@@ -320,18 +322,16 @@
|
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reg = <0x08af8800 0x400>;
|
||||
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>;
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event",
|
||||
"dp_hs_phy_irq",
|
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"dm_hs_phy_irq";
|
||||
|
||||
clocks = <&gcc GCC_USB0_MASTER_CLK>,
|
||||
<&gcc GCC_SNOC_USB_CLK>,
|
||||
<&gcc GCC_USB0_SLEEP_CLK>,
|
||||
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
|
||||
clock-names = "core",
|
||||
"iface",
|
||||
"sleep",
|
||||
"mock_utmi";
|
||||
|
||||
@@ -342,6 +342,9 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interconnects = <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>,
|
||||
<&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
||||
@@ -168,7 +168,7 @@
|
||||
mboxes = <&apcs_glb 0>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-ipq6018";
|
||||
compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
regulators {
|
||||
|
||||
@@ -181,7 +181,7 @@
|
||||
mboxes = <&apcs_glb 0>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-ipq9574";
|
||||
compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -125,6 +125,26 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
flash-led-controller@53 {
|
||||
compatible = "silergy,sy7802";
|
||||
reg = <0x53>;
|
||||
|
||||
enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&camera_rear_flash_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_FLASH;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
led-sources = <0>, <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c3 {
|
||||
@@ -278,6 +298,13 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
camera_rear_flash_default: camera-rear-flash-default-state {
|
||||
pins = "gpio9", "gpio16", "gpio117";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
gpio_keys_default: gpio-keys-default-state {
|
||||
pins = "gpio107";
|
||||
function = "gpio";
|
||||
|
||||
@@ -262,6 +262,8 @@
|
||||
|
||||
pinctrl-0 = <&tsp_int_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
linux,keycodes = <KEY_APPSELECT KEY_BACK>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -47,12 +47,34 @@
|
||||
constant-charge-voltage-max-microvolt = <4400000>;
|
||||
};
|
||||
|
||||
&blsp_i2c5 {
|
||||
status = "okay";
|
||||
|
||||
touchscreen@50 {
|
||||
compatible = "imagis,ist3038";
|
||||
reg = <0x50>;
|
||||
|
||||
interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
touchscreen-size-x = <720>;
|
||||
touchscreen-size-y = <1280>;
|
||||
|
||||
vdd-supply = <®_vdd_tsp_a>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
|
||||
pinctrl-0 = <&ts_int_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
linux,keycodes = <KEY_APPSELECT KEY_BACK>;
|
||||
};
|
||||
};
|
||||
|
||||
®_motor_vdd {
|
||||
gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
®_touch_key {
|
||||
status = "disabled";
|
||||
status = "disabled"; /* Using Imagis touch key */
|
||||
};
|
||||
|
||||
&sound {
|
||||
|
||||
@@ -75,6 +75,7 @@
|
||||
|
||||
touchscreen-size-x = <768>;
|
||||
touchscreen-size-y = <1024>;
|
||||
linux,keycodes = <KEY_APPSELECT KEY_BACK>;
|
||||
|
||||
vcca-supply = <®_vdd_tsp>;
|
||||
vdd-supply = <&pm8916_l6>;
|
||||
|
||||
@@ -0,0 +1,62 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include "msm8916-samsung-j5-common.dtsi"
|
||||
|
||||
/ {
|
||||
reserved-memory {
|
||||
/delete-node/ tz-apps@85500000;
|
||||
|
||||
/* Additional memory used by Samsung firmware modifications */
|
||||
tz-apps@85800000 {
|
||||
reg = <0x0 0x85800000 0x0 0x800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
reg_vdd_tsp_a: regulator-vdd-tsp-a {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_tsp_a";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
gpio = <&tlmm 16 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&tsp_ldo_en_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&accelerometer {
|
||||
vdd-supply = <&pm8916_l5>;
|
||||
vddio-supply = <&pm8916_l5>;
|
||||
|
||||
mount-matrix = "0", "-1", "0",
|
||||
"1", "0", "0",
|
||||
"0", "0", "-1";
|
||||
};
|
||||
|
||||
&gpio_hall_sensor {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c_muic {
|
||||
/* GPIO pins vary depending on model variant */
|
||||
};
|
||||
|
||||
&i2c_sensors {
|
||||
/* GPIO pins vary depending on model variant */
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
vdd-supply = <®_vdd_tsp_a>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
tsp_ldo_en_default: tsp-ldo-en-default-state {
|
||||
pins = "gpio16";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,31 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8916-samsung-j3-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Samsung Galaxy J3 (2016) (SM-J320YZ)";
|
||||
compatible = "samsung,j3ltetw", "qcom,msm8916";
|
||||
chassis-type = "handset";
|
||||
};
|
||||
|
||||
&i2c_muic {
|
||||
sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
|
||||
scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
|
||||
};
|
||||
|
||||
&i2c_sensors {
|
||||
/* I2C2 */
|
||||
sda-gpios = <&tlmm 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
|
||||
scl-gpios = <&tlmm 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
|
||||
};
|
||||
|
||||
&muic_i2c_default {
|
||||
pins = "gpio0", "gpio1";
|
||||
};
|
||||
|
||||
&sensors_i2c_default {
|
||||
/* I2C2 */
|
||||
pins = "gpio6", "gpio7";
|
||||
};
|
||||
@@ -16,6 +16,26 @@
|
||||
constant-charge-voltage-max-microvolt = <4400000>;
|
||||
};
|
||||
|
||||
&blsp_i2c5 {
|
||||
touchscreen@50 {
|
||||
compatible = "imagis,ist3038";
|
||||
reg = <0x50>;
|
||||
|
||||
interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
touchscreen-size-x = <480>;
|
||||
touchscreen-size-y = <800>;
|
||||
|
||||
vdd-supply = <®_vdd_tsp_a>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
|
||||
pinctrl-0 = <&tsp_int_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
linux,keycodes = <KEY_APPSELECT KEY_BACK>;
|
||||
};
|
||||
};
|
||||
|
||||
&mpss_mem {
|
||||
/* Firmware for rossa needs more space */
|
||||
reg = <0x0 0x86800000 0x0 0x5800000>;
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8916-wingtech-wt865x8.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Lenovo A6000 (Wingtech WT86518)";
|
||||
compatible = "wingtech,wt86518", "qcom,msm8916";
|
||||
chassis-type = "handset";
|
||||
|
||||
speaker_amp: audio-amplifier {
|
||||
compatible = "awinic,aw8738";
|
||||
|
||||
pinctrl-0 = <&spk_ext_pa_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mode-gpios = <&tlmm 119 GPIO_ACTIVE_HIGH>;
|
||||
sound-name-prefix = "Speaker Amp";
|
||||
awinic,mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c2 {
|
||||
accelerometer@e {
|
||||
compatible = "kionix,kxcj91008";
|
||||
reg = <0xe>;
|
||||
|
||||
vdd-supply = <&pm8916_l6>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
|
||||
mount-matrix = "0", "-1", "0",
|
||||
"-1", "0", "0",
|
||||
"0", "0", "1";
|
||||
};
|
||||
};
|
||||
|
||||
&headphones_switch {
|
||||
VCC-supply = <&pm8916_l17>;
|
||||
};
|
||||
|
||||
&pm8916_bms {
|
||||
power-supplies = <&pm8916_charger>;
|
||||
};
|
||||
|
||||
&pm8916_charger {
|
||||
qcom,fast-charge-safe-current = <900000>;
|
||||
qcom,fast-charge-safe-voltage = <4300000>;
|
||||
|
||||
monitored-battery = <&battery>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sound {
|
||||
model = "wt88047";
|
||||
widgets = "Speaker", "Speaker",
|
||||
"Headphone", "Headphones";
|
||||
pin-switches = "Speaker", "Headphones";
|
||||
audio-routing = "Speaker", "Speaker Amp OUT",
|
||||
"Speaker Amp IN", "HPH_R",
|
||||
"Headphones", "Headphones Switch OUTL",
|
||||
"Headphones", "Headphones Switch OUTR",
|
||||
"Headphones Switch INL", "HPH_L",
|
||||
"Headphones Switch INR", "HPH_R",
|
||||
"AMIC1", "MIC BIAS Internal1",
|
||||
"AMIC2", "MIC BIAS Internal2";
|
||||
aux-devs = <&speaker_amp>, <&headphones_switch>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
dr_mode = "peripheral";
|
||||
extcon = <&pm8916_charger>;
|
||||
};
|
||||
|
||||
&usb_hs_phy {
|
||||
extcon = <&pm8916_charger>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
spk_ext_pa_default: spk-ext-pa-default-state {
|
||||
pins = "gpio119";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,158 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8916-wingtech-wt865x8.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Lenovo A6010 (Wingtech WT86528)";
|
||||
compatible = "wingtech,wt86528", "qcom,msm8916";
|
||||
chassis-type = "handset";
|
||||
|
||||
/* left AW8736 */
|
||||
speaker_amp_left: audio-amplifier-left {
|
||||
compatible = "awinic,aw8738";
|
||||
|
||||
pinctrl-0 = <&spk_ext_pa_left_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mode-gpios = <&tlmm 119 GPIO_ACTIVE_HIGH>;
|
||||
sound-name-prefix = "Speaker Amp L";
|
||||
awinic,mode = <3>;
|
||||
};
|
||||
|
||||
/* right AW8736 */
|
||||
speaker_amp_right: audio-amplifier-right {
|
||||
compatible = "awinic,aw8738";
|
||||
|
||||
pinctrl-0 = <&spk_ext_pa_right_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mode-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
|
||||
sound-name-prefix = "Speaker Amp R";
|
||||
awinic,mode = <3>;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pinctrl-0 = <&gpio_leds_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
led-0 {
|
||||
gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
|
||||
label = "red";
|
||||
default-state = "off";
|
||||
retain-state-suspended;
|
||||
};
|
||||
|
||||
led-1 {
|
||||
gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
|
||||
label = "green";
|
||||
default-state = "off";
|
||||
retain-state-suspended;
|
||||
};
|
||||
};
|
||||
|
||||
usb_id: usb-id {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&usb_id_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c2 {
|
||||
magnetometer@c {
|
||||
compatible = "asahi-kasei,ak09911";
|
||||
reg = <0x0c>;
|
||||
|
||||
vdd-supply = <&pm8916_l17>;
|
||||
vid-supply = <&pm8916_l6>;
|
||||
};
|
||||
|
||||
imu@68 {
|
||||
compatible = "invensense,mpu6880";
|
||||
reg = <0x68>;
|
||||
|
||||
interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
vdd-supply = <&pm8916_l17>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
|
||||
pinctrl-0 = <&imu_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mount-matrix = "1", "0", "0",
|
||||
"0", "-1", "0",
|
||||
"0", "0", "1";
|
||||
};
|
||||
};
|
||||
|
||||
&pm8916_codec {
|
||||
qcom,micbias1-ext-cap;
|
||||
};
|
||||
|
||||
&sound {
|
||||
model = "wt86528";
|
||||
widgets = "Speaker", "Speaker",
|
||||
"Headphone", "Headphones";
|
||||
pin-switches = "Speaker", "Headphones";
|
||||
audio-routing = "Speaker", "Speaker Amp L OUT",
|
||||
"Speaker", "Speaker Amp R OUT",
|
||||
"Speaker Amp L IN", "HPH_L",
|
||||
"Speaker Amp R IN", "HPH_R",
|
||||
"Headphones", "Headphones Switch OUTL",
|
||||
"Headphones", "Headphones Switch OUTR",
|
||||
"Headphones Switch INL", "HPH_L",
|
||||
"Headphones Switch INR", "HPH_R",
|
||||
"AMIC1", "MIC BIAS External1",
|
||||
"AMIC2", "MIC BIAS Internal2",
|
||||
"AMIC3", "MIC BIAS External1";
|
||||
aux-devs = <&speaker_amp_left>, <&speaker_amp_right>, <&headphones_switch>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
extcon = <&usb_id>, <&usb_id>;
|
||||
};
|
||||
|
||||
&usb_hs_phy {
|
||||
extcon = <&usb_id>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio_leds_default: gpio-leds-default-state {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
imu_default: imu-default-state {
|
||||
pins = "gpio115";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
spk_ext_pa_left_default: spk-ext-pa-left-default-state {
|
||||
pins = "gpio119";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
spk_ext_pa_right_default: spk-ext-pa-right-default-state {
|
||||
pins = "gpio121";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
usb_id_default: usb-id-default-state {
|
||||
pins = "gpio110";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,215 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include "msm8916-pm8916.dtsi"
|
||||
#include "msm8916-modem-qdsp6.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc0 = &sdhc_1; /* eMMC */
|
||||
mmc1 = &sdhc_2; /* SD card */
|
||||
serial0 = &blsp_uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
|
||||
headphones_switch: audio-switch {
|
||||
compatible = "simple-audio-amplifier";
|
||||
|
||||
pinctrl-0 = <&headphones_switch_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
enable-gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>;
|
||||
sound-name-prefix = "Headphones Switch";
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pm8916_pwm 0 100000>;
|
||||
|
||||
brightness-levels = <0 255>;
|
||||
num-interpolated-steps = <255>;
|
||||
default-brightness-level = <255>;
|
||||
};
|
||||
|
||||
battery: battery {
|
||||
compatible = "simple-battery";
|
||||
voltage-min-design-microvolt = <3400000>;
|
||||
voltage-max-design-microvolt = <4350000>;
|
||||
energy-full-design-microwatt-hours = <8740000>;
|
||||
charge-full-design-microamp-hours = <2300000>;
|
||||
|
||||
ocv-capacity-celsius = <25>;
|
||||
ocv-capacity-table-0 = <4328000 100>, <4266000 95>, <4208000 90>,
|
||||
<4154000 85>, <4102000 80>, <4062000 75>, <3992000 70>,
|
||||
<3960000 65>, <3914000 60>, <3870000 55>, <3840000 50>,
|
||||
<3818000 45>, <3800000 40>, <3784000 35>, <3770000 30>,
|
||||
<3756000 25>, <3736000 20>, <3714000 16>, <3696000 13>,
|
||||
<3690000 11>, <3689000 10>, <3688000 9>, <3686000 8>,
|
||||
<3682000 7>, <3670000 6>, <3639000 5>, <3592000 4>,
|
||||
<3530000 3>, <3448000 2>, <3320000 1>, <3000000 0>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&gpio_keys_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
label = "GPIO Buttons";
|
||||
|
||||
volume-up-button {
|
||||
label = "Volume Up";
|
||||
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c5 {
|
||||
status = "okay";
|
||||
|
||||
touchscreen@38 {
|
||||
compatible = "edt,edt-ft5306";
|
||||
reg = <0x38>;
|
||||
|
||||
interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
vcc-supply = <&pm8916_l17>;
|
||||
iovcc-supply = <&pm8916_l6>;
|
||||
|
||||
reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
|
||||
|
||||
touchscreen-size-x = <720>;
|
||||
touchscreen-size-y = <1280>;
|
||||
|
||||
pinctrl-0 = <&touchscreen_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mpss_mem {
|
||||
reg = <0x0 0x86800000 0x0 0x5500000>;
|
||||
};
|
||||
|
||||
&pm8916_bms {
|
||||
monitored-battery = <&battery>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8916_codec {
|
||||
qcom,micbias-lvl = <2800>;
|
||||
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
|
||||
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
|
||||
qcom,hphl-jack-type-normally-open;
|
||||
};
|
||||
|
||||
&pm8916_pwm {
|
||||
pinctrl-0 = <&pwm_out>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8916_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8916_rpm_regulators {
|
||||
pm8916_l17: l17 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pm8916_vib {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
pinctrl-0 = <&sdc2_default>;
|
||||
pinctrl-1 = <&sdc2_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
non-removable;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&venus {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&venus_mem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcnss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcnss_iris {
|
||||
compatible = "qcom,wcn3620";
|
||||
};
|
||||
|
||||
&wcnss_mem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio_keys_default: gpio-keys-default-state {
|
||||
pins = "gpio107";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
headphones_switch_default: headphones-switch-default-state {
|
||||
pins = "gpio120";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
touchscreen_default: touchscreen-default-state {
|
||||
touchscreen-pins {
|
||||
pins = "gpio13";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
reset-pins {
|
||||
pins = "gpio12";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pm8916_mpps {
|
||||
pwm_out: mpp4-state {
|
||||
pins = "mpp4";
|
||||
function = "digital";
|
||||
power-source = <PM8916_MPP_VPH>;
|
||||
output-low;
|
||||
qcom,dtest = <1>;
|
||||
};
|
||||
};
|
||||
@@ -312,7 +312,7 @@
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-msm8916";
|
||||
compatible = "qcom,rpm-msm8916", "qcom,smd-rpm";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -0,0 +1,162 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* msm8929-pm8916.dtsi describes common properties (e.g. regulator connections)
|
||||
* that apply to most devices that make use of the MSM8929 SoC and PM8916 PMIC.
|
||||
* Many regulators have a fixed purpose in the original reference design and
|
||||
* were rarely re-used for different purposes. Devices that deviate from the
|
||||
* typical reference design should not make use of this include and instead add
|
||||
* the necessary properties in the board-specific device tree.
|
||||
*/
|
||||
|
||||
#include "msm8929.dtsi"
|
||||
#include "pm8916.dtsi"
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-supply = <&pm8916_l2>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
vdda-supply = <&pm8916_l2>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
};
|
||||
|
||||
&mdss_dsi1_phy {
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
};
|
||||
|
||||
&mpss {
|
||||
pll-supply = <&pm8916_l7>;
|
||||
};
|
||||
|
||||
&pm8916_codec {
|
||||
vdd-cdc-io-supply = <&pm8916_l5>;
|
||||
vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>;
|
||||
vdd-micbias-supply = <&pm8916_l13>;
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
pm8916_rpm_regulators: regulators {
|
||||
compatible = "qcom,rpm-pm8916-regulators";
|
||||
vdd_l1_l2_l3-supply = <&pm8916_s3>;
|
||||
vdd_l4_l5_l6-supply = <&pm8916_s4>;
|
||||
vdd_l7-supply = <&pm8916_s4>;
|
||||
|
||||
/* pm8916_s1 is managed by rpmpd (MSM8939_VDDMDCX) */
|
||||
/* pm8916_s2 is managed by rpmpd (MSM8939_VDDCX) */
|
||||
pm8916_s3: s3 {
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on; /* Needed for L2 */
|
||||
};
|
||||
pm8916_s4: s4 {
|
||||
regulator-min-microvolt = <1850000>;
|
||||
regulator-max-microvolt = <2150000>;
|
||||
regulator-always-on; /* Needed for L5/L7 */
|
||||
};
|
||||
|
||||
/*
|
||||
* Some of the regulators are unused or managed by another
|
||||
* processor (e.g. the modem). We should still define nodes for
|
||||
* them to ensure the vote from the application processor can be
|
||||
* dropped in case the regulators are already on during boot.
|
||||
*
|
||||
* The labels for these nodes are omitted on purpose because
|
||||
* boards should configure a proper voltage before using them.
|
||||
*/
|
||||
l1 {};
|
||||
|
||||
pm8916_l2: l2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on; /* Needed for LPDDR RAM */
|
||||
};
|
||||
|
||||
/* pm8916_l3 is managed by rpmpd (MSM8939_VDDMX) */
|
||||
|
||||
l4 {};
|
||||
|
||||
pm8916_l5: l5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on; /* Needed for most digital I/O */
|
||||
};
|
||||
|
||||
pm8916_l6: l6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
pm8916_l7: l7 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on; /* Needed for CPU PLL */
|
||||
};
|
||||
|
||||
pm8916_l8: l8 {
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
pm8916_l9: l9 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
l10 {};
|
||||
|
||||
pm8916_l11: l11 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
regulator-allow-set-load;
|
||||
regulator-system-load = <200000>;
|
||||
};
|
||||
|
||||
pm8916_l12: l12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
|
||||
pm8916_l13: l13 {
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3075000>;
|
||||
};
|
||||
|
||||
l14 {};
|
||||
l15 {};
|
||||
l16 {};
|
||||
l17 {};
|
||||
l18 {};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
vmmc-supply = <&pm8916_l8>;
|
||||
vqmmc-supply = <&pm8916_l5>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
vmmc-supply = <&pm8916_l11>;
|
||||
vqmmc-supply = <&pm8916_l12>;
|
||||
};
|
||||
|
||||
&usb_hs_phy {
|
||||
v1p8-supply = <&pm8916_l7>;
|
||||
v3p3-supply = <&pm8916_l13>;
|
||||
};
|
||||
|
||||
&wcnss {
|
||||
vddpx-supply = <&pm8916_l7>;
|
||||
};
|
||||
|
||||
&wcnss_iris {
|
||||
vddxo-supply = <&pm8916_l7>;
|
||||
vddrfa-supply = <&pm8916_s3>;
|
||||
vddpa-supply = <&pm8916_l9>;
|
||||
vdddig-supply = <&pm8916_l5>;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8929-pm8916.dtsi"
|
||||
#include "msm8939-wingtech-wt82918.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Lenovo Vibe K5 (HD) (Wingtech WT82918)";
|
||||
compatible = "wingtech,wt82918hd", "qcom,msm8929";
|
||||
chassis-type = "handset";
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
touchscreen-size-x = <720>;
|
||||
touchscreen-size-y = <1280>;
|
||||
};
|
||||
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include "msm8939.dtsi"
|
||||
|
||||
&opp_table {
|
||||
/delete-node/ opp-550000000;
|
||||
};
|
||||
@@ -159,6 +159,26 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
flash-led-controller@53 {
|
||||
compatible = "silergy,sy7802";
|
||||
reg = <0x53>;
|
||||
|
||||
enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&camera_rear_flash_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_FLASH;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
led-sources = <0>, <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c3 {
|
||||
@@ -318,6 +338,13 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
camera_rear_flash_default: camera-rear-flash-default-state {
|
||||
pins = "gpio9", "gpio16", "gpio51";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
gpio_hall_sensor_default: gpio-hall-sensor-default-state {
|
||||
pins = "gpio20";
|
||||
function = "gpio";
|
||||
|
||||
@@ -198,7 +198,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
pwm_vibrator: pwm-vibrator {
|
||||
pwm_vibrator: pwm {
|
||||
compatible = "clk-pwm";
|
||||
#pwm-cells = <2>;
|
||||
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8939-pm8916.dtsi"
|
||||
#include "msm8939-wingtech-wt82918.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Lenovo Vibe K5 (Wingtech WT82918)";
|
||||
compatible = "wingtech,wt82918", "qcom,msm8939";
|
||||
chassis-type = "handset";
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
touchscreen-size-x = <1080>;
|
||||
touchscreen-size-y = <1920>;
|
||||
};
|
||||
@@ -0,0 +1,252 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include "msm8916-modem-qdsp6.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc0 = &sdhc_1; /* eMMC */
|
||||
mmc1 = &sdhc_2; /* SD card */
|
||||
serial0 = &blsp_uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pm8916_pwm 0 100000>;
|
||||
brightness-levels = <0 255>;
|
||||
num-interpolated-steps = <255>;
|
||||
default-brightness-level = <128>;
|
||||
};
|
||||
|
||||
flash-led-controller {
|
||||
compatible = "sgmicro,sgm3140";
|
||||
enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
|
||||
flash-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&camera_front_flash_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
flash_led: led {
|
||||
function = LED_FUNCTION_FLASH;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&gpio_keys_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
label = "GPIO Buttons";
|
||||
|
||||
button-volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pinctrl-0 = <&gpio_leds_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
led-0 {
|
||||
gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
|
||||
function = LED_FUNCTION_CHARGING;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
default-state = "off";
|
||||
retain-state-suspended;
|
||||
};
|
||||
|
||||
led-1 {
|
||||
gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "off";
|
||||
retain-state-suspended;
|
||||
};
|
||||
};
|
||||
|
||||
usb_id: usb-id {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&usb_id_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c2 {
|
||||
status = "okay";
|
||||
|
||||
accelerometer@68 {
|
||||
compatible = "invensense,icm20608";
|
||||
reg = <0x68>;
|
||||
|
||||
interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
pinctrl-0 = <&accelerometer_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vdd-supply = <&pm8916_l17>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
|
||||
mount-matrix = "-1", "0", "0",
|
||||
"0", "1", "0",
|
||||
"0", "0", "1";
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c5 {
|
||||
status = "okay";
|
||||
|
||||
touchscreen: touchscreen@38 {
|
||||
compatible = "edt,edt-ft5306";
|
||||
reg = <0x38>;
|
||||
|
||||
interrupts-extended = <&tlmm 13 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-0 = <&touchscreen_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vcc-supply = <&pm8916_l17>;
|
||||
iovcc-supply = <&pm8916_l6>;
|
||||
|
||||
reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mpss_mem {
|
||||
reg = <0x0 0x86800000 0x0 0x5500000>;
|
||||
};
|
||||
|
||||
&pm8916_pwm {
|
||||
pinctrl-0 = <&pwm_out>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8916_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8916_rpm_regulators {
|
||||
pm8916_l17: l17 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pm8916_vib {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
pinctrl-0 = <&sdc2_default>;
|
||||
pinctrl-1 = <&sdc2_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
extcon = <&usb_id>, <&usb_id>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_hs_phy {
|
||||
extcon = <&usb_id>;
|
||||
};
|
||||
|
||||
&wcnss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcnss_iris {
|
||||
compatible = "qcom,wcn3620";
|
||||
};
|
||||
|
||||
&wcnss_mem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
accelerometer_default: accelerometer-default-state {
|
||||
pins = "gpio115";
|
||||
function = "gpio";
|
||||
drive-strength = <6>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
camera_front_flash_default: camera-front-flash-default-state {
|
||||
pins = "gpio31", "gpio32";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
gpio_keys_default: gpio-keys-default-state {
|
||||
pins = "gpio107";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
gpio_leds_default: gpio-leds-default-state {
|
||||
pins = "gpio36", "gpio69";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
touchscreen_default: touchscreen-default-state {
|
||||
reset-pins {
|
||||
pins = "gpio12";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
touchscreen-pins {
|
||||
pins = "gpio13";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usb_id_default: usb-id-default-state {
|
||||
pins = "gpio110";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&pm8916_mpps {
|
||||
pwm_out: mpp4-state {
|
||||
pins = "mpp4";
|
||||
function = "digital";
|
||||
power-source = <PM8916_MPP_VPH>;
|
||||
output-low;
|
||||
qcom,dtest = <1>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8939-pm8916.dtsi"
|
||||
#include "msm8939-wingtech-wt82918.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Lenovo Vibe K5 (HD) (Wingtech WT82918)";
|
||||
compatible = "wingtech,wt82918hdhw39", "qcom,msm8939";
|
||||
chassis-type = "handset";
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
touchscreen-size-x = <720>;
|
||||
touchscreen-size-y = <1280>;
|
||||
};
|
||||
@@ -252,7 +252,7 @@
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-msm8936";
|
||||
compatible = "qcom,rpm-msm8936", "qcom,smd-rpm";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -199,7 +199,7 @@
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-msm8953";
|
||||
compatible = "qcom,rpm-msm8953", "qcom,smd-rpm";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -247,7 +247,7 @@
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-msm8976";
|
||||
compatible = "qcom,rpm-msm8976", "qcom,smd-rpm";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
@@ -663,6 +663,11 @@
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
restart@4ab000 {
|
||||
compatible = "qcom,pshold";
|
||||
reg = <0x004ab000 0x4>;
|
||||
};
|
||||
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,msm8976-pinctrl";
|
||||
reg = <0x01000000 0x300000>;
|
||||
|
||||
@@ -0,0 +1,231 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* MSM8992 LG G4 (h815) device tree.
|
||||
*
|
||||
* Copyright (c) 2024, Alexander Reimelt <alexander.reimelt@posteo.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8992.dtsi"
|
||||
#include "pm8994.dtsi"
|
||||
#include "pmi8994.dtsi"
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/* different mapping */
|
||||
/delete-node/ &cont_splash_mem;
|
||||
|
||||
/* disabled downstream */
|
||||
/delete-node/ &dfps_data_mem;
|
||||
|
||||
/ {
|
||||
model = "LG G4 (H815)";
|
||||
compatible = "lg,h815", "qcom,msm8992";
|
||||
chassis-type = "handset";
|
||||
|
||||
qcom,msm-id = <0xfb 0x0>;
|
||||
qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
|
||||
qcom,board-id = <0xb64 0x0>;
|
||||
|
||||
/* psci is broken */
|
||||
/delete-node/ psci;
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
spin-table@6000000 {
|
||||
reg = <0x0 0x06000000 0x0 0x00001000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ramoops@ff00000 {
|
||||
compatible = "ramoops";
|
||||
reg = <0x0 0x0ff00000 0x0 0x00100000>;
|
||||
console-size = <0x20000>;
|
||||
pmsg-size = <0x20000>;
|
||||
record-size = <0x10000>;
|
||||
ecc-size = <0x10>;
|
||||
};
|
||||
|
||||
cont_splash_mem: fb@3400000 {
|
||||
reg = <0x0 0x03400000 0x0 0x00c00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
crash_fb_mem: crash-fb@4000000 {
|
||||
reg = <0x0 0x04000000 0x0 0x00c00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-hall-sensor {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&hall_sensor_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
label = "Hall Effect Sensor";
|
||||
|
||||
event-hall-sensor {
|
||||
gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
|
||||
label = "hall effect sensor";
|
||||
linux,input-type = <EV_SW>;
|
||||
linux,code = <SW_LID>;
|
||||
linux,can-disable;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-vol-up {
|
||||
label = "volume up";
|
||||
gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
wakeup-source;
|
||||
debounce-interval = <15>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&CPU0 {
|
||||
enable-method = "spin-table";
|
||||
};
|
||||
|
||||
&CPU1 {
|
||||
enable-method = "spin-table";
|
||||
};
|
||||
|
||||
&CPU2 {
|
||||
enable-method = "spin-table";
|
||||
};
|
||||
|
||||
&CPU3 {
|
||||
enable-method = "spin-table";
|
||||
};
|
||||
|
||||
&CPU4 {
|
||||
enable-method = "spin-table";
|
||||
};
|
||||
|
||||
&CPU5 {
|
||||
enable-method = "spin-table";
|
||||
};
|
||||
|
||||
&pm8994_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
regulators-0 {
|
||||
compatible = "qcom,rpm-pm8994-regulators";
|
||||
|
||||
vdd_s3-supply = <&vph_pwr>;
|
||||
vdd_s4-supply = <&vph_pwr>;
|
||||
vdd_s5-supply = <&vph_pwr>;
|
||||
vdd_s7-supply = <&vph_pwr>;
|
||||
vdd_l1-supply = <&pmi8994_s1>;
|
||||
vdd_l2_26_28-supply = <&pm8994_s3>;
|
||||
vdd_l3_11-supply = <&pm8994_s3>;
|
||||
vdd_l4_27_31-supply = <&pm8994_s3>;
|
||||
vdd_l5_7-supply = <&pm8994_s5>;
|
||||
vdd_l6_12_32-supply = <&pm8994_s5>;
|
||||
vdd_l8_16_30-supply = <&vph_pwr>;
|
||||
vdd_l9_10_18_22-supply = <&pmi8994_bby>;
|
||||
vdd_l13_19_23_24-supply = <&pmi8994_bby>;
|
||||
vdd_l14_15-supply = <&pm8994_s5>;
|
||||
vdd_l17_29-supply = <&pmi8994_bby>;
|
||||
vdd_l20_21-supply = <&pmi8994_bby>;
|
||||
vdd_l25-supply = <&pm8994_s5>;
|
||||
vdd_lvs1_2-supply = <&pm8994_s4>;
|
||||
|
||||
pm8994_s3: s3 {
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
|
||||
/* sdhc1 vqmmc and bcm */
|
||||
pm8994_s4: s4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-system-load = <325000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
pm8994_s5: s5 {
|
||||
regulator-min-microvolt = <2150000>;
|
||||
regulator-max-microvolt = <2150000>;
|
||||
};
|
||||
|
||||
/* sdhc2 vqmmc */
|
||||
pm8994_l13: l13 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
regulator-system-load = <22000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
/* sdhc1 vmmc */
|
||||
pm8994_l20: l20 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
regulator-system-load = <570000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
/* sdhc2 vmmc */
|
||||
pm8994_l21: l21 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
regulator-system-load = <800000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-1 {
|
||||
compatible = "qcom,rpm-pmi8994-regulators";
|
||||
|
||||
vdd_s1-supply = <&vph_pwr>;
|
||||
vdd_bst_byp-supply = <&vph_pwr>;
|
||||
|
||||
pmi8994_s1: s1 {
|
||||
regulator-min-microvolt = <1025000>;
|
||||
regulator-max-microvolt = <1025000>;
|
||||
};
|
||||
|
||||
/* S2 & S3 - VDD_GFX */
|
||||
|
||||
pmi8994_bby: boost-bypass {
|
||||
regulator-min-microvolt = <3150000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc1 {
|
||||
mmc-hs400-1_8v;
|
||||
vmmc-supply = <&pm8994_l20>;
|
||||
vqmmc-supply = <&pm8994_s4>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc2 {
|
||||
vmmc-supply = <&pm8994_l21>;
|
||||
vqmmc-supply = <&pm8994_l13>;
|
||||
cd-gpios = <&pm8994_gpios 8 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
hall_sensor_default: hall-sensor-default-state {
|
||||
pins = "gpio75";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
@@ -188,7 +188,7 @@
|
||||
qcom,remote-pid = <6>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-msm8994";
|
||||
compatible = "qcom,rpm-msm8994", "qcom,smd-rpm";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -472,7 +472,7 @@
|
||||
mboxes = <&apcs_glb 0>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-msm8996";
|
||||
compatible = "qcom,rpm-msm8996", "qcom,glink-smd-rpm";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -352,7 +352,7 @@
|
||||
mboxes = <&apcs_glb 0>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-msm8998";
|
||||
compatible = "qcom,rpm-msm8998", "qcom,glink-smd-rpm";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
@@ -1586,6 +1586,33 @@
|
||||
"gpll0";
|
||||
};
|
||||
|
||||
lpass_q6_smmu: iommu@5100000 {
|
||||
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
|
||||
reg = <0x05100000 0x40000>;
|
||||
clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
|
||||
clock-names = "bus";
|
||||
|
||||
#global-interrupts = <0>;
|
||||
#iommu-cells = <1>;
|
||||
interrupts =
|
||||
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
power-domains = <&gcc LPASS_ADSP_GDSC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
remoteproc_slpi: remoteproc@5800000 {
|
||||
compatible = "qcom,msm8998-slpi-pas";
|
||||
reg = <0x05800000 0x4040>;
|
||||
|
||||
@@ -18,7 +18,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pon@800 {
|
||||
pm8950_pon: pon@800 {
|
||||
compatible = "qcom,pm8916-pon";
|
||||
reg = <0x0800>;
|
||||
mode-bootloader = <0x2>;
|
||||
@@ -31,6 +31,14 @@
|
||||
bias-pull-up;
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
|
||||
pm8950_resin: resin {
|
||||
compatible = "qcom,pm8941-resin";
|
||||
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
|
||||
debounce = <15625>;
|
||||
bias-pull-up;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pm8950_temp: temp-alarm@2400 {
|
||||
|
||||
@@ -84,9 +84,8 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmi8950_pwm: pwm@b000 {
|
||||
pmi8950_pwm: pwm {
|
||||
compatible = "qcom,pmi8950-pwm";
|
||||
reg = <0xb000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
@@ -57,8 +57,11 @@
|
||||
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
|
||||
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ovp", "short";
|
||||
label = "backlight";
|
||||
|
||||
qcom,cabc;
|
||||
qcom,external-pfet;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -215,7 +215,7 @@
|
||||
mboxes = <&apcs_glb 0>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-qcm2290";
|
||||
compatible = "qcom,rpm-qcm2290", "qcom,glink-smd-rpm";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -641,6 +641,21 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdc2_clk {
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
&sdc2_cmd {
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
&sdc2_data {
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
non-removable;
|
||||
no-sd;
|
||||
@@ -652,9 +667,27 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>;
|
||||
pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>;
|
||||
|
||||
vmmc-supply = <&vreg_l9c_2p96>;
|
||||
vqmmc-supply = <&vreg_l6c_2p96>;
|
||||
|
||||
cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <32 2>, /* ADSP */
|
||||
<48 4>; /* NFC */
|
||||
|
||||
sd_cd: sd-cd-state {
|
||||
pins = "gpio91";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
|
||||
@@ -177,7 +177,7 @@
|
||||
mboxes = <&apcs_glb 0>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-qcs404";
|
||||
compatible = "qcom,rpm-qcs404", "qcom,glink-smd-rpm";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -9,6 +9,10 @@
|
||||
|
||||
#include "sm8150.dtsi"
|
||||
|
||||
&camcc {
|
||||
power-domains = <&rpmhpd SA8155P_CX>;
|
||||
};
|
||||
|
||||
&dispcc {
|
||||
power-domains = <&rpmhpd SA8155P_CX>;
|
||||
};
|
||||
|
||||
@@ -9,6 +9,7 @@
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
|
||||
|
||||
#include "sa8540p.dtsi"
|
||||
#include "sa8540p-pmics.dtsi"
|
||||
@@ -109,6 +110,46 @@
|
||||
};
|
||||
};
|
||||
|
||||
regulator-usb2-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB2_VBUS";
|
||||
gpio = <&pmm8540c_gpios 9 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&usb2_en>;
|
||||
pinctrl-names = "default";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator-usb3-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB3_VBUS";
|
||||
gpio = <&pmm8540e_gpios 5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&usb3_en>;
|
||||
pinctrl-names = "default";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator-usb4-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB4_VBUS";
|
||||
gpio = <&pmm8540g_gpios 5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&usb4_en>;
|
||||
pinctrl-names = "default";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator-usb5-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB5_VBUS";
|
||||
gpio = <&pmm8540g_gpios 9 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&usb5_en>;
|
||||
pinctrl-names = "default";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
gpu_mem: gpu-mem@8bf00000 {
|
||||
reg = <0 0x8bf00000 0 0x2000>;
|
||||
@@ -637,6 +678,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2_hsphy0 {
|
||||
vdda-pll-supply = <&vreg_l5a>;
|
||||
vdda18-supply = <&vreg_l7g>;
|
||||
@@ -697,6 +742,44 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pmm8540c_gpios {
|
||||
usb2_en: usb2-en-state {
|
||||
pins = "gpio9";
|
||||
function = "normal";
|
||||
qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
|
||||
output-enable;
|
||||
power-source = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pmm8540e_gpios {
|
||||
usb3_en: usb3-en-state {
|
||||
pins = "gpio5";
|
||||
function = "normal";
|
||||
qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
|
||||
output-enable;
|
||||
power-source = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pmm8540g_gpios {
|
||||
usb4_en: usb4-en-state {
|
||||
pins = "gpio5";
|
||||
function = "normal";
|
||||
qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
|
||||
output-enable;
|
||||
power-source = <0>;
|
||||
};
|
||||
|
||||
usb5_en: usb5-en-state {
|
||||
pins = "gpio9";
|
||||
function = "normal";
|
||||
qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
|
||||
output-enable;
|
||||
power-source = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
pcie2a_default: pcie2a-default-state {
|
||||
clkreq-n-pins {
|
||||
|
||||
@@ -702,6 +702,31 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/sa8775p/adsp.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp0 {
|
||||
firmware-name = "qcom/sa8775p/cdsp0.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp1 {
|
||||
firmware-name = "qcom/sa8775p/cdsp1.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_gpdsp0 {
|
||||
firmware-name = "qcom/sa8775p/gpdsp0.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_gpdsp1 {
|
||||
firmware-name = "qcom/sa8775p/gpdsp1.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart10 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
pinctrl-0 = <&qup_uart10_default>;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -484,6 +484,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmc8180_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmc8180c_lpg {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -557,6 +561,40 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_hsphy0 {
|
||||
vdda-pll-supply = <&vreg_l5e_0p88>;
|
||||
vdda18-supply = <&vreg_l12a_1p8>;
|
||||
vdda33-supply = <&vreg_l16e_3p0>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_hsphy1 {
|
||||
vdda-pll-supply = <&vreg_l5e_0p88>;
|
||||
vdda18-supply = <&vreg_l12a_1p8>;
|
||||
vdda33-supply = <&vreg_l16e_3p0>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_qmpphy0 {
|
||||
vdda-phy-supply = <&vreg_l3c_1p2>;
|
||||
vdda-pll-supply = <&vreg_l5e_0p88>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_qmpphy1 {
|
||||
vdda-phy-supply = <&vreg_l3c_1p2>;
|
||||
vdda-pll-supply = <&vreg_l5e_0p88>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_prim_hsphy {
|
||||
vdda-pll-supply = <&vreg_l5e_0p88>;
|
||||
vdda18-supply = <&vreg_l12a_1p8>;
|
||||
|
||||
@@ -75,7 +75,7 @@
|
||||
pon: pon@800 {
|
||||
compatible = "qcom,pm8916-pon";
|
||||
reg = <0x0800>;
|
||||
pwrkey {
|
||||
pmc8180_pwrkey: pwrkey {
|
||||
compatible = "qcom,pm8941-pwrkey";
|
||||
interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
debounce = <15625>;
|
||||
@@ -139,11 +139,11 @@
|
||||
interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
|
||||
};
|
||||
|
||||
pmc8180_gpios: gpio@c000 {
|
||||
pmc8180_1_gpios: gpio@c000 {
|
||||
compatible = "qcom,pmc8180-gpio", "qcom,spmi-gpio";
|
||||
reg = <0xc000>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pmc8180_gpios 0 0 10>;
|
||||
gpio-ranges = <&pmc8180_1_gpios 0 0 10>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
@@ -198,11 +198,21 @@
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
pmic@8 {
|
||||
pmc8180_2: pmic@8 {
|
||||
compatible = "qcom,pm8150", "qcom,spmi-pmic";
|
||||
reg = <0x8 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmc8180_2_gpios: gpio@c000 {
|
||||
compatible = "qcom,pmc8180-gpio", "qcom,spmi-gpio";
|
||||
reg = <0xc000>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pmc8180_2_gpios 0 0 10>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic@a {
|
||||
|
||||
@@ -223,6 +223,32 @@
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
|
||||
vreg_usb2_host_en: regulator-usb2-host-en {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb2_host_en";
|
||||
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
gpio = <&pmc8180_1_gpios 9 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_usb3_host_en: regulator-usb3-host-en {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb3_host_en";
|
||||
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
gpio = <&pmc8180_2_gpios 9 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
usbprim-sbu-mux {
|
||||
compatible = "pericom,pi3usb102", "gpio-sbu-mux";
|
||||
|
||||
@@ -552,6 +578,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmc8180_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmc8180c_lpg {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -623,6 +653,40 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_hsphy0 {
|
||||
vdda-pll-supply = <&vreg_l5e_0p88>;
|
||||
vdda18-supply = <&vreg_l12a_1p8>;
|
||||
vdda33-supply = <&vreg_l16e_3p0>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_hsphy1 {
|
||||
vdda-pll-supply = <&vreg_l5e_0p88>;
|
||||
vdda18-supply = <&vreg_l12a_1p8>;
|
||||
vdda33-supply = <&vreg_l16e_3p0>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_qmpphy0 {
|
||||
vdda-phy-supply = <&vreg_l3c_1p2>;
|
||||
vdda-pll-supply = <&vreg_l5e_0p88>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_qmpphy1 {
|
||||
vdda-phy-supply = <&vreg_l3c_1p2>;
|
||||
vdda-pll-supply = <&vreg_l5e_0p88>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_prim_hsphy {
|
||||
vdda-pll-supply = <&vreg_l5e_0p88>;
|
||||
vdda18-supply = <&vreg_l12a_1p8>;
|
||||
|
||||
@@ -2507,6 +2507,34 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_mp_hsphy0: phy@88e4000 {
|
||||
compatible = "qcom,sc8180x-usb-hs-phy",
|
||||
"qcom,usb-snps-hs-7nm-phy";
|
||||
reg = <0 0x088e4000 0 0x400>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "ref";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_MP0_BCR>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_mp_hsphy1: phy@88e5000 {
|
||||
compatible = "qcom,sc8180x-usb-hs-phy",
|
||||
"qcom,usb-snps-hs-7nm-phy";
|
||||
reg = <0 0x088e5000 0 0x400>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "ref";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_MP1_BCR>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_prim_qmpphy: phy@88e8000 {
|
||||
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
|
||||
reg = <0 0x088e8000 0 0x3000>;
|
||||
@@ -2555,6 +2583,60 @@
|
||||
};
|
||||
};
|
||||
|
||||
usb_mp_qmpphy0: phy@88eb000 {
|
||||
compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
|
||||
reg = <0 0x088eb000 0 0x1000>;
|
||||
|
||||
clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
||||
<&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
|
||||
<&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
|
||||
clock-names = "aux",
|
||||
"ref",
|
||||
"com_aux",
|
||||
"pipe";
|
||||
|
||||
resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
|
||||
<&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
|
||||
reset-names = "phy", "phy_phy";
|
||||
|
||||
power-domains = <&gcc USB30_MP_GDSC>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "usb2_phy0_pipe_clk";
|
||||
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_mp_qmpphy1: phy@88ec000 {
|
||||
compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
|
||||
reg = <0 0x088ec000 0 0x1000>;
|
||||
|
||||
clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
||||
<&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
|
||||
<&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
|
||||
clock-names = "aux",
|
||||
"ref",
|
||||
"com_aux",
|
||||
"pipe";
|
||||
|
||||
resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
|
||||
<&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
|
||||
reset-names = "phy", "phy_phy";
|
||||
|
||||
power-domains = <&gcc USB30_MP_GDSC>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "usb2_phy1_pipe_clk";
|
||||
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_sec_qmpphy: phy@88ee000 {
|
||||
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
|
||||
reg = <0 0x088ed000 0 0x3000>;
|
||||
@@ -2622,17 +2704,89 @@
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
usb_mp: usb@a4f8800 {
|
||||
compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
|
||||
reg = <0 0x0a4f8800 0 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
|
||||
<&gcc GCC_USB30_MP_MASTER_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
|
||||
<&gcc GCC_USB30_MP_SLEEP_CLK>,
|
||||
<&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
|
||||
clock-names = "cfg_noc",
|
||||
"core",
|
||||
"iface",
|
||||
"sleep",
|
||||
"mock_utmi",
|
||||
"xo";
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_MP_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 59 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 46 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 71 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 68 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event_1", "pwr_event_2",
|
||||
"hs_phy_1", "hs_phy_2",
|
||||
"dp_hs_phy_1", "dm_hs_phy_1",
|
||||
"dp_hs_phy_2", "dm_hs_phy_2",
|
||||
"ss_phy_1", "ss_phy_2";
|
||||
|
||||
power-domains = <&gcc USB30_MP_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_USB30_MP_BCR>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
usb_mp_dwc3: usb@a400000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a400000 0 0xcd00>;
|
||||
interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x60 0>;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
phys = <&usb_mp_hsphy0>,
|
||||
<&usb_mp_qmpphy0>,
|
||||
<&usb_mp_hsphy1>,
|
||||
<&usb_mp_qmpphy1>;
|
||||
phy-names = "usb2-0",
|
||||
"usb3-0",
|
||||
"usb2-1",
|
||||
"usb3-1";
|
||||
dr_mode = "host";
|
||||
};
|
||||
};
|
||||
|
||||
usb_prim: usb@a6f8800 {
|
||||
compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a6f8800 0 0x400>;
|
||||
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 9 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
|
||||
interrupt-names = "hs_phy_irq",
|
||||
"ss_phy_irq",
|
||||
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event",
|
||||
"hs_phy_irq",
|
||||
"dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq",
|
||||
"dp_hs_phy_irq";
|
||||
"ss_phy_irq";
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
||||
@@ -2714,12 +2868,17 @@
|
||||
"xo";
|
||||
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||||
power-domains = <&gcc USB30_SEC_GDSC>;
|
||||
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 11 IRQ_TYPE_EDGE_BOTH>;
|
||||
interrupt-names = "hs_phy_irq", "ss_phy_irq",
|
||||
"dm_hs_phy_irq", "dp_hs_phy_irq";
|
||||
<&pdc 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event",
|
||||
"hs_phy_irq",
|
||||
"dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq",
|
||||
"ss_phy_irq";
|
||||
|
||||
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MASTER_CLK>;
|
||||
|
||||
@@ -848,15 +848,15 @@
|
||||
pins = "gpio143";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio145";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins = "gpio145";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie3a_default: pcie3a-default-state {
|
||||
@@ -871,7 +871,7 @@
|
||||
pins = "gpio151";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
@@ -894,7 +894,7 @@
|
||||
pins = "gpio141";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
|
||||
@@ -592,6 +592,57 @@
|
||||
};
|
||||
};
|
||||
|
||||
&camss {
|
||||
vdda-phy-supply = <&vreg_l6d>;
|
||||
vdda-pll-supply = <&vreg_l4d>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
csiphy0_lanes01_ep: endpoint@0 {
|
||||
reg = <0>;
|
||||
clock-lanes = <7>;
|
||||
data-lanes = <0 1>;
|
||||
remote-endpoint = <&ov5675_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cci2_i2c1 {
|
||||
camera@10 {
|
||||
compatible = "ovti,ov5675";
|
||||
reg = <0x10>;
|
||||
|
||||
reset-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cam_rgb_default>;
|
||||
|
||||
clocks = <&camcc CAMCC_MCLK3_CLK>;
|
||||
|
||||
orientation = <0>; /* Front facing */
|
||||
|
||||
avdd-supply = <&vreg_l6q>;
|
||||
dvdd-supply = <&vreg_l2q>;
|
||||
dovdd-supply = <&vreg_l7q>;
|
||||
|
||||
port {
|
||||
ov5675_ep: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
link-frequencies = /bits/ 64 <450000000>;
|
||||
remote-endpoint = <&csiphy0_lanes01_ep>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
&dispcc0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1436,6 +1487,22 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cam_rgb_default: cam-rgb-default-state {
|
||||
mclk-pins {
|
||||
pins = "gpio17";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sc-rgb-xshut-n-pins {
|
||||
pins = "gpio15";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
edp_reg_en: edp-reg-en-state {
|
||||
pins = "gpio25";
|
||||
function = "gpio";
|
||||
@@ -1509,15 +1576,15 @@
|
||||
pins = "gpio143";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio145";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins = "gpio145";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie3a_default: pcie3a-default-state {
|
||||
@@ -1532,7 +1599,7 @@
|
||||
pins = "gpio151";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
@@ -1555,7 +1622,7 @@
|
||||
pins = "gpio141";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
|
||||
@@ -372,7 +372,7 @@
|
||||
mboxes = <&apcs_glb 0>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-sdm660";
|
||||
compatible = "qcom,rpm-sdm660", "qcom,glink-smd-rpm";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -282,6 +282,12 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_mpss {
|
||||
firmware-name = "qcom/sdx75/modem.mbn",
|
||||
"qcom/sdx75/modem_dtb.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc {
|
||||
cd-gpios = <&tlmm 103 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_2v95_vdd>;
|
||||
|
||||
@@ -366,7 +366,12 @@
|
||||
no-map;
|
||||
};
|
||||
|
||||
qdss_mem: qdss@88800000 {
|
||||
qdss_mem: qdss@88500000 {
|
||||
reg = <0x0 0x88500000 0x0 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qlink_logging_mem: qlink-logging@88800000 {
|
||||
reg = <0x0 0x88800000 0x0 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
@@ -377,8 +382,13 @@
|
||||
no-map;
|
||||
};
|
||||
|
||||
mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
|
||||
reg = <0x0 0x88f00000 0x0 0x5080000>;
|
||||
mpss_dsm_mem_2: mpss-dsm-2@88f00000 {
|
||||
reg = <0x0 0x88f00000 0x0 0x2500000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mpss_dsm_mem: mpss-dsm@8b400000 {
|
||||
reg = <0x0 0x8b400000 0x0 0x2b80000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
@@ -388,7 +398,7 @@
|
||||
};
|
||||
|
||||
mpssadsp_mem: mpssadsp@8e000000 {
|
||||
reg = <0x0 0x8e000000 0x0 0xf400000>;
|
||||
reg = <0x0 0x8e000000 0x0 0xf100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
@@ -881,6 +891,53 @@
|
||||
reg = <0x0 0x01fc0000 0x0 0x30000>;
|
||||
};
|
||||
|
||||
remoteproc_mpss: remoteproc@4080000 {
|
||||
compatible = "qcom,sdx75-mpss-pas";
|
||||
reg = <0 0x04080000 0 0x4040>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog",
|
||||
"fatal",
|
||||
"ready",
|
||||
"handover",
|
||||
"stop-ack",
|
||||
"shutdown-ack";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_CX>,
|
||||
<&rpmhpd RPMHPD_MSS>;
|
||||
power-domain-names = "cx",
|
||||
"mss";
|
||||
|
||||
memory-region = <&mpssadsp_mem>, <&q6_mpss_dtb_mem>,
|
||||
<&mpss_dsm_mem>, <&mpss_dsm_mem_2>,
|
||||
<&qlink_logging_mem>;
|
||||
|
||||
qcom,qmp = <&aoss_qmp>;
|
||||
|
||||
qcom,smem-states = <&smp2p_modem_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
glink-edge {
|
||||
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
|
||||
IPCC_MPROC_SIGNAL_PING
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc IPCC_CLIENT_MPSS
|
||||
IPCC_MPROC_SIGNAL_PING>;
|
||||
label = "mpss";
|
||||
qcom,remote-pid = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhc: mmc@8804000 {
|
||||
compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5";
|
||||
reg = <0x0 0x08804000 0x0 0x1000>;
|
||||
|
||||
@@ -4,7 +4,10 @@
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sm4450-camcc.h>
|
||||
#include <dt-bindings/clock/qcom,sm4450-dispcc.h>
|
||||
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,sm4450-gpucc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
@@ -422,6 +425,41 @@
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
gpucc: clock-controller@3d90000 {
|
||||
compatible = "qcom,sm4450-gpucc";
|
||||
reg = <0x0 0x03d90000 0x0 0xa000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
camcc: clock-controller@ade0000 {
|
||||
compatible = "qcom,sm4450-camcc";
|
||||
reg = <0x0 0x0ade0000 0x0 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
dispcc: clock-controller@af00000 {
|
||||
compatible = "qcom,sm4450-dispcc";
|
||||
reg = <0x0 0x0af00000 0x0 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&sleep_clk>,
|
||||
<0>,
|
||||
<0>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,sm4450-pdc", "qcom,pdc";
|
||||
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
|
||||
|
||||
@@ -1,13 +1,16 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) 2023, Dang Huynh <danct12@riseup.net>
|
||||
* Copyright (c) 2023 - 2024, Dang Huynh <danct12@riseup.net>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sm6115.dtsi"
|
||||
#include "pm6125.dtsi"
|
||||
#include "pmi632.dtsi"
|
||||
#include <dt-bindings/arm/qcom,ids.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
|
||||
/ {
|
||||
model = "F(x)tec Pro1X (QX1050)";
|
||||
@@ -32,12 +35,48 @@
|
||||
};
|
||||
};
|
||||
|
||||
disp_elvdd_supply: disp-elvdd-supply {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "disp_elvdd_supply";
|
||||
};
|
||||
|
||||
disp_elvss_supply: disp-elvss-supply {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "disp_elvss_supply";
|
||||
};
|
||||
|
||||
disp_vcc_supply: disp-vcc-supply {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "disp_vcc_supply";
|
||||
};
|
||||
|
||||
disp_vci_supply: disp-vci-supply {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "disp_vci_supply";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&vol_up_n>;
|
||||
pinctrl-0 = <&hall_sensor_n>, <&key_camera_n>, <&vol_up_n>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
hall-switch {
|
||||
label = "Hall Switch";
|
||||
linux,input-type = <EV_SW>;
|
||||
linux,code = <SW_KEYPAD_SLIDE>;
|
||||
gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
|
||||
debounce-interval = <90>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
key-camera {
|
||||
label = "Camera Button";
|
||||
linux,code = <KEY_CAMERA>;
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <15>;
|
||||
};
|
||||
|
||||
key-volume-up {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
@@ -47,11 +86,119 @@
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
capslock-led {
|
||||
label = "green:capslock";
|
||||
function = LED_FUNCTION_CAPSLOCK;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&pca9534 1 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "kbd-capslock";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
ts_vdd_supply: ts-vdd-supply {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ts_vdd_supply";
|
||||
gpio = <&pca9534 3 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
ts_vddio_supply: ts-vddio-supply {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ts_vddio_supply";
|
||||
gpio = <&pca9534 2 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&dispcc {
|
||||
/* HACK: disable until a panel driver is ready to retain simplefb */
|
||||
status = "disabled";
|
||||
&gpi_dma0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
|
||||
zap-shader {
|
||||
firmware-name = "qcom/sm6115/Fxtec/QX1050/a610_zap.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
pca9534: gpio@21 {
|
||||
compatible = "nxp,pca9534";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
/* Clock frequency was not specified downstream, let's park it to 100 KHz */
|
||||
clock-frequency = <100000>;
|
||||
|
||||
touchscreen@14 {
|
||||
compatible = "goodix,gt9286";
|
||||
reg = <0x14>;
|
||||
|
||||
interrupts-extended = <&tlmm 80 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
irq-gpios = <&tlmm 80 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&tlmm 71 GPIO_ACTIVE_HIGH>;
|
||||
AVDD28-supply = <&ts_vdd_supply>;
|
||||
VDDIO-supply = <&ts_vddio_supply>;
|
||||
|
||||
pinctrl-0 = <&ts_int_n>, <&ts_rst_n>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-supply = <&pm6125_l18a>;
|
||||
status = "okay";
|
||||
|
||||
panel: panel@0 {
|
||||
compatible = "boe,bf060y8m-aj0";
|
||||
reg = <0>;
|
||||
|
||||
reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
|
||||
|
||||
elvdd-supply = <&disp_elvdd_supply>;
|
||||
elvss-supply = <&disp_elvss_supply>;
|
||||
vcc-supply = <&disp_vcc_supply>;
|
||||
vci-supply = <&disp_vci_supply>;
|
||||
vddio-supply = <&pm6125_l9a>;
|
||||
|
||||
pinctrl-0 = <&mdss_dsi_n &panel_en_n>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm6125_gpios {
|
||||
@@ -64,6 +211,73 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pmi632_lpg {
|
||||
status = "okay";
|
||||
|
||||
multi-led {
|
||||
color = <LED_COLOR_ID_RGB>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led@3 {
|
||||
reg = <3>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmi632_typec {
|
||||
status = "okay";
|
||||
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
|
||||
power-role = "dual";
|
||||
data-role = "dual";
|
||||
self-powered;
|
||||
|
||||
typec-power-opmode = "default";
|
||||
pd-disable;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
pmi632_hs_in: endpoint {
|
||||
remote-endpoint = <&usb_dwc3_hs>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
pmi632_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_qmpphy_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmi632_vbus {
|
||||
regulator-min-microamp = <500000>;
|
||||
regulator-max-microamp = <1000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -73,6 +287,25 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/sm6115/Fxtec/QX1050/adsp.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
firmware-name = "qcom/sm6115/Fxtec/QX1050/cdsp.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_mpss {
|
||||
firmware-name = "qcom/sm6115/Fxtec/QX1050/modem.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
regulators-0 {
|
||||
compatible = "qcom,rpm-pm6125-regulators";
|
||||
@@ -105,6 +338,7 @@
|
||||
pm6125_l5a: l5 {
|
||||
regulator-min-microvolt = <1648000>;
|
||||
regulator-max-microvolt = <3056000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
pm6125_l6a: l6 {
|
||||
@@ -206,12 +440,84 @@
|
||||
};
|
||||
};
|
||||
|
||||
&sdc2_state_off {
|
||||
cd-pins {
|
||||
pins = "gpio88";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&sdc2_state_on {
|
||||
cd-pins {
|
||||
pins = "gpio88";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
pinctrl-0 = <&sdc2_state_on>;
|
||||
pinctrl-1 = <&sdc2_state_off>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vmmc-supply = <&pm6125_l22a>;
|
||||
vqmmc-supply = <&pm6125_l5a>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sleep_clk {
|
||||
clock-frequency = <32764>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <14 4>;
|
||||
|
||||
key_camera_n: key-camera-n-state {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
panel_en_n: panel-en-n-state {
|
||||
pins = "gpio65";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ts_rst_n: ts-rst-n-state {
|
||||
pins = "gpio71";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
ts_int_n: ts-int-n-state {
|
||||
pins = "gpio80";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mdss_dsi_n: mdss-dsi-n-state {
|
||||
pins = "gpio82";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
hall_sensor_n: hall-sensor-n-state {
|
||||
pins = "gpio96";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
@@ -233,10 +539,8 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3 {
|
||||
/delete-property/ usb-role-switch;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "peripheral";
|
||||
&usb_dwc3_hs {
|
||||
remote-endpoint = <&pmi632_hs_in>;
|
||||
};
|
||||
|
||||
&usb_hsphy {
|
||||
@@ -246,6 +550,27 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_qmpphy {
|
||||
vdda-phy-supply = <&pm6125_l4a>;
|
||||
vdda-pll-supply = <&pm6125_l12a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_qmpphy_out {
|
||||
remote-endpoint = <&pmi632_ss_in>;
|
||||
};
|
||||
|
||||
&wifi {
|
||||
vdd-0.8-cx-mx-supply = <&pm6125_l8a>;
|
||||
vdd-1.8-xo-supply = <&pm6125_l16a>;
|
||||
vdd-1.3-rfa-supply = <&pm6125_l17a>;
|
||||
vdd-3.3-ch0-supply = <&pm6125_l23a>;
|
||||
|
||||
qcom,ath10k-calibration-variant = "Fxtec_QX1050";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xo_board {
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
@@ -376,7 +376,7 @@
|
||||
mboxes = <&apcs_glb 0>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-sm6115";
|
||||
compatible = "qcom,rpm-sm6115", "qcom,glink-smd-rpm";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -192,7 +192,7 @@
|
||||
mboxes = <&apcs_glb 0>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-sm6125";
|
||||
compatible = "qcom,rpm-sm6125", "qcom,glink-smd-rpm";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -653,7 +653,7 @@
|
||||
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
||||
|
||||
rpm_requests: rpm-requests {
|
||||
compatible = "qcom,rpm-sm6375";
|
||||
compatible = "qcom,rpm-sm6375", "qcom,glink-smd-rpm";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
|
||||
@@ -411,6 +411,8 @@
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
reset-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vcc-supply = <&vreg_l19a_3p0>;
|
||||
vcc-max-microamp = <600000>;
|
||||
vccq2-supply = <&vreg_l12a_1p8>;
|
||||
|
||||
@@ -355,11 +355,6 @@
|
||||
};
|
||||
|
||||
&gpu {
|
||||
/*
|
||||
* NOTE: "amd,imageon" makes Adreno start in headless mode, remove it
|
||||
* after display support is added on this board.
|
||||
*/
|
||||
compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -17,6 +17,7 @@
|
||||
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
|
||||
#include <dt-bindings/interconnect/qcom,osm-l3.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,sm8150-camcc.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
@@ -3759,6 +3760,18 @@
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
camcc: clock-controller@ad00000 {
|
||||
compatible = "qcom,sm8150-camcc";
|
||||
reg = <0 0x0ad00000 0 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
mdss: display-subsystem@ae00000 {
|
||||
compatible = "qcom,sm8150-mdss";
|
||||
reg = <0 0x0ae00000 0 0x1000>;
|
||||
|
||||
@@ -8,8 +8,6 @@
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
|
||||
#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
|
||||
#include <dt-bindings/dma/qcom-gpi.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,osm-l3.h>
|
||||
@@ -2633,14 +2631,13 @@
|
||||
wsamacro: codec@3240000 {
|
||||
compatible = "qcom,sm8250-lpass-wsa-macro";
|
||||
reg = <0 0x03240000 0 0x1000>;
|
||||
clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
|
||||
<&audiocc LPASS_CDC_WSA_NPL>,
|
||||
clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&aoncc LPASS_CDC_VA_MCLK>,
|
||||
<&vamacro>;
|
||||
|
||||
clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
|
||||
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mclk";
|
||||
@@ -2674,20 +2671,10 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audiocc: clock-controller@3300000 {
|
||||
compatible = "qcom,sm8250-lpass-audiocc";
|
||||
reg = <0 0x03300000 0 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
||||
clock-names = "core", "audio", "bus";
|
||||
};
|
||||
|
||||
vamacro: codec@3370000 {
|
||||
compatible = "qcom,sm8250-lpass-va-macro";
|
||||
reg = <0 0x03370000 0 0x1000>;
|
||||
clocks = <&aoncc LPASS_CDC_VA_MCLK>,
|
||||
clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
||||
|
||||
@@ -2792,16 +2779,6 @@
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
aoncc: clock-controller@3380000 {
|
||||
compatible = "qcom,sm8250-lpass-aoncc";
|
||||
reg = <0 0x03380000 0 0x40000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
||||
clock-names = "core", "audio", "bus";
|
||||
};
|
||||
|
||||
lpass_tlmm: pinctrl@33c0000 {
|
||||
compatible = "qcom,sm8250-lpass-lpi-pinctrl";
|
||||
reg = <0 0x033c0000 0x0 0x20000>,
|
||||
|
||||
@@ -2251,6 +2251,12 @@
|
||||
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
||||
};
|
||||
|
||||
refgen: regulator@88e7000 {
|
||||
compatible = "qcom,sm8350-refgen-regulator",
|
||||
"qcom,sm8250-refgen-regulator";
|
||||
reg = <0x0 0x088e7000 0x0 0x84>;
|
||||
};
|
||||
|
||||
usb_1_qmpphy: phy@88e8000 {
|
||||
compatible = "qcom,sm8350-qmp-usb3-dp-phy";
|
||||
reg = <0 0x088e8000 0 0x3000>;
|
||||
@@ -2490,8 +2496,12 @@
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
|
||||
interconnect-names = "mdp0-mem",
|
||||
"mdp1-mem",
|
||||
"cpu-cfg";
|
||||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
|
||||
@@ -2706,6 +2716,7 @@
|
||||
|
||||
operating-points-v2 = <&dsi0_opp_table>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
refgen-supply = <&refgen>;
|
||||
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
|
||||
@@ -2804,6 +2815,7 @@
|
||||
|
||||
operating-points-v2 = <&dsi1_opp_table>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
refgen-supply = <&refgen>;
|
||||
|
||||
phys = <&mdss_dsi1_phy>;
|
||||
|
||||
|
||||
@@ -279,6 +279,65 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcn7850-pmu {
|
||||
compatible = "qcom,wcn7850-pmu";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>;
|
||||
|
||||
wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
|
||||
bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vdd-supply = <&vreg_s5g_0p85>;
|
||||
vddio-supply = <&vreg_l15b_1p8>;
|
||||
vddaon-supply = <&vreg_s2g_0p85>;
|
||||
vdddig-supply = <&vreg_s4e_0p95>;
|
||||
vddrfa1p2-supply = <&vreg_s4g_1p25>;
|
||||
vddrfa1p8-supply = <&vreg_s6g_1p86>;
|
||||
|
||||
regulators {
|
||||
vreg_pmu_rfa_cmn: ldo0 {
|
||||
regulator-name = "vreg_pmu_rfa_cmn";
|
||||
};
|
||||
|
||||
vreg_pmu_aon_0p59: ldo1 {
|
||||
regulator-name = "vreg_pmu_aon_0p59";
|
||||
};
|
||||
|
||||
vreg_pmu_wlcx_0p8: ldo2 {
|
||||
regulator-name = "vreg_pmu_wlcx_0p8";
|
||||
};
|
||||
|
||||
vreg_pmu_wlmx_0p85: ldo3 {
|
||||
regulator-name = "vreg_pmu_wlmx_0p85";
|
||||
};
|
||||
|
||||
vreg_pmu_btcmx_0p85: ldo4 {
|
||||
regulator-name = "vreg_pmu_btcmx_0p85";
|
||||
};
|
||||
|
||||
vreg_pmu_rfa_0p8: ldo5 {
|
||||
regulator-name = "vreg_pmu_rfa_0p8";
|
||||
};
|
||||
|
||||
vreg_pmu_rfa_1p2: ldo6 {
|
||||
regulator-name = "vreg_pmu_rfa_1p2";
|
||||
};
|
||||
|
||||
vreg_pmu_rfa_1p8: ldo7 {
|
||||
regulator-name = "vreg_pmu_rfa_1p8";
|
||||
};
|
||||
|
||||
vreg_pmu_pcie_0p9: ldo8 {
|
||||
regulator-name = "vreg_pmu_pcie_0p9";
|
||||
};
|
||||
|
||||
vreg_pmu_pcie_1p8: ldo9 {
|
||||
regulator-name = "vreg_pmu_pcie_1p8";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
@@ -953,6 +1012,23 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcieport0 {
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
||||
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
|
||||
vddaon-supply = <&vreg_pmu_aon_0p59>;
|
||||
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
|
||||
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
|
||||
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
|
||||
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
|
||||
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
|
||||
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0_phy {
|
||||
vdda-phy-supply = <&vreg_l1e_0p88>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
@@ -1041,6 +1117,17 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmk8550_gpios {
|
||||
pmk8550_sleep_clk: sleep-clk-state {
|
||||
pins = "gpio3";
|
||||
function = "func1";
|
||||
input-disable;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
power-source = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1203,6 +1290,13 @@
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
|
||||
wlan_en: wlan-en-state {
|
||||
pins = "gpio80";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
@@ -1215,20 +1309,15 @@
|
||||
bluetooth {
|
||||
compatible = "qcom,wcn7850-bt";
|
||||
|
||||
vddio-supply = <&vreg_l15b_1p8>;
|
||||
vddaon-supply = <&vreg_s4e_0p95>;
|
||||
vdddig-supply = <&vreg_s4e_0p95>;
|
||||
vddrfa0p8-supply = <&vreg_s4e_0p95>;
|
||||
vddrfa1p2-supply = <&vreg_s4g_1p25>;
|
||||
vddrfa1p9-supply = <&vreg_s6g_1p86>;
|
||||
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
|
||||
vddaon-supply = <&vreg_pmu_aon_0p59>;
|
||||
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
|
||||
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
|
||||
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
|
||||
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
|
||||
|
||||
max-speed = <3200000>;
|
||||
|
||||
enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
|
||||
swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&bt_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -219,13 +219,10 @@
|
||||
compatible = "qcom,wcn7850-pmu";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wlan_en>, <&pmk8550_sleep_clk>;
|
||||
pinctrl-0 = <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>;
|
||||
|
||||
wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
|
||||
/*
|
||||
* TODO Add bt-enable-gpios once the Bluetooth driver is
|
||||
* converted to using the power sequencer.
|
||||
*/
|
||||
bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vdd-supply = <&vreg_s5g_0p85>;
|
||||
vddio-supply = <&vreg_l15b_1p8>;
|
||||
@@ -1175,20 +1172,15 @@
|
||||
bluetooth {
|
||||
compatible = "qcom,wcn7850-bt";
|
||||
|
||||
vddio-supply = <&vreg_l15b_1p8>;
|
||||
vddaon-supply = <&vreg_s4e_0p95>;
|
||||
vdddig-supply = <&vreg_s4e_0p95>;
|
||||
vddrfa0p8-supply = <&vreg_s4e_0p95>;
|
||||
vddrfa1p2-supply = <&vreg_s4g_1p25>;
|
||||
vddrfa1p9-supply = <&vreg_s6g_1p86>;
|
||||
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
|
||||
vddaon-supply = <&vreg_pmu_aon_0p59>;
|
||||
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
|
||||
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
|
||||
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
|
||||
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
|
||||
|
||||
max-speed = <3200000>;
|
||||
|
||||
enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
|
||||
swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&bt_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -2747,6 +2747,98 @@
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
cci0: cci@ac15000 {
|
||||
compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
|
||||
reg = <0 0x0ac15000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CCI_0_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cci";
|
||||
pinctrl-0 = <&cci0_0_default &cci0_1_default>;
|
||||
pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cci0_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cci0_i2c1: i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cci1: cci@ac16000 {
|
||||
compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
|
||||
reg = <0 0x0ac16000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CCI_1_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cci";
|
||||
pinctrl-0 = <&cci1_0_default>;
|
||||
pinctrl-1 = <&cci1_0_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cci1_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cci2: cci@ac17000 {
|
||||
compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
|
||||
reg = <0 0x0ac17000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CCI_2_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cci";
|
||||
pinctrl-0 = <&cci2_0_default &cci2_1_default>;
|
||||
pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cci2_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cci2_i2c1: i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
camcc: clock-controller@ade0000 {
|
||||
compatible = "qcom,sm8550-camcc";
|
||||
reg = <0 0x0ade0000 0 0x20000>;
|
||||
@@ -3393,6 +3485,166 @@
|
||||
gpio-ranges = <&tlmm 0 0 211>;
|
||||
wakeup-parent = <&pdc>;
|
||||
|
||||
cci0_0_default: cci0-0-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio110";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio111";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci0_0_sleep: cci0-0-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio110";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio111";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
cci0_1_default: cci0-1-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio112";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio113";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci0_1_sleep: cci0-1-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio112";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio113";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
cci1_0_default: cci1-0-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio114";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio115";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci1_0_sleep: cci1-0-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio114";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio115";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
cci2_0_default: cci2-0-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio74";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio75";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci2_0_sleep: cci2-0-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio74";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio75";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
cci2_1_default: cci2-1-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio0";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio1";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci2_1_sleep: cci2-1-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio0";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio1";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
|
||||
/* SDA, SCL */
|
||||
pins = "gpio16", "gpio17";
|
||||
|
||||
@@ -271,13 +271,10 @@
|
||||
compatible = "qcom,wcn7850-pmu";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wlan_en>;
|
||||
pinctrl-0 = <&wlan_en>, <&bt_default>;
|
||||
|
||||
wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
|
||||
/*
|
||||
* TODO Add bt-enable-gpios once the Bluetooth driver is
|
||||
* converted to using the power sequencer.
|
||||
*/
|
||||
bt-enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vdd-supply = <&vreg_s4i_0p85>;
|
||||
vddio-supply = <&vreg_l15b_1p8>;
|
||||
@@ -1272,20 +1269,15 @@
|
||||
bluetooth {
|
||||
compatible = "qcom,wcn7850-bt";
|
||||
|
||||
vddio-supply = <&vreg_l3c_1p2>;
|
||||
vddaon-supply = <&vreg_l15b_1p8>;
|
||||
vdddig-supply = <&vreg_s3c_0p9>;
|
||||
vddrfa0p8-supply = <&vreg_s3c_0p9>;
|
||||
vddrfa1p2-supply = <&vreg_s1c_1p2>;
|
||||
vddrfa1p9-supply = <&vreg_s6c_1p8>;
|
||||
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
|
||||
vddaon-supply = <&vreg_pmu_aon_0p59>;
|
||||
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
|
||||
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
|
||||
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
|
||||
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
|
||||
|
||||
max-speed = <3200000>;
|
||||
|
||||
enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
|
||||
swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&bt_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -208,13 +208,10 @@
|
||||
compatible = "qcom,wcn7850-pmu";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wlan_en>;
|
||||
pinctrl-0 = <&wlan_en>, <&bt_default>;
|
||||
|
||||
wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
|
||||
/*
|
||||
* TODO Add bt-enable-gpios once the Bluetooth driver is
|
||||
* converted to using the power sequencer.
|
||||
*/
|
||||
bt-enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vdd-supply = <&vreg_s4i_0p85>;
|
||||
vddio-supply = <&vreg_l15b_1p8>;
|
||||
@@ -1255,22 +1252,15 @@
|
||||
bluetooth {
|
||||
compatible = "qcom,wcn7850-bt";
|
||||
|
||||
clocks = <&rpmhcc RPMH_RF_CLK1>;
|
||||
|
||||
vddio-supply = <&vreg_l3c_1p2>;
|
||||
vddaon-supply = <&vreg_l15b_1p8>;
|
||||
vdddig-supply = <&vreg_s3c_0p9>;
|
||||
vddrfa0p8-supply = <&vreg_s3c_0p9>;
|
||||
vddrfa1p2-supply = <&vreg_s1c_1p2>;
|
||||
vddrfa1p9-supply = <&vreg_s6c_1p8>;
|
||||
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
|
||||
vddaon-supply = <&vreg_pmu_aon_0p59>;
|
||||
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
|
||||
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
|
||||
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
|
||||
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
|
||||
|
||||
max-speed = <3200000>;
|
||||
|
||||
enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
|
||||
swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&bt_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -3329,6 +3329,105 @@
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
cci0: cci@ac15000 {
|
||||
compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
|
||||
reg = <0 0x0ac15000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CCI_0_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cci";
|
||||
pinctrl-0 = <&cci0_0_default &cci0_1_default>;
|
||||
pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cci0_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cci0_i2c1: i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cci1: cci@ac16000 {
|
||||
compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
|
||||
reg = <0 0x0ac16000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CCI_1_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cci";
|
||||
pinctrl-0 = <&cci1_0_default &cci1_1_default>;
|
||||
pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cci1_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cci1_i2c1: i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cci2: cci@ac17000 {
|
||||
compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
|
||||
reg = <0 0x0ac17000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CCI_2_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cci";
|
||||
pinctrl-0 = <&cci2_0_default &cci2_1_default>;
|
||||
pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cci2_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cci2_i2c1: i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
camcc: clock-controller@ade0000 {
|
||||
compatible = "qcom,sm8650-camcc";
|
||||
reg = <0 0x0ade0000 0 0x20000>;
|
||||
@@ -4029,6 +4128,198 @@
|
||||
|
||||
wakeup-parent = <&pdc>;
|
||||
|
||||
cci0_0_default: cci0-0-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio113";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio114";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci0_0_sleep: cci0-0-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio113";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio114";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
cci0_1_default: cci0-1-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio115";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio116";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci0_1_sleep: cci0-1-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio115";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio116";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
cci1_0_default: cci1-0-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio117";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio118";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci1_0_sleep: cci1-0-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio117";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio118";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
cci1_1_default: cci1-1-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio12";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio13";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci1_1_sleep: cci1-1-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio12";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio13";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
cci2_0_default: cci2-0-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio112";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio153";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci2_0_sleep: cci2-0-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio112";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio153";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
cci2_1_default: cci2-1-default-state {
|
||||
sda-pins {
|
||||
pins = "gpio119";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio120";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
cci2_1_sleep: cci2-1-sleep-state {
|
||||
sda-pins {
|
||||
pins = "gpio119";
|
||||
function = "cci_i2c_sda";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
scl-pins {
|
||||
pins = "gpio120";
|
||||
function = "cci_i2c_scl";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
|
||||
/* SDA, SCL */
|
||||
pins = "gpio64", "gpio65";
|
||||
|
||||
@@ -0,0 +1,807 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2024, Linaro Limited
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/gpio-keys.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
|
||||
#include "x1e80100.dtsi"
|
||||
#include "x1e80100-pmics.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Lenovo ThinkPad T14s Gen 6";
|
||||
compatible = "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100";
|
||||
chassis-type = "laptop";
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&hall_int_n_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
switch-lid {
|
||||
gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <EV_SW>;
|
||||
linux,code = <SW_LID>;
|
||||
wakeup-source;
|
||||
wakeup-event-action = <EV_ACT_DEASSERTED>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic-glink {
|
||||
compatible = "qcom,x1e80100-pmic-glink",
|
||||
"qcom,sm8550-pmic-glink",
|
||||
"qcom,pmic-glink";
|
||||
orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
|
||||
<&tlmm 123 GPIO_ACTIVE_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Display-adjacent port */
|
||||
connector@0 {
|
||||
compatible = "usb-c-connector";
|
||||
reg = <0>;
|
||||
power-role = "dual";
|
||||
data-role = "dual";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
pmic_glink_ss0_hs_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss0_dwc3_hs>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
pmic_glink_ss0_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* User-adjacent port */
|
||||
connector@1 {
|
||||
compatible = "usb-c-connector";
|
||||
reg = <1>;
|
||||
power-role = "dual";
|
||||
data-role = "dual";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
pmic_glink_ss1_hs_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss1_dwc3_hs>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
pmic_glink_ss1_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0x0 0x8000000>;
|
||||
reusable;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
vreg_edp_3p3: regulator-edp-3p3 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_EDP_3P3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&edp_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_nvme: regulator-nvme {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_NVME_3P3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&nvme_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
vph_pwr: regulator-vph-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
regulators-0 {
|
||||
compatible = "qcom,pm8550-rpmh-regulators";
|
||||
qcom,pmic-id = "b";
|
||||
|
||||
vdd-bob1-supply = <&vph_pwr>;
|
||||
vdd-bob2-supply = <&vph_pwr>;
|
||||
vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
|
||||
vdd-l2-l13-l14-supply = <&vreg_bob1>;
|
||||
vdd-l5-l16-supply = <&vreg_bob1>;
|
||||
vdd-l6-l7-supply = <&vreg_bob2>;
|
||||
vdd-l8-l9-supply = <&vreg_bob1>;
|
||||
vdd-l12-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l15-supply = <&vreg_s4c_1p8>;
|
||||
vdd-l17-supply = <&vreg_bob2>;
|
||||
|
||||
vreg_bob1: bob1 {
|
||||
regulator-name = "vreg_bob1";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_bob2: bob2 {
|
||||
regulator-name = "vreg_bob2";
|
||||
regulator-min-microvolt = <2504000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2b_3p0: ldo2 {
|
||||
regulator-name = "vreg_l2b_3p0";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4b_1p8: ldo4 {
|
||||
regulator-name = "vreg_l4b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6b_1p8: ldo6 {
|
||||
regulator-name = "vreg_l6b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8b_3p0: ldo8 {
|
||||
regulator-name = "vreg_l8b_3p0";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9b_2p9: ldo9 {
|
||||
regulator-name = "vreg_l9b_2p9";
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10b_1p8: ldo10 {
|
||||
regulator-name = "vreg_l10b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l12b_1p2: ldo12 {
|
||||
regulator-name = "vreg_l12b_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13b_3p0: ldo13 {
|
||||
regulator-name = "vreg_l13b_3p0";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l14b_3p0: ldo14 {
|
||||
regulator-name = "vreg_l14b_3p0";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l15b_1p8: ldo15 {
|
||||
regulator-name = "vreg_l15b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l17b_2p5: ldo17 {
|
||||
regulator-name = "vreg_l17b_2p5";
|
||||
regulator-min-microvolt = <2504000>;
|
||||
regulator-max-microvolt = <2504000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-1 {
|
||||
compatible = "qcom,pm8550ve-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-l1-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l2-supply = <&vreg_s1f_0p7>;
|
||||
vdd-l3-supply = <&vreg_s1f_0p7>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s4c_1p8: smps4 {
|
||||
regulator-name = "vreg_s4c_1p8";
|
||||
regulator-min-microvolt = <1856000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1c_1p2: ldo1 {
|
||||
regulator-name = "vreg_l1c_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2c_0p8: ldo2 {
|
||||
regulator-name = "vreg_l2c_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3c_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3c_0p8";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-2 {
|
||||
compatible = "qcom,pmc8380-rpmh-regulators";
|
||||
qcom,pmic-id = "d";
|
||||
|
||||
vdd-l1-supply = <&vreg_s1f_0p7>;
|
||||
vdd-l2-supply = <&vreg_s1f_0p7>;
|
||||
vdd-l3-supply = <&vreg_s4c_1p8>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
|
||||
vreg_l1d_0p8: ldo1 {
|
||||
regulator-name = "vreg_l1d_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2d_0p9: ldo2 {
|
||||
regulator-name = "vreg_l2d_0p9";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3d_1p8: ldo3 {
|
||||
regulator-name = "vreg_l3d_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-3 {
|
||||
compatible = "qcom,pmc8380-rpmh-regulators";
|
||||
qcom,pmic-id = "e";
|
||||
|
||||
vdd-l2-supply = <&vreg_s1f_0p7>;
|
||||
vdd-l3-supply = <&vreg_s5j_1p2>;
|
||||
|
||||
vreg_l2e_0p8: ldo2 {
|
||||
regulator-name = "vreg_l2e_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3e_1p2: ldo3 {
|
||||
regulator-name = "vreg_l3e_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-4 {
|
||||
compatible = "qcom,pmc8380-rpmh-regulators";
|
||||
qcom,pmic-id = "f";
|
||||
|
||||
vdd-l1-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l2-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l3-supply = <&vreg_s5j_1p2>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s1f_0p7: smps1 {
|
||||
regulator-name = "vreg_s1f_0p7";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-6 {
|
||||
compatible = "qcom,pm8550ve-rpmh-regulators";
|
||||
qcom,pmic-id = "i";
|
||||
|
||||
vdd-l1-supply = <&vreg_s4c_1p8>;
|
||||
vdd-l2-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l3-supply = <&vreg_s1f_0p7>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
|
||||
vreg_l1i_1p8: ldo1 {
|
||||
regulator-name = "vreg_l1i_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2i_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2i_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3i_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3i_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-7 {
|
||||
compatible = "qcom,pm8550ve-rpmh-regulators";
|
||||
qcom,pmic-id = "j";
|
||||
|
||||
vdd-l1-supply = <&vreg_s1f_0p7>;
|
||||
vdd-l2-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l3-supply = <&vreg_s1f_0p7>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s5j_1p2: smps5 {
|
||||
regulator-name = "vreg_s5j_1p2";
|
||||
regulator-min-microvolt = <1256000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1j_0p8: ldo1 {
|
||||
regulator-name = "vreg_l1j_0p8";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2j_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2j_1p2";
|
||||
regulator-min-microvolt = <1256000>;
|
||||
regulator-max-microvolt = <1256000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3j_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3j_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
|
||||
zap-shader {
|
||||
firmware-name = "qcom/x1e80100/LENOVO/21N1/qcdxkmsuc8380.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* ELAN06E2 or ELAN06E3 */
|
||||
touchpad@15 {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x15>;
|
||||
|
||||
hid-descr-addr = <0x1>;
|
||||
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-0 = <&tpad_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
/* TODO: second-sourced SYNA8022 or SYNA8024 touchpad @ 0x2c */
|
||||
|
||||
/* ELAN06F1 or SYNA06F2 */
|
||||
keyboard@3a {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x3a>;
|
||||
|
||||
hid-descr-addr = <0x1>;
|
||||
interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-0 = <&kybd_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* ILIT2911 or GTCH1563 */
|
||||
touchscreen@10 {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x10>;
|
||||
|
||||
hid-descr-addr = <0x1>;
|
||||
interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-0 = <&ts0_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
/* TODO: second-sourced touchscreen @ 0x41 */
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp3 {
|
||||
compatible = "qcom,x1e80100-dp";
|
||||
/delete-property/ #sound-dai-cells;
|
||||
|
||||
status = "okay";
|
||||
|
||||
aux-bus {
|
||||
panel {
|
||||
compatible = "edp-panel";
|
||||
enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <&vreg_edp_3p3>;
|
||||
|
||||
pinctrl-0 = <&edp_bl_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
edp_panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dp3_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mdss_dp3_out: endpoint {
|
||||
data-lanes = <0 1 2 3>;
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
|
||||
remote-endpoint = <&edp_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dp3_phy {
|
||||
vdda-phy-supply = <&vreg_l3j_0p8>;
|
||||
vdda-pll-supply = <&vreg_l2j_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_phy {
|
||||
vdda-phy-supply = <&vreg_l1d_0p8>;
|
||||
vdda-pll-supply = <&vreg_l2j_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmc8380_3_gpios {
|
||||
edp_bl_en: edp-bl-en-state {
|
||||
pins = "gpio4";
|
||||
function = "normal";
|
||||
power-source = <1>;
|
||||
input-disable;
|
||||
output-enable;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/x1e80100/LENOVO/21N1/qcadsp8380.mbn",
|
||||
"qcom/x1e80100/LENOVO/21N1/adsp_dtbs.elf";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
firmware-name = "qcom/x1e80100/LENOVO/21N1/qccdsp8380.mbn",
|
||||
"qcom/x1e80100/LENOVO/21N1/cdsp_dtbs.elf";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&smb2360_0_eusb2_repeater {
|
||||
vdd18-supply = <&vreg_l3d_1p8>;
|
||||
vdd3-supply = <&vreg_l2b_3p0>;
|
||||
};
|
||||
|
||||
&smb2360_1_eusb2_repeater {
|
||||
vdd18-supply = <&vreg_l3d_1p8>;
|
||||
vdd3-supply = <&vreg_l14b_3p0>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <34 2>, /* Unused */
|
||||
<44 4>, /* SPI (TPM) */
|
||||
<72 2>, /* Secure EC I2C connection (?) */
|
||||
<238 1>; /* UFS Reset */
|
||||
|
||||
tpad_default: tpad-default-state {
|
||||
pins = "gpio3";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
nvme_reg_en: nvme-reg-en-state {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ts0_default: ts0-default-state {
|
||||
reset-n-pins {
|
||||
pins = "gpio48";
|
||||
function = "gpio";
|
||||
output-high;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
int-n-pins {
|
||||
pins = "gpio51";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
kybd_default: kybd-default-state {
|
||||
pins = "gpio67";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
edp_reg_en: edp-reg-en-state {
|
||||
pins = "gpio70";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
hall_int_n_default: hall-int-n-state {
|
||||
pins = "gpio92";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
wcd_default: wcd-reset-n-active-state {
|
||||
pins = "gpio191";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
&usb_1_ss0_hsphy {
|
||||
vdd-supply = <&vreg_l3j_0p8>;
|
||||
vdda12-supply = <&vreg_l2j_1p2>;
|
||||
|
||||
phys = <&smb2360_0_eusb2_repeater>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss0_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l3e_1p2>;
|
||||
vdda-pll-supply = <&vreg_l1j_0p8>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss0_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb_1_ss0_dwc3_hs {
|
||||
remote-endpoint = <&pmic_glink_ss0_hs_in>;
|
||||
};
|
||||
|
||||
&usb_1_ss0_qmpphy_out {
|
||||
remote-endpoint = <&pmic_glink_ss0_ss_in>;
|
||||
};
|
||||
|
||||
&usb_1_ss1_hsphy {
|
||||
vdd-supply = <&vreg_l3j_0p8>;
|
||||
vdda12-supply = <&vreg_l2j_1p2>;
|
||||
|
||||
phys = <&smb2360_1_eusb2_repeater>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss1_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l3e_1p2>;
|
||||
vdda-pll-supply = <&vreg_l2d_0p9>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss1_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb_1_ss1_dwc3_hs {
|
||||
remote-endpoint = <&pmic_glink_ss1_hs_in>;
|
||||
};
|
||||
|
||||
&usb_1_ss1_qmpphy_out {
|
||||
remote-endpoint = <&pmic_glink_ss1_ss_in>;
|
||||
};
|
||||
@@ -278,6 +278,13 @@
|
||||
vdd-l3-supply = <&vreg_s1f_0p7>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
|
||||
vreg_l3i_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3i_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-7 {
|
||||
@@ -423,11 +430,17 @@
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3j_0p8>;
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
@@ -488,10 +501,6 @@
|
||||
vdd3-supply = <&vreg_l14b_3p0>;
|
||||
};
|
||||
|
||||
&smb2360_2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <34 2>, /* Unused */
|
||||
<44 4>, /* SPI (TPM) */
|
||||
@@ -517,7 +526,30 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie6a_default: pcie2a-default-state {
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
@@ -529,7 +561,7 @@
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
|
||||
@@ -6,6 +6,8 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/gpio-keys.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
|
||||
#include "x1e80100.dtsi"
|
||||
@@ -49,6 +51,21 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&hall_int_n_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
switch-lid {
|
||||
gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <EV_SW>;
|
||||
linux,code = <SW_LID>;
|
||||
wakeup-source;
|
||||
wakeup-event-action = <EV_ACT_DEASSERTED>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic-glink {
|
||||
compatible = "qcom,x1e80100-pmic-glink",
|
||||
"qcom,sm8550-pmic-glink",
|
||||
@@ -285,6 +302,22 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nvme_reg_en>;
|
||||
};
|
||||
|
||||
vreg_wwan: regulator-wwan {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDX_VPH_PWR";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&wwan_sw_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
@@ -756,11 +789,36 @@
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3j_0p8>;
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie5 {
|
||||
perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddpe-3v3-supply = <&vreg_wwan>;
|
||||
|
||||
pinctrl-0 = <&pcie5_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie5_phy {
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
@@ -821,6 +879,10 @@
|
||||
vdd3-supply = <&vreg_l14b_3p0>;
|
||||
};
|
||||
|
||||
&smb2360_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&smb2360_2_eusb2_repeater {
|
||||
vdd18-supply = <&vreg_l3d_1p8>;
|
||||
vdd3-supply = <&vreg_l8b_3p0>;
|
||||
@@ -841,6 +903,7 @@
|
||||
sound-name-prefix = "WooferLeft";
|
||||
vdd-1p8-supply = <&vreg_l15b_1p8>;
|
||||
vdd-io-supply = <&vreg_l12b_1p2>;
|
||||
qcom,port-mapping = <1 2 3 7 10 13>;
|
||||
};
|
||||
|
||||
/* WSA8845, Left Tweeter */
|
||||
@@ -852,6 +915,7 @@
|
||||
sound-name-prefix = "TwitterLeft";
|
||||
vdd-1p8-supply = <&vreg_l15b_1p8>;
|
||||
vdd-io-supply = <&vreg_l12b_1p2>;
|
||||
qcom,port-mapping = <4 5 6 7 11 13>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -892,6 +956,7 @@
|
||||
sound-name-prefix = "WooferRight";
|
||||
vdd-1p8-supply = <&vreg_l15b_1p8>;
|
||||
vdd-io-supply = <&vreg_l12b_1p2>;
|
||||
qcom,port-mapping = <1 2 3 7 10 13>;
|
||||
};
|
||||
|
||||
/* WSA8845, Right Tweeter */
|
||||
@@ -903,6 +968,7 @@
|
||||
sound-name-prefix = "TwitterRight";
|
||||
vdd-1p8-supply = <&vreg_l15b_1p8>;
|
||||
vdd-io-supply = <&vreg_l12b_1p2>;
|
||||
qcom,port-mapping = <4 5 6 7 11 13>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -918,6 +984,12 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
hall_int_n_default: hall-int-n-state {
|
||||
pins = "gpio92";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
kybd_default: kybd-default-state {
|
||||
pins = "gpio67";
|
||||
function = "gpio";
|
||||
@@ -931,7 +1003,53 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie6a_default: pcie2a-default-state {
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie5_default: pcie5-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio150";
|
||||
function = "pcie5_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio149";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio151";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
@@ -943,15 +1061,15 @@
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
tpad_default: tpad-default-state {
|
||||
@@ -982,6 +1100,13 @@
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
|
||||
wwan_sw_en: wwan-sw-en-state {
|
||||
pins = "gpio221";
|
||||
function = "gpio";
|
||||
drive-strength = <4>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&uart21 {
|
||||
|
||||
@@ -190,7 +190,6 @@
|
||||
pinctrl-0 = <&edp_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
@@ -592,9 +591,13 @@
|
||||
|
||||
aux-bus {
|
||||
panel {
|
||||
compatible = "edp-panel";
|
||||
compatible = "samsung,atna45dc02", "samsung,atna33xc20";
|
||||
enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <&vreg_edp_3p3>;
|
||||
|
||||
pinctrl-0 = <&edp_bl_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
edp_panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dp3_out>;
|
||||
@@ -625,16 +628,31 @@
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3j_0p8>;
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
||||
qcom,ath12k-calibration-variant = "LES790";
|
||||
};
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
@@ -654,6 +672,16 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmc8380_3_gpios {
|
||||
edp_bl_en: edp-bl-en-state {
|
||||
pins = "gpio4";
|
||||
function = "normal";
|
||||
power-source = <0>;
|
||||
input-disable;
|
||||
output-enable;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -689,6 +717,10 @@
|
||||
vdd3-supply = <&vreg_l14b_3p0>;
|
||||
};
|
||||
|
||||
&smb2360_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&smb2360_2_eusb2_repeater {
|
||||
vdd18-supply = <&vreg_l3d_1p8>;
|
||||
vdd3-supply = <&vreg_l8b_3p0>;
|
||||
@@ -782,7 +814,30 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie6a_default: pcie2a-default-state {
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
@@ -794,15 +849,15 @@
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
tpad_default: tpad-default-state {
|
||||
|
||||
@@ -0,0 +1,835 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
|
||||
#include "x1e80100.dtsi"
|
||||
#include "x1e80100-pmics.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart2;
|
||||
i2c0 = &i2c0;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c7 = &i2c7;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pmk8550_pwm 0 5000000>;
|
||||
enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
|
||||
/* TODO: power-supply? */
|
||||
|
||||
pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cam_indicator_en>;
|
||||
|
||||
led-camera-indicator {
|
||||
label = "white:camera-indicator";
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
gpios = <&tlmm 225 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "none";
|
||||
default-state = "off";
|
||||
/* Reuse as a panic indicator until we get a "camera on" trigger */
|
||||
panic-indicator;
|
||||
};
|
||||
};
|
||||
|
||||
pmic-glink {
|
||||
compatible = "qcom,x1e80100-pmic-glink",
|
||||
"qcom,sm8550-pmic-glink",
|
||||
"qcom,pmic-glink";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
|
||||
<&tlmm 123 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* Left-side rear port */
|
||||
connector@0 {
|
||||
compatible = "usb-c-connector";
|
||||
reg = <0>;
|
||||
power-role = "dual";
|
||||
data-role = "dual";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
pmic_glink_ss0_hs_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss0_dwc3_hs>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
pmic_glink_ss0_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Left-side front port */
|
||||
connector@1 {
|
||||
compatible = "usb-c-connector";
|
||||
reg = <1>;
|
||||
power-role = "dual";
|
||||
data-role = "dual";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
pmic_glink_ss1_hs_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss1_dwc3_hs>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
pmic_glink_ss1_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0x0 0x8000000>;
|
||||
reusable;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_edp_3p3: regulator-edp-3p3 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_EDP_3P3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&edp_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vreg_nvme: regulator-nvme {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "VREG_NVME_3P3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-0 = <&nvme_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
regulators-0 {
|
||||
compatible = "qcom,pm8550-rpmh-regulators";
|
||||
qcom,pmic-id = "b";
|
||||
|
||||
vdd-bob1-supply = <&vph_pwr>;
|
||||
vdd-bob2-supply = <&vph_pwr>;
|
||||
vdd-l1-l4-l10-supply = <&vreg_s4c>;
|
||||
vdd-l2-l13-l14-supply = <&vreg_bob1>;
|
||||
vdd-l5-l16-supply = <&vreg_bob1>;
|
||||
vdd-l6-l7-supply = <&vreg_bob2>;
|
||||
vdd-l8-l9-supply = <&vreg_bob1>;
|
||||
vdd-l12-supply = <&vreg_s5j>;
|
||||
vdd-l15-supply = <&vreg_s4c>;
|
||||
vdd-l17-supply = <&vreg_bob2>;
|
||||
|
||||
vreg_bob1: bob1 {
|
||||
regulator-name = "vreg_bob1";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_bob2: bob2 {
|
||||
regulator-name = "vreg_bob2";
|
||||
regulator-min-microvolt = <2504000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1b: ldo1 {
|
||||
regulator-name = "vreg_l1b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2b: ldo2 {
|
||||
regulator-name = "vreg_l2b";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4b: ldo4 {
|
||||
regulator-name = "vreg_l4b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5b: ldo5 {
|
||||
regulator-name = "vreg_l5b";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6b: ldo6 {
|
||||
regulator-name = "vreg_l6b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7b: ldo7 {
|
||||
regulator-name = "vreg_l7b";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8b: ldo8 {
|
||||
regulator-name = "vreg_l8b";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9b: ldo9 {
|
||||
regulator-name = "vreg_l9b";
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10b: ldo10 {
|
||||
regulator-name = "vreg_l10b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l12b: ldo12 {
|
||||
regulator-name = "vreg_l12b";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13b: ldo13 {
|
||||
regulator-name = "vreg_l13b";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l14b: ldo14 {
|
||||
regulator-name = "vreg_l14b";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l15b: ldo15 {
|
||||
regulator-name = "vreg_l15b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l16b: ldo16 {
|
||||
regulator-name = "vreg_l16b";
|
||||
regulator-min-microvolt = <2912000>;
|
||||
regulator-max-microvolt = <2912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l17b: ldo17 {
|
||||
regulator-name = "vreg_l17b";
|
||||
regulator-min-microvolt = <2504000>;
|
||||
regulator-max-microvolt = <2504000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-1 {
|
||||
compatible = "qcom,pm8550ve-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-l1-supply = <&vreg_s5j>;
|
||||
vdd-l2-supply = <&vreg_s1f>;
|
||||
vdd-l3-supply = <&vreg_s1f>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s4c: smps4 {
|
||||
regulator-name = "vreg_s4c";
|
||||
regulator-min-microvolt = <1856000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1c: ldo1 {
|
||||
regulator-name = "vreg_l1c";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2c: ldo2 {
|
||||
regulator-name = "vreg_l2c";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3c: ldo3 {
|
||||
regulator-name = "vreg_l3c";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-2 {
|
||||
compatible = "qcom,pmc8380-rpmh-regulators";
|
||||
qcom,pmic-id = "d";
|
||||
|
||||
vdd-l1-supply = <&vreg_s1f>;
|
||||
vdd-l2-supply = <&vreg_s1f>;
|
||||
vdd-l3-supply = <&vreg_s4c>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
|
||||
vreg_l1d: ldo1 {
|
||||
regulator-name = "vreg_l1d";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2d: ldo2 {
|
||||
regulator-name = "vreg_l2d";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3d: ldo3 {
|
||||
regulator-name = "vreg_l3d";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-3 {
|
||||
compatible = "qcom,pmc8380-rpmh-regulators";
|
||||
qcom,pmic-id = "e";
|
||||
|
||||
vdd-l2-supply = <&vreg_s1f>;
|
||||
vdd-l3-supply = <&vreg_s5j>;
|
||||
|
||||
vreg_l2e: ldo2 {
|
||||
regulator-name = "vreg_l2e";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3e: ldo3 {
|
||||
regulator-name = "vreg_l3e";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-4 {
|
||||
compatible = "qcom,pmc8380-rpmh-regulators";
|
||||
qcom,pmic-id = "f";
|
||||
|
||||
vdd-l1-supply = <&vreg_s5j>;
|
||||
vdd-l2-supply = <&vreg_s5j>;
|
||||
vdd-l3-supply = <&vreg_s5j>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s1f: smps1 {
|
||||
regulator-name = "vreg_s1f";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1f: ldo1 {
|
||||
regulator-name = "vreg_l1f";
|
||||
regulator-min-microvolt = <1024000>;
|
||||
regulator-max-microvolt = <1024000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2f: ldo2 {
|
||||
regulator-name = "vreg_l2f";
|
||||
regulator-min-microvolt = <1024000>;
|
||||
regulator-max-microvolt = <1024000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3f: ldo3 {
|
||||
regulator-name = "vreg_l3f";
|
||||
regulator-min-microvolt = <1024000>;
|
||||
regulator-max-microvolt = <1024000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-6 {
|
||||
compatible = "qcom,pm8550ve-rpmh-regulators";
|
||||
qcom,pmic-id = "i";
|
||||
|
||||
vdd-l1-supply = <&vreg_s4c>;
|
||||
vdd-l2-supply = <&vreg_s5j>;
|
||||
vdd-l3-supply = <&vreg_s1f>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s1i: smps1 {
|
||||
regulator-name = "vreg_s1i";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s2i: smps2 {
|
||||
regulator-name = "vreg_s2i";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1i: ldo1 {
|
||||
regulator-name = "vreg_l1i";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2i: ldo2 {
|
||||
regulator-name = "vreg_l2i";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3i: ldo3 {
|
||||
regulator-name = "vreg_l3i";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-7 {
|
||||
compatible = "qcom,pm8550ve-rpmh-regulators";
|
||||
qcom,pmic-id = "j";
|
||||
|
||||
vdd-l1-supply = <&vreg_s1f>;
|
||||
vdd-l2-supply = <&vreg_s5j>;
|
||||
vdd-l3-supply = <&vreg_s1f>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s5j: smps5 {
|
||||
regulator-name = "vreg_s5j";
|
||||
regulator-min-microvolt = <1256000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1j: ldo1 {
|
||||
regulator-name = "vreg_l1j";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2j: ldo2 {
|
||||
regulator-name = "vreg_l2j";
|
||||
regulator-min-microvolt = <1256000>;
|
||||
regulator-max-microvolt = <1256000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3j: ldo3 {
|
||||
regulator-name = "vreg_l3j";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_microcode_mem>;
|
||||
firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* Something @39, @3e, @44 */
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* PS8830 USB retimer @8 */
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* Something @18, @2c, @2e */
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* Something @4f */
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* PS8830 USB retimer @8 */
|
||||
};
|
||||
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp3 {
|
||||
compatible = "qcom,x1e80100-dp";
|
||||
/delete-property/ #sound-dai-cells;
|
||||
|
||||
status = "okay";
|
||||
|
||||
aux-bus {
|
||||
panel {
|
||||
compatible = "edp-panel";
|
||||
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&vreg_edp_3p3>;
|
||||
|
||||
port {
|
||||
edp_panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dp3_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mdss_dp3_out: endpoint {
|
||||
data-lanes = <0 1 2 3>;
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
|
||||
remote-endpoint = <&edp_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dp3_phy {
|
||||
vdda-phy-supply = <&vreg_l3j>;
|
||||
vdda-pll-supply = <&vreg_l2j>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3i>;
|
||||
vdda-pll-supply = <&vreg_l3e>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_phy {
|
||||
vdda-phy-supply = <&vreg_l1d>;
|
||||
vdda-pll-supply = <&vreg_l2j>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmc8380_3_gpios {
|
||||
edp_bl_en: edp-bl-en-state {
|
||||
pins = "gpio4";
|
||||
function = "normal";
|
||||
power-source = <1>; /* 1.8V */
|
||||
input-disable;
|
||||
output-enable;
|
||||
};
|
||||
};
|
||||
|
||||
&pmk8550_pwm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmk8550_gpios {
|
||||
edp_bl_pwm: edp-bl-pwm-state {
|
||||
pins = "gpio5";
|
||||
function = "func3";
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/x1e80100/microsoft/Romulus/qcadsp8380.mbn",
|
||||
"qcom/x1e80100/microsoft/Romulus/adsp_dtb.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
firmware-name = "qcom/x1e80100/microsoft/Romulus/qccdsp8380.mbn",
|
||||
"qcom/x1e80100/microsoft/Romulus/cdsp_dtb.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&smb2360_0_eusb2_repeater {
|
||||
vdd18-supply = <&vreg_l3d>;
|
||||
vdd3-supply = <&vreg_l2b>;
|
||||
};
|
||||
|
||||
&smb2360_1_eusb2_repeater {
|
||||
vdd18-supply = <&vreg_l3d>;
|
||||
vdd3-supply = <&vreg_l14b>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <44 4>, /* SPI (TPM) */
|
||||
<238 1>; /* UFS Reset */
|
||||
|
||||
nvme_reg_en: nvme-reg-en-state {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
edp_reg_en: edp-reg-en-state {
|
||||
pins = "gpio70";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ssam_state: ssam-state-state {
|
||||
pins = "gpio91";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
perst-n-pins {
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
cam_indicator_en: cam-indicator-en-state {
|
||||
pins = "gpio225";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
|
||||
embedded-controller {
|
||||
compatible = "microsoft,surface-sam";
|
||||
|
||||
interrupts-extended = <&tlmm 91 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
current-speed = <4000000>;
|
||||
|
||||
pinctrl-0 = <&ssam_state>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&usb_1_ss0_hsphy {
|
||||
vdd-supply = <&vreg_l3j>;
|
||||
vdda12-supply = <&vreg_l2j>;
|
||||
|
||||
phys = <&smb2360_0_eusb2_repeater>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss0_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l3e>;
|
||||
vdda-pll-supply = <&vreg_l1j>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss0_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb_1_ss0_dwc3_hs {
|
||||
remote-endpoint = <&pmic_glink_ss0_hs_in>;
|
||||
};
|
||||
|
||||
&usb_1_ss0_qmpphy_out {
|
||||
remote-endpoint = <&pmic_glink_ss0_ss_in>;
|
||||
};
|
||||
|
||||
&usb_1_ss1_hsphy {
|
||||
vdd-supply = <&vreg_l3j>;
|
||||
vdda12-supply = <&vreg_l2j>;
|
||||
|
||||
phys = <&smb2360_1_eusb2_repeater>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss1_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l3e>;
|
||||
vdda-pll-supply = <&vreg_l2d>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss1_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb_1_ss1_dwc3_hs {
|
||||
remote-endpoint = <&pmic_glink_ss1_hs_in>;
|
||||
};
|
||||
|
||||
&usb_1_ss1_qmpphy_out {
|
||||
remote-endpoint = <&pmic_glink_ss1_ss_in>;
|
||||
};
|
||||
@@ -0,0 +1,13 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "x1e80100-microsoft-romulus.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Microsoft Surface Laptop 7 (13.8 inch)";
|
||||
compatible = "microsoft,romulus13", "qcom,x1e80100";
|
||||
};
|
||||
@@ -0,0 +1,13 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "x1e80100-microsoft-romulus.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Microsoft Surface Laptop 7 (15 inch)";
|
||||
compatible = "microsoft,romulus15", "qcom,x1e80100";
|
||||
};
|
||||
@@ -249,6 +249,14 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pmk8550_pwm: pwm {
|
||||
compatible = "qcom,pmk8550-pwm";
|
||||
|
||||
#pwm-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC8380C */
|
||||
@@ -509,6 +517,8 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
smb2360_2_eusb2_repeater: phy@fd00 {
|
||||
compatible = "qcom,smb2360-eusb2-repeater";
|
||||
reg = <0xfd00>;
|
||||
|
||||
@@ -660,11 +660,17 @@
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3j_0p8>;
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
@@ -715,10 +721,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&smb2360_3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&smb2360_0_eusb2_repeater {
|
||||
vdd18-supply = <&vreg_l3d_1p8>;
|
||||
vdd3-supply = <&vreg_l2b_3p0>;
|
||||
@@ -729,11 +731,19 @@
|
||||
vdd3-supply = <&vreg_l14b_3p0>;
|
||||
};
|
||||
|
||||
&smb2360_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&smb2360_2_eusb2_repeater {
|
||||
vdd18-supply = <&vreg_l3d_1p8>;
|
||||
vdd3-supply = <&vreg_l8b_3p0>;
|
||||
};
|
||||
|
||||
&smb2360_3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
|
||||
pinctrl-names = "default";
|
||||
@@ -749,6 +759,7 @@
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
vdd-1p8-supply = <&vreg_l15b_1p8>;
|
||||
vdd-io-supply = <&vreg_l12b_1p2>;
|
||||
qcom,port-mapping = <1 2 3 7 10 13>;
|
||||
};
|
||||
|
||||
/* WSA8845, Right Speaker */
|
||||
@@ -760,6 +771,7 @@
|
||||
sound-name-prefix = "SpkrRight";
|
||||
vdd-1p8-supply = <&vreg_l15b_1p8>;
|
||||
vdd-io-supply = <&vreg_l12b_1p2>;
|
||||
qcom,port-mapping = <4 5 6 7 11 13>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -804,7 +816,30 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie6a_default: pcie2a-default-state {
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
@@ -816,15 +851,15 @@
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
wcd_default: wcd-reset-n-active-state {
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
|
||||
#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
|
||||
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
|
||||
@@ -745,7 +746,7 @@
|
||||
<&sleep_clk>,
|
||||
<0>,
|
||||
<&pcie4_phy>,
|
||||
<0>,
|
||||
<&pcie5_phy>,
|
||||
<&pcie6a_phy>,
|
||||
<0>,
|
||||
<&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
|
||||
@@ -1979,7 +1980,7 @@
|
||||
|
||||
i2c0: i2c@b80000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0xb80000 0 0x4000>;
|
||||
reg = <0 0x00b80000 0 0x4000>;
|
||||
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@@ -2142,9 +2143,31 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@b88000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00b88000 0 0x4000>;
|
||||
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
clock-names = "se";
|
||||
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core",
|
||||
"qup-config";
|
||||
|
||||
pinctrl-0 = <&qup_uart2_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@b88000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0xb88000 0 0x4000>;
|
||||
reg = <0 0x00b88000 0 0x4000>;
|
||||
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@@ -2243,7 +2266,7 @@
|
||||
|
||||
i2c4: i2c@b90000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0xb90000 0 0x4000>;
|
||||
reg = <0 0x00b90000 0 0x4000>;
|
||||
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@@ -2603,6 +2626,8 @@
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <1>;
|
||||
|
||||
orientation-switch;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
@@ -2671,6 +2696,8 @@
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <1>;
|
||||
|
||||
orientation-switch;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
@@ -2739,6 +2766,8 @@
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <1>;
|
||||
|
||||
orientation-switch;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
@@ -2772,7 +2801,7 @@
|
||||
|
||||
cnoc_main: interconnect@1500000 {
|
||||
compatible = "qcom,x1e80100-cnoc-main";
|
||||
reg = <0 0x1500000 0 0x14400>;
|
||||
reg = <0 0x01500000 0 0x14400>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2781,7 +2810,7 @@
|
||||
|
||||
config_noc: interconnect@1600000 {
|
||||
compatible = "qcom,x1e80100-cnoc-cfg";
|
||||
reg = <0 0x1600000 0 0x6600>;
|
||||
reg = <0 0x01600000 0 0x6600>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2790,7 +2819,7 @@
|
||||
|
||||
system_noc: interconnect@1680000 {
|
||||
compatible = "qcom,x1e80100-system-noc";
|
||||
reg = <0 0x1680000 0 0x1c080>;
|
||||
reg = <0 0x01680000 0 0x1c080>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2799,7 +2828,7 @@
|
||||
|
||||
pcie_south_anoc: interconnect@16c0000 {
|
||||
compatible = "qcom,x1e80100-pcie-south-anoc";
|
||||
reg = <0 0x16c0000 0 0xd080>;
|
||||
reg = <0 0x016c0000 0 0xd080>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2808,7 +2837,7 @@
|
||||
|
||||
pcie_center_anoc: interconnect@16d0000 {
|
||||
compatible = "qcom,x1e80100-pcie-center-anoc";
|
||||
reg = <0 0x16d0000 0 0x7000>;
|
||||
reg = <0 0x016d0000 0 0x7000>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2817,7 +2846,7 @@
|
||||
|
||||
aggre1_noc: interconnect@16e0000 {
|
||||
compatible = "qcom,x1e80100-aggre1-noc";
|
||||
reg = <0 0x16E0000 0 0x14400>;
|
||||
reg = <0 0x016e0000 0 0x14400>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2826,7 +2855,7 @@
|
||||
|
||||
aggre2_noc: interconnect@1700000 {
|
||||
compatible = "qcom,x1e80100-aggre2-noc";
|
||||
reg = <0 0x1700000 0 0x1c400>;
|
||||
reg = <0 0x01700000 0 0x1c400>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2835,7 +2864,7 @@
|
||||
|
||||
pcie_north_anoc: interconnect@1740000 {
|
||||
compatible = "qcom,x1e80100-pcie-north-anoc";
|
||||
reg = <0 0x1740000 0 0x9080>;
|
||||
reg = <0 0x01740000 0 0x9080>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2844,7 +2873,7 @@
|
||||
|
||||
usb_center_anoc: interconnect@1750000 {
|
||||
compatible = "qcom,x1e80100-usb-center-anoc";
|
||||
reg = <0 0x1750000 0 0x8800>;
|
||||
reg = <0 0x01750000 0 0x8800>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2853,7 +2882,7 @@
|
||||
|
||||
usb_north_anoc: interconnect@1760000 {
|
||||
compatible = "qcom,x1e80100-usb-north-anoc";
|
||||
reg = <0 0x1760000 0 0x7080>;
|
||||
reg = <0 0x01760000 0 0x7080>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2862,7 +2891,7 @@
|
||||
|
||||
usb_south_anoc: interconnect@1770000 {
|
||||
compatible = "qcom,x1e80100-usb-south-anoc";
|
||||
reg = <0 0x1770000 0 0xf080>;
|
||||
reg = <0 0x01770000 0 0xf080>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2871,7 +2900,7 @@
|
||||
|
||||
mmss_noc: interconnect@1780000 {
|
||||
compatible = "qcom,x1e80100-mmss-noc";
|
||||
reg = <0 0x1780000 0 0x5B800>;
|
||||
reg = <0 0x01780000 0 0x5B800>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -2901,7 +2930,7 @@
|
||||
|
||||
dma-coherent;
|
||||
|
||||
linux,pci-domain = <7>;
|
||||
linux,pci-domain = <6>;
|
||||
num-lanes = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@@ -2959,6 +2988,7 @@
|
||||
"link_down";
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_6A_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
phys = <&pcie6a_phy>;
|
||||
phy-names = "pciephy";
|
||||
@@ -2999,6 +3029,126 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie5: pci@1c00000 {
|
||||
device_type = "pci";
|
||||
compatible = "qcom,pcie-x1e80100";
|
||||
reg = <0 0x01c00000 0 0x3000>,
|
||||
<0 0x7e000000 0 0xf1d>,
|
||||
<0 0x7e000f40 0 0xa8>,
|
||||
<0 0x7e001000 0 0x1000>,
|
||||
<0 0x7e100000 0 0x100000>,
|
||||
<0 0x01c03000 0 0x1000>;
|
||||
reg-names = "parf",
|
||||
"dbi",
|
||||
"elbi",
|
||||
"atu",
|
||||
"config",
|
||||
"mhi";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
dma-coherent;
|
||||
|
||||
linux,pci-domain = <5>;
|
||||
num-lanes = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_5_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_5_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_5_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
|
||||
<&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"noc_aggr",
|
||||
"cnoc_sf_axi";
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
interconnects = <&pcie_south_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "pcie-mem",
|
||||
"cpu-pcie";
|
||||
|
||||
resets = <&gcc GCC_PCIE_5_BCR>,
|
||||
<&gcc GCC_PCIE_5_LINK_DOWN_BCR>;
|
||||
reset-names = "pci",
|
||||
"link_down";
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_5_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
phys = <&pcie5_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie5_phy: phy@1c06000 {
|
||||
compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
|
||||
reg = <0 0x01c06000 0 0x2000>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_5_CFG_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,
|
||||
<&gcc GCC_PCIE_5_PIPE_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg_ahb",
|
||||
"ref",
|
||||
"rchng",
|
||||
"pipe";
|
||||
|
||||
resets = <&gcc GCC_PCIE_5_PHY_BCR>;
|
||||
reset-names = "phy";
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "pcie5_pipe_clk";
|
||||
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie4: pci@1c08000 {
|
||||
device_type = "pci";
|
||||
compatible = "qcom,pcie-x1e80100";
|
||||
@@ -3022,7 +3172,7 @@
|
||||
|
||||
dma-coherent;
|
||||
|
||||
linux,pci-domain = <5>;
|
||||
linux,pci-domain = <4>;
|
||||
num-lanes = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@@ -3080,11 +3230,22 @@
|
||||
"link_down";
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_4_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
phys = <&pcie4_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie4_port0: pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
pcie4_phy: phy@1c0e000 {
|
||||
@@ -3337,7 +3498,7 @@
|
||||
|
||||
nsp_noc: interconnect@320c0000 {
|
||||
compatible = "qcom,x1e80100-nsp-noc";
|
||||
reg = <0 0x320C0000 0 0xE080>;
|
||||
reg = <0 0x320C0000 0 0xe080>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -3372,6 +3533,8 @@
|
||||
|
||||
pinctrl-0 = <&wsa2_swr_active>;
|
||||
pinctrl-names = "default";
|
||||
resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>;
|
||||
reset-names = "swr_audio_cgcr";
|
||||
|
||||
qcom,din-ports = <4>;
|
||||
qcom,dout-ports = <9>;
|
||||
@@ -3420,6 +3583,8 @@
|
||||
pinctrl-0 = <&rx_swr_active>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
|
||||
reset-names = "swr_audio_cgcr";
|
||||
qcom,din-ports = <1>;
|
||||
qcom,dout-ports = <11>;
|
||||
|
||||
@@ -3484,6 +3649,8 @@
|
||||
|
||||
pinctrl-0 = <&wsa_swr_active>;
|
||||
pinctrl-names = "default";
|
||||
resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
|
||||
reset-names = "swr_audio_cgcr";
|
||||
|
||||
qcom,din-ports = <4>;
|
||||
qcom,dout-ports = <9>;
|
||||
@@ -3504,6 +3671,13 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpass_audiocc: clock-controller@6b6c000 {
|
||||
compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
|
||||
reg = <0 0x06b6c000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
swr2: soundwire@6d30000 {
|
||||
compatible = "qcom,soundwire-v2.0.0";
|
||||
reg = <0 0x06d30000 0 0x10000>;
|
||||
@@ -3513,6 +3687,8 @@
|
||||
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "core", "wakeup";
|
||||
label = "TX";
|
||||
resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
|
||||
reset-names = "swr_audio_cgcr";
|
||||
|
||||
pinctrl-0 = <&tx_swr_active>;
|
||||
pinctrl-names = "default";
|
||||
@@ -3669,9 +3845,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
lpasscc: clock-controller@6ea0000 {
|
||||
compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
|
||||
reg = <0 0x06ea0000 0 0x12000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
lpass_ag_noc: interconnect@7e40000 {
|
||||
compatible = "qcom,x1e80100-lpass-ag-noc";
|
||||
reg = <0 0x7e40000 0 0xE080>;
|
||||
reg = <0 0x07e40000 0 0xe080>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -3680,7 +3863,7 @@
|
||||
|
||||
lpass_lpiaon_noc: interconnect@7400000 {
|
||||
compatible = "qcom,x1e80100-lpass-lpiaon-noc";
|
||||
reg = <0 0x7400000 0 0x19080>;
|
||||
reg = <0 0x07400000 0 0x19080>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -3689,7 +3872,7 @@
|
||||
|
||||
lpass_lpicx_noc: interconnect@7430000 {
|
||||
compatible = "qcom,x1e80100-lpass-lpicx-noc";
|
||||
reg = <0 0x7430000 0 0x3A200>;
|
||||
reg = <0 0x07430000 0 0x3A200>;
|
||||
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
|
||||
@@ -3710,6 +3893,90 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_mp_hsphy0: phy@88e1000 {
|
||||
compatible = "qcom,x1e80100-snps-eusb2-phy",
|
||||
"qcom,sm8550-snps-eusb2-phy";
|
||||
reg = <0 0x088e1000 0 0x154>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>;
|
||||
clock-names = "ref";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_mp_hsphy1: phy@88e2000 {
|
||||
compatible = "qcom,x1e80100-snps-eusb2-phy",
|
||||
"qcom,sm8550-snps-eusb2-phy";
|
||||
reg = <0 0x088e2000 0 0x154>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>;
|
||||
clock-names = "ref";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_mp_qmpphy0: phy@88e3000 {
|
||||
compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
|
||||
reg = <0 0x088e3000 0 0x2000>;
|
||||
|
||||
clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
|
||||
<&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
|
||||
clock-names = "aux",
|
||||
"ref",
|
||||
"com_aux",
|
||||
"pipe";
|
||||
|
||||
resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
|
||||
<&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
|
||||
reset-names = "phy",
|
||||
"phy_phy";
|
||||
|
||||
power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "usb_mp_phy0_pipe_clk";
|
||||
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_mp_qmpphy1: phy@88e5000 {
|
||||
compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
|
||||
reg = <0 0x088e5000 0 0x2000>;
|
||||
|
||||
clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
|
||||
<&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
|
||||
clock-names = "aux",
|
||||
"ref",
|
||||
"com_aux",
|
||||
"pipe";
|
||||
|
||||
resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
|
||||
<&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
|
||||
reset-names = "phy",
|
||||
"phy_phy";
|
||||
|
||||
power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "usb_mp_phy1_pipe_clk";
|
||||
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_1_ss2: usb@a0f8800 {
|
||||
compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a0f8800 0 0x400>;
|
||||
@@ -3884,6 +4151,92 @@
|
||||
};
|
||||
};
|
||||
|
||||
usb_mp: usb@a4f8800 {
|
||||
compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
|
||||
reg = <0 0x0a4f8800 0 0x400>;
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
|
||||
<&gcc GCC_USB30_MP_MASTER_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
|
||||
<&gcc GCC_USB30_MP_SLEEP_CLK>,
|
||||
<&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
|
||||
<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
|
||||
clock-names = "cfg_noc",
|
||||
"core",
|
||||
"iface",
|
||||
"sleep",
|
||||
"mock_utmi",
|
||||
"noc_aggr",
|
||||
"noc_aggr_north",
|
||||
"noc_aggr_south",
|
||||
"noc_sys";
|
||||
|
||||
assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_MP_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>,
|
||||
<200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 52 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 51 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 54 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 53 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event_1", "pwr_event_2",
|
||||
"hs_phy_1", "hs_phy_2",
|
||||
"dp_hs_phy_1", "dm_hs_phy_1",
|
||||
"dp_hs_phy_2", "dm_hs_phy_2",
|
||||
"ss_phy_1", "ss_phy_2";
|
||||
|
||||
power-domains = <&gcc GCC_USB30_MP_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
resets = <&gcc GCC_USB30_MP_BCR>;
|
||||
|
||||
interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "usb-ddr",
|
||||
"apps-usb";
|
||||
|
||||
wakeup-source;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
usb_mp_dwc3: usb@a400000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a400000 0 0xcd00>;
|
||||
|
||||
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
iommus = <&apps_smmu 0x1400 0x0>;
|
||||
|
||||
phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>,
|
||||
<&usb_mp_hsphy1>, <&usb_mp_qmpphy1>;
|
||||
phy-names = "usb2-0", "usb3-0",
|
||||
"usb2-1", "usb3-1";
|
||||
dr_mode = "host";
|
||||
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,usb3_lpm_capable;
|
||||
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
|
||||
usb_1_ss0: usb@a6f8800 {
|
||||
compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a6f8800 0 0x400>;
|
||||
@@ -4202,11 +4555,11 @@
|
||||
|
||||
mdss_dp0: displayport-controller@ae90000 {
|
||||
compatible = "qcom,x1e80100-dp";
|
||||
reg = <0 0xae90000 0 0x200>,
|
||||
<0 0xae90200 0 0x200>,
|
||||
<0 0xae90400 0 0x600>,
|
||||
<0 0xae91000 0 0x400>,
|
||||
<0 0xae91400 0 0x400>;
|
||||
reg = <0 0x0ae90000 0 0x200>,
|
||||
<0 0x0ae90200 0 0x200>,
|
||||
<0 0x0ae90400 0 0x600>,
|
||||
<0 0x0ae91000 0 0x400>,
|
||||
<0 0x0ae91400 0 0x400>;
|
||||
|
||||
interrupts-extended = <&mdss 12>;
|
||||
|
||||
@@ -4285,11 +4638,11 @@
|
||||
|
||||
mdss_dp1: displayport-controller@ae98000 {
|
||||
compatible = "qcom,x1e80100-dp";
|
||||
reg = <0 0xae98000 0 0x200>,
|
||||
<0 0xae98200 0 0x200>,
|
||||
<0 0xae98400 0 0x600>,
|
||||
<0 0xae99000 0 0x400>,
|
||||
<0 0xae99400 0 0x400>;
|
||||
reg = <0 0x0ae98000 0 0x200>,
|
||||
<0 0x0ae98200 0 0x200>,
|
||||
<0 0x0ae98400 0 0x600>,
|
||||
<0 0x0ae99000 0 0x400>,
|
||||
<0 0x0ae99400 0 0x400>;
|
||||
|
||||
interrupts-extended = <&mdss 13>;
|
||||
|
||||
@@ -4368,11 +4721,11 @@
|
||||
|
||||
mdss_dp2: displayport-controller@ae9a000 {
|
||||
compatible = "qcom,x1e80100-dp";
|
||||
reg = <0 0xae9a000 0 0x200>,
|
||||
<0 0xae9a200 0 0x200>,
|
||||
<0 0xae9a400 0 0x600>,
|
||||
<0 0xae9b000 0 0x400>,
|
||||
<0 0xae9b400 0 0x400>;
|
||||
reg = <0 0x0ae9a000 0 0x200>,
|
||||
<0 0x0ae9a200 0 0x200>,
|
||||
<0 0x0ae9a400 0 0x600>,
|
||||
<0 0x0ae9b000 0 0x400>,
|
||||
<0 0x0ae9b400 0 0x400>;
|
||||
|
||||
interrupts-extended = <&mdss 14>;
|
||||
|
||||
@@ -4389,14 +4742,14 @@
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss_dp2_phy 0>,
|
||||
<&mdss_dp2_phy 1>;
|
||||
assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
operating-points-v2 = <&mdss_dp2_opp_table>;
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
phys = <&mdss_dp2_phy>;
|
||||
phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
phy-names = "dp";
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
@@ -4450,11 +4803,11 @@
|
||||
|
||||
mdss_dp3: displayport-controller@aea0000 {
|
||||
compatible = "qcom,x1e80100-dp";
|
||||
reg = <0 0xaea0000 0 0x200>,
|
||||
<0 0xaea0200 0 0x200>,
|
||||
<0 0xaea0400 0 0x600>,
|
||||
<0 0xaea1000 0 0x400>,
|
||||
<0 0xaea1400 0 0x400>;
|
||||
reg = <0 0x0aea0000 0 0x200>,
|
||||
<0 0x0aea0200 0 0x200>,
|
||||
<0 0x0aea0400 0 0x600>,
|
||||
<0 0x0aea1000 0 0x400>,
|
||||
<0 0x0aea1400 0 0x400>;
|
||||
|
||||
interrupts-extended = <&mdss 15>;
|
||||
|
||||
@@ -4584,8 +4937,8 @@
|
||||
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
|
||||
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&mdss_dp2_phy 0>, /* dp2 */
|
||||
<&mdss_dp2_phy 1>,
|
||||
<&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */
|
||||
<&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&mdss_dp3_phy 0>, /* dp3 */
|
||||
<&mdss_dp3_phy 1>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
@@ -4618,6 +4971,11 @@
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sram@c3f0000 {
|
||||
compatible = "qcom,rpmh-stats";
|
||||
reg = <0 0x0c3f0000 0 0x400>;
|
||||
};
|
||||
|
||||
spmi: arbiter@c400000 {
|
||||
compatible = "qcom,x1e80100-spmi-pmic-arb";
|
||||
reg = <0 0x0c400000 0 0x3000>,
|
||||
@@ -5228,12 +5586,50 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_uart2_default: qup-uart2-default-state {
|
||||
cts-pins {
|
||||
pins = "gpio8";
|
||||
function = "qup0_se2";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rts-pins {
|
||||
pins = "gpio9";
|
||||
function = "qup0_se2";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tx-pins {
|
||||
pins = "gpio10";
|
||||
function = "qup0_se2";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rx-pins {
|
||||
pins = "gpio11";
|
||||
function = "qup0_se2";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart21_default: qup-uart21-default-state {
|
||||
/* TX, RX */
|
||||
pins = "gpio86", "gpio87";
|
||||
function = "qup2_se5";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
tx-pins {
|
||||
pins = "gpio86";
|
||||
function = "qup2_se5";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rx-pins {
|
||||
pins = "gpio87";
|
||||
function = "qup2_se5";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -193,10 +193,15 @@
|
||||
#define GCC_MMSS_GPLL0_DIV_CLK 184
|
||||
#define GCC_GPU_GPLL0_DIV_CLK 185
|
||||
#define GCC_GPU_GPLL0_CLK 186
|
||||
#define HLOS1_VOTE_LPASS_CORE_SMMU_CLK 187
|
||||
#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 188
|
||||
#define GCC_MSS_Q6_BIMC_AXI_CLK 189
|
||||
|
||||
#define PCIE_0_GDSC 0
|
||||
#define UFS_GDSC 1
|
||||
#define USB_30_GDSC 2
|
||||
#define LPASS_ADSP_GDSC 3
|
||||
#define LPASS_CORE_GDSC 4
|
||||
|
||||
#define GCC_BLSP1_QUP1_BCR 0
|
||||
#define GCC_BLSP1_QUP2_BCR 1
|
||||
|
||||
@@ -294,6 +294,10 @@
|
||||
#define GCC_VIDEO_AXI0_CLK_BCR 42
|
||||
#define GCC_VIDEO_AXI1_CLK_BCR 43
|
||||
#define GCC_USB3_DP_PHY_SEC_BCR 44
|
||||
#define GCC_USB3_UNIPHY_MP0_BCR 45
|
||||
#define GCC_USB3_UNIPHY_MP1_BCR 46
|
||||
#define GCC_USB3UNIPHY_PHY_MP0_BCR 47
|
||||
#define GCC_USB3UNIPHY_PHY_MP1_BCR 48
|
||||
|
||||
/* GCC GDSCRs */
|
||||
#define EMAC_GDSC 0
|
||||
|
||||
@@ -0,0 +1,106 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
|
||||
|
||||
/* CAM_CC clocks */
|
||||
#define CAM_CC_BPS_AHB_CLK 0
|
||||
#define CAM_CC_BPS_AREG_CLK 1
|
||||
#define CAM_CC_BPS_CLK 2
|
||||
#define CAM_CC_BPS_CLK_SRC 3
|
||||
#define CAM_CC_CAMNOC_ATB_CLK 4
|
||||
#define CAM_CC_CAMNOC_AXI_CLK 5
|
||||
#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
|
||||
#define CAM_CC_CAMNOC_AXI_HF_CLK 7
|
||||
#define CAM_CC_CAMNOC_AXI_SF_CLK 8
|
||||
#define CAM_CC_CCI_0_CLK 9
|
||||
#define CAM_CC_CCI_0_CLK_SRC 10
|
||||
#define CAM_CC_CCI_1_CLK 11
|
||||
#define CAM_CC_CCI_1_CLK_SRC 12
|
||||
#define CAM_CC_CORE_AHB_CLK 13
|
||||
#define CAM_CC_CPAS_AHB_CLK 14
|
||||
#define CAM_CC_CPHY_RX_CLK_SRC 15
|
||||
#define CAM_CC_CRE_AHB_CLK 16
|
||||
#define CAM_CC_CRE_CLK 17
|
||||
#define CAM_CC_CRE_CLK_SRC 18
|
||||
#define CAM_CC_CSI0PHYTIMER_CLK 19
|
||||
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 20
|
||||
#define CAM_CC_CSI1PHYTIMER_CLK 21
|
||||
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 22
|
||||
#define CAM_CC_CSI2PHYTIMER_CLK 23
|
||||
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 24
|
||||
#define CAM_CC_CSIPHY0_CLK 25
|
||||
#define CAM_CC_CSIPHY1_CLK 26
|
||||
#define CAM_CC_CSIPHY2_CLK 27
|
||||
#define CAM_CC_FAST_AHB_CLK_SRC 28
|
||||
#define CAM_CC_ICP_ATB_CLK 29
|
||||
#define CAM_CC_ICP_CLK 30
|
||||
#define CAM_CC_ICP_CLK_SRC 31
|
||||
#define CAM_CC_ICP_CTI_CLK 32
|
||||
#define CAM_CC_ICP_TS_CLK 33
|
||||
#define CAM_CC_MCLK0_CLK 34
|
||||
#define CAM_CC_MCLK0_CLK_SRC 35
|
||||
#define CAM_CC_MCLK1_CLK 36
|
||||
#define CAM_CC_MCLK1_CLK_SRC 37
|
||||
#define CAM_CC_MCLK2_CLK 38
|
||||
#define CAM_CC_MCLK2_CLK_SRC 39
|
||||
#define CAM_CC_MCLK3_CLK 40
|
||||
#define CAM_CC_MCLK3_CLK_SRC 41
|
||||
#define CAM_CC_OPE_0_AHB_CLK 42
|
||||
#define CAM_CC_OPE_0_AREG_CLK 43
|
||||
#define CAM_CC_OPE_0_CLK 44
|
||||
#define CAM_CC_OPE_0_CLK_SRC 45
|
||||
#define CAM_CC_PLL0 46
|
||||
#define CAM_CC_PLL0_OUT_EVEN 47
|
||||
#define CAM_CC_PLL0_OUT_ODD 48
|
||||
#define CAM_CC_PLL1 49
|
||||
#define CAM_CC_PLL1_OUT_EVEN 50
|
||||
#define CAM_CC_PLL2 51
|
||||
#define CAM_CC_PLL2_OUT_EVEN 52
|
||||
#define CAM_CC_PLL3 53
|
||||
#define CAM_CC_PLL3_OUT_EVEN 54
|
||||
#define CAM_CC_PLL4 55
|
||||
#define CAM_CC_PLL4_OUT_EVEN 56
|
||||
#define CAM_CC_SLOW_AHB_CLK_SRC 57
|
||||
#define CAM_CC_SOC_AHB_CLK 58
|
||||
#define CAM_CC_SYS_TMR_CLK 59
|
||||
#define CAM_CC_TFE_0_AHB_CLK 60
|
||||
#define CAM_CC_TFE_0_CLK 61
|
||||
#define CAM_CC_TFE_0_CLK_SRC 62
|
||||
#define CAM_CC_TFE_0_CPHY_RX_CLK 63
|
||||
#define CAM_CC_TFE_0_CSID_CLK 64
|
||||
#define CAM_CC_TFE_0_CSID_CLK_SRC 65
|
||||
#define CAM_CC_TFE_1_AHB_CLK 66
|
||||
#define CAM_CC_TFE_1_CLK 67
|
||||
#define CAM_CC_TFE_1_CLK_SRC 68
|
||||
#define CAM_CC_TFE_1_CPHY_RX_CLK 69
|
||||
#define CAM_CC_TFE_1_CSID_CLK 70
|
||||
#define CAM_CC_TFE_1_CSID_CLK_SRC 71
|
||||
|
||||
/* CAM_CC power domains */
|
||||
#define CAM_CC_CAMSS_TOP_GDSC 0
|
||||
|
||||
/* CAM_CC resets */
|
||||
#define CAM_CC_BPS_BCR 0
|
||||
#define CAM_CC_CAMNOC_BCR 1
|
||||
#define CAM_CC_CAMSS_TOP_BCR 2
|
||||
#define CAM_CC_CCI_0_BCR 3
|
||||
#define CAM_CC_CCI_1_BCR 4
|
||||
#define CAM_CC_CPAS_BCR 5
|
||||
#define CAM_CC_CRE_BCR 6
|
||||
#define CAM_CC_CSI0PHY_BCR 7
|
||||
#define CAM_CC_CSI1PHY_BCR 8
|
||||
#define CAM_CC_CSI2PHY_BCR 9
|
||||
#define CAM_CC_ICP_BCR 10
|
||||
#define CAM_CC_MCLK0_BCR 11
|
||||
#define CAM_CC_MCLK1_BCR 12
|
||||
#define CAM_CC_MCLK2_BCR 13
|
||||
#define CAM_CC_MCLK3_BCR 14
|
||||
#define CAM_CC_OPE_0_BCR 15
|
||||
#define CAM_CC_TFE_0_BCR 16
|
||||
#define CAM_CC_TFE_1_BCR 17
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,51 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
|
||||
|
||||
/* DISP_CC clocks */
|
||||
#define DISP_CC_MDSS_AHB1_CLK 0
|
||||
#define DISP_CC_MDSS_AHB_CLK 1
|
||||
#define DISP_CC_MDSS_AHB_CLK_SRC 2
|
||||
#define DISP_CC_MDSS_BYTE0_CLK 3
|
||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
|
||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
|
||||
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
|
||||
#define DISP_CC_MDSS_ESC0_CLK 7
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 8
|
||||
#define DISP_CC_MDSS_MDP1_CLK 9
|
||||
#define DISP_CC_MDSS_MDP_CLK 10
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 11
|
||||
#define DISP_CC_MDSS_MDP_LUT1_CLK 12
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 13
|
||||
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 14
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 15
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
|
||||
#define DISP_CC_MDSS_ROT1_CLK 17
|
||||
#define DISP_CC_MDSS_ROT_CLK 18
|
||||
#define DISP_CC_MDSS_ROT_CLK_SRC 19
|
||||
#define DISP_CC_MDSS_RSCC_AHB_CLK 20
|
||||
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 21
|
||||
#define DISP_CC_MDSS_VSYNC1_CLK 22
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 23
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
|
||||
#define DISP_CC_PLL0 25
|
||||
#define DISP_CC_PLL1 26
|
||||
#define DISP_CC_SLEEP_CLK 27
|
||||
#define DISP_CC_SLEEP_CLK_SRC 28
|
||||
#define DISP_CC_XO_CLK 29
|
||||
#define DISP_CC_XO_CLK_SRC 30
|
||||
|
||||
/* DISP_CC power domains */
|
||||
#define DISP_CC_MDSS_CORE_GDSC 0
|
||||
#define DISP_CC_MDSS_CORE_INT2_GDSC 1
|
||||
|
||||
/* DISP_CC resets */
|
||||
#define DISP_CC_MDSS_CORE_BCR 0
|
||||
#define DISP_CC_MDSS_CORE_INT2_BCR 1
|
||||
#define DISP_CC_MDSS_RSCC_BCR 2
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
|
||||
|
||||
/* GPU_CC clocks */
|
||||
#define GPU_CC_AHB_CLK 0
|
||||
#define GPU_CC_CB_CLK 1
|
||||
#define GPU_CC_CRC_AHB_CLK 2
|
||||
#define GPU_CC_CX_FF_CLK 3
|
||||
#define GPU_CC_CX_GFX3D_CLK 4
|
||||
#define GPU_CC_CX_GFX3D_SLV_CLK 5
|
||||
#define GPU_CC_CX_GMU_CLK 6
|
||||
#define GPU_CC_CX_SNOC_DVM_CLK 7
|
||||
#define GPU_CC_CXO_AON_CLK 8
|
||||
#define GPU_CC_CXO_CLK 9
|
||||
#define GPU_CC_DEMET_CLK 10
|
||||
#define GPU_CC_DEMET_DIV_CLK_SRC 11
|
||||
#define GPU_CC_FF_CLK_SRC 12
|
||||
#define GPU_CC_FREQ_MEASURE_CLK 13
|
||||
#define GPU_CC_GMU_CLK_SRC 14
|
||||
#define GPU_CC_GX_CXO_CLK 15
|
||||
#define GPU_CC_GX_FF_CLK 16
|
||||
#define GPU_CC_GX_GFX3D_CLK 17
|
||||
#define GPU_CC_GX_GFX3D_CLK_SRC 18
|
||||
#define GPU_CC_GX_GFX3D_RDVM_CLK 19
|
||||
#define GPU_CC_GX_GMU_CLK 20
|
||||
#define GPU_CC_GX_VSENSE_CLK 21
|
||||
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 22
|
||||
#define GPU_CC_HUB_AON_CLK 23
|
||||
#define GPU_CC_HUB_CLK_SRC 24
|
||||
#define GPU_CC_HUB_CX_INT_CLK 25
|
||||
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 26
|
||||
#define GPU_CC_MEMNOC_GFX_CLK 27
|
||||
#define GPU_CC_MND1X_0_GFX3D_CLK 28
|
||||
#define GPU_CC_PLL0 29
|
||||
#define GPU_CC_PLL1 30
|
||||
#define GPU_CC_SLEEP_CLK 31
|
||||
#define GPU_CC_XO_CLK_SRC 32
|
||||
#define GPU_CC_XO_DIV_CLK_SRC 33
|
||||
|
||||
/* GPU_CC power domains */
|
||||
#define GPU_CC_CX_GDSC 0
|
||||
#define GPU_CC_GX_GDSC 1
|
||||
|
||||
/* GPU_CC resets */
|
||||
#define GPU_CC_ACD_BCR 0
|
||||
#define GPU_CC_CB_BCR 1
|
||||
#define GPU_CC_CX_BCR 2
|
||||
#define GPU_CC_FAST_HUB_BCR 3
|
||||
#define GPU_CC_FF_BCR 4
|
||||
#define GPU_CC_GFX3D_AON_BCR 5
|
||||
#define GPU_CC_GMU_BCR 6
|
||||
#define GPU_CC_GX_BCR 7
|
||||
#define GPU_CC_XO_BCR 8
|
||||
#define GPU_CC_GX_ACD_IROOT_BCR 9
|
||||
#define GPU_CC_RBCPR_BCR 10
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,135 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
|
||||
|
||||
/* CAM_CC clocks */
|
||||
#define CAM_CC_PLL0 0
|
||||
#define CAM_CC_PLL0_OUT_EVEN 1
|
||||
#define CAM_CC_PLL0_OUT_ODD 2
|
||||
#define CAM_CC_PLL1 3
|
||||
#define CAM_CC_PLL1_OUT_EVEN 4
|
||||
#define CAM_CC_PLL2 5
|
||||
#define CAM_CC_PLL2_OUT_MAIN 6
|
||||
#define CAM_CC_PLL3 7
|
||||
#define CAM_CC_PLL3_OUT_EVEN 8
|
||||
#define CAM_CC_PLL4 9
|
||||
#define CAM_CC_PLL4_OUT_EVEN 10
|
||||
#define CAM_CC_BPS_AHB_CLK 11
|
||||
#define CAM_CC_BPS_AREG_CLK 12
|
||||
#define CAM_CC_BPS_AXI_CLK 13
|
||||
#define CAM_CC_BPS_CLK 14
|
||||
#define CAM_CC_BPS_CLK_SRC 15
|
||||
#define CAM_CC_CAMNOC_AXI_CLK 16
|
||||
#define CAM_CC_CAMNOC_AXI_CLK_SRC 17
|
||||
#define CAM_CC_CAMNOC_DCD_XO_CLK 18
|
||||
#define CAM_CC_CCI_0_CLK 19
|
||||
#define CAM_CC_CCI_0_CLK_SRC 20
|
||||
#define CAM_CC_CCI_1_CLK 21
|
||||
#define CAM_CC_CCI_1_CLK_SRC 22
|
||||
#define CAM_CC_CORE_AHB_CLK 23
|
||||
#define CAM_CC_CPAS_AHB_CLK 24
|
||||
#define CAM_CC_CPHY_RX_CLK_SRC 25
|
||||
#define CAM_CC_CSI0PHYTIMER_CLK 26
|
||||
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 27
|
||||
#define CAM_CC_CSI1PHYTIMER_CLK 28
|
||||
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 29
|
||||
#define CAM_CC_CSI2PHYTIMER_CLK 30
|
||||
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 31
|
||||
#define CAM_CC_CSI3PHYTIMER_CLK 32
|
||||
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 33
|
||||
#define CAM_CC_CSIPHY0_CLK 34
|
||||
#define CAM_CC_CSIPHY1_CLK 35
|
||||
#define CAM_CC_CSIPHY2_CLK 36
|
||||
#define CAM_CC_CSIPHY3_CLK 37
|
||||
#define CAM_CC_FAST_AHB_CLK_SRC 38
|
||||
#define CAM_CC_FD_CORE_CLK 39
|
||||
#define CAM_CC_FD_CORE_CLK_SRC 40
|
||||
#define CAM_CC_FD_CORE_UAR_CLK 41
|
||||
#define CAM_CC_GDSC_CLK 42
|
||||
#define CAM_CC_ICP_AHB_CLK 43
|
||||
#define CAM_CC_ICP_CLK 44
|
||||
#define CAM_CC_ICP_CLK_SRC 45
|
||||
#define CAM_CC_IFE_0_AXI_CLK 46
|
||||
#define CAM_CC_IFE_0_CLK 47
|
||||
#define CAM_CC_IFE_0_CLK_SRC 48
|
||||
#define CAM_CC_IFE_0_CPHY_RX_CLK 49
|
||||
#define CAM_CC_IFE_0_CSID_CLK 50
|
||||
#define CAM_CC_IFE_0_CSID_CLK_SRC 51
|
||||
#define CAM_CC_IFE_0_DSP_CLK 52
|
||||
#define CAM_CC_IFE_1_AXI_CLK 53
|
||||
#define CAM_CC_IFE_1_CLK 54
|
||||
#define CAM_CC_IFE_1_CLK_SRC 55
|
||||
#define CAM_CC_IFE_1_CPHY_RX_CLK 56
|
||||
#define CAM_CC_IFE_1_CSID_CLK 57
|
||||
#define CAM_CC_IFE_1_CSID_CLK_SRC 58
|
||||
#define CAM_CC_IFE_1_DSP_CLK 59
|
||||
#define CAM_CC_IFE_LITE_0_CLK 60
|
||||
#define CAM_CC_IFE_LITE_0_CLK_SRC 61
|
||||
#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 62
|
||||
#define CAM_CC_IFE_LITE_0_CSID_CLK 63
|
||||
#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 64
|
||||
#define CAM_CC_IFE_LITE_1_CLK 65
|
||||
#define CAM_CC_IFE_LITE_1_CLK_SRC 66
|
||||
#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 67
|
||||
#define CAM_CC_IFE_LITE_1_CSID_CLK 68
|
||||
#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 69
|
||||
#define CAM_CC_IPE_0_AHB_CLK 70
|
||||
#define CAM_CC_IPE_0_AREG_CLK 71
|
||||
#define CAM_CC_IPE_0_AXI_CLK 72
|
||||
#define CAM_CC_IPE_0_CLK 73
|
||||
#define CAM_CC_IPE_0_CLK_SRC 74
|
||||
#define CAM_CC_IPE_1_AHB_CLK 75
|
||||
#define CAM_CC_IPE_1_AREG_CLK 76
|
||||
#define CAM_CC_IPE_1_AXI_CLK 77
|
||||
#define CAM_CC_IPE_1_CLK 78
|
||||
#define CAM_CC_JPEG_CLK 79
|
||||
#define CAM_CC_JPEG_CLK_SRC 80
|
||||
#define CAM_CC_LRME_CLK 81
|
||||
#define CAM_CC_LRME_CLK_SRC 82
|
||||
#define CAM_CC_MCLK0_CLK 83
|
||||
#define CAM_CC_MCLK0_CLK_SRC 84
|
||||
#define CAM_CC_MCLK1_CLK 85
|
||||
#define CAM_CC_MCLK1_CLK_SRC 86
|
||||
#define CAM_CC_MCLK2_CLK 87
|
||||
#define CAM_CC_MCLK2_CLK_SRC 88
|
||||
#define CAM_CC_MCLK3_CLK 89
|
||||
#define CAM_CC_MCLK3_CLK_SRC 90
|
||||
#define CAM_CC_SLOW_AHB_CLK_SRC 91
|
||||
|
||||
/* CAM_CC power domains */
|
||||
#define TITAN_TOP_GDSC 0
|
||||
#define BPS_GDSC 1
|
||||
#define IFE_0_GDSC 2
|
||||
#define IFE_1_GDSC 3
|
||||
#define IPE_0_GDSC 4
|
||||
#define IPE_1_GDSC 5
|
||||
|
||||
/* CAM_CC resets */
|
||||
#define CAM_CC_BPS_BCR 0
|
||||
#define CAM_CC_CAMNOC_BCR 1
|
||||
#define CAM_CC_CCI_BCR 2
|
||||
#define CAM_CC_CPAS_BCR 3
|
||||
#define CAM_CC_CSI0PHY_BCR 4
|
||||
#define CAM_CC_CSI1PHY_BCR 5
|
||||
#define CAM_CC_CSI2PHY_BCR 6
|
||||
#define CAM_CC_CSI3PHY_BCR 7
|
||||
#define CAM_CC_FD_BCR 8
|
||||
#define CAM_CC_ICP_BCR 9
|
||||
#define CAM_CC_IFE_0_BCR 10
|
||||
#define CAM_CC_IFE_1_BCR 11
|
||||
#define CAM_CC_IFE_LITE_0_BCR 12
|
||||
#define CAM_CC_IFE_LITE_1_BCR 13
|
||||
#define CAM_CC_IPE_0_BCR 14
|
||||
#define CAM_CC_IPE_1_BCR 15
|
||||
#define CAM_CC_JPEG_BCR 16
|
||||
#define CAM_CC_LRME_BCR 17
|
||||
#define CAM_CC_MCLK0_BCR 18
|
||||
#define CAM_CC_MCLK1_BCR 19
|
||||
#define CAM_CC_MCLK2_BCR 20
|
||||
#define CAM_CC_MCLK3_BCR 21
|
||||
|
||||
#endif
|
||||
@@ -1,102 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
|
||||
* Copyright (c) 2023, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
|
||||
|
||||
/* DISP_CC clocks */
|
||||
#define DISP_CC_MDSS_ACCU_CLK 0
|
||||
#define DISP_CC_MDSS_AHB1_CLK 1
|
||||
#define DISP_CC_MDSS_AHB_CLK 2
|
||||
#define DISP_CC_MDSS_AHB_CLK_SRC 3
|
||||
#define DISP_CC_MDSS_BYTE0_CLK 4
|
||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
|
||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
|
||||
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
|
||||
#define DISP_CC_MDSS_BYTE1_CLK 8
|
||||
#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
|
||||
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
|
||||
#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
|
||||
#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
|
||||
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
|
||||
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_CLK 15
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22
|
||||
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23
|
||||
#define DISP_CC_MDSS_DPTX1_AUX_CLK 24
|
||||
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25
|
||||
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_CLK 27
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34
|
||||
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35
|
||||
#define DISP_CC_MDSS_DPTX2_AUX_CLK 36
|
||||
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37
|
||||
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_CLK 39
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46
|
||||
#define DISP_CC_MDSS_DPTX3_AUX_CLK 47
|
||||
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48
|
||||
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_CLK 50
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53
|
||||
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54
|
||||
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55
|
||||
#define DISP_CC_MDSS_ESC0_CLK 56
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 57
|
||||
#define DISP_CC_MDSS_ESC1_CLK 58
|
||||
#define DISP_CC_MDSS_ESC1_CLK_SRC 59
|
||||
#define DISP_CC_MDSS_MDP1_CLK 60
|
||||
#define DISP_CC_MDSS_MDP_CLK 61
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 62
|
||||
#define DISP_CC_MDSS_MDP_LUT1_CLK 63
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 64
|
||||
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 66
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 67
|
||||
#define DISP_CC_MDSS_PCLK1_CLK 68
|
||||
#define DISP_CC_MDSS_PCLK1_CLK_SRC 69
|
||||
#define DISP_CC_MDSS_RSCC_AHB_CLK 70
|
||||
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71
|
||||
#define DISP_CC_MDSS_VSYNC1_CLK 72
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 73
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 74
|
||||
#define DISP_CC_PLL0 75
|
||||
#define DISP_CC_PLL1 76
|
||||
#define DISP_CC_SLEEP_CLK 77
|
||||
#define DISP_CC_SLEEP_CLK_SRC 78
|
||||
#define DISP_CC_XO_CLK 79
|
||||
#define DISP_CC_XO_CLK_SRC 80
|
||||
|
||||
/* DISP_CC resets */
|
||||
#define DISP_CC_MDSS_CORE_BCR 0
|
||||
#define DISP_CC_MDSS_CORE_INT2_BCR 1
|
||||
#define DISP_CC_MDSS_RSCC_BCR 2
|
||||
|
||||
/* DISP_CC GDSCR */
|
||||
#define MDSS_GDSC 0
|
||||
#define MDSS_INT2_GDSC 1
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1 @@
|
||||
qcom,sm8550-dispcc.h
|
||||
@@ -0,0 +1,46 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
#ifndef INTERCONNECT_QCOM_IPQ5332_H
|
||||
#define INTERCONNECT_QCOM_IPQ5332_H
|
||||
|
||||
#define MASTER_SNOC_PCIE3_1_M 0
|
||||
#define SLAVE_SNOC_PCIE3_1_M 1
|
||||
#define MASTER_ANOC_PCIE3_1_S 2
|
||||
#define SLAVE_ANOC_PCIE3_1_S 3
|
||||
#define MASTER_SNOC_PCIE3_2_M 4
|
||||
#define SLAVE_SNOC_PCIE3_2_M 5
|
||||
#define MASTER_ANOC_PCIE3_2_S 6
|
||||
#define SLAVE_ANOC_PCIE3_2_S 7
|
||||
#define MASTER_SNOC_USB 8
|
||||
#define SLAVE_SNOC_USB 9
|
||||
#define MASTER_NSSNOC_NSSCC 10
|
||||
#define SLAVE_NSSNOC_NSSCC 11
|
||||
#define MASTER_NSSNOC_SNOC_0 12
|
||||
#define SLAVE_NSSNOC_SNOC_0 13
|
||||
#define MASTER_NSSNOC_SNOC_1 14
|
||||
#define SLAVE_NSSNOC_SNOC_1 15
|
||||
#define MASTER_NSSNOC_ATB 16
|
||||
#define SLAVE_NSSNOC_ATB 17
|
||||
#define MASTER_NSSNOC_PCNOC_1 18
|
||||
#define SLAVE_NSSNOC_PCNOC_1 19
|
||||
#define MASTER_NSSNOC_QOSGEN_REF 20
|
||||
#define SLAVE_NSSNOC_QOSGEN_REF 21
|
||||
#define MASTER_NSSNOC_TIMEOUT_REF 22
|
||||
#define SLAVE_NSSNOC_TIMEOUT_REF 23
|
||||
#define MASTER_NSSNOC_XO_DCD 24
|
||||
#define SLAVE_NSSNOC_XO_DCD 25
|
||||
|
||||
#define MASTER_NSSNOC_PPE 0
|
||||
#define SLAVE_NSSNOC_PPE 1
|
||||
#define MASTER_NSSNOC_PPE_CFG 2
|
||||
#define SLAVE_NSSNOC_PPE_CFG 3
|
||||
#define MASTER_NSSNOC_NSS_CSR 4
|
||||
#define SLAVE_NSSNOC_NSS_CSR 5
|
||||
#define MASTER_NSSNOC_CE_APB 6
|
||||
#define SLAVE_NSSNOC_CE_APB 7
|
||||
#define MASTER_NSSNOC_CE_AXI 8
|
||||
#define SLAVE_NSSNOC_CE_AXI 9
|
||||
|
||||
#define MASTER_CNOC_AHB 0
|
||||
#define SLAVE_CNOC_AHB 1
|
||||
|
||||
#endif /* INTERCONNECT_QCOM_IPQ5332_H */
|
||||
@@ -33,5 +33,7 @@
|
||||
#define IPCC_CLIENT_NSP1 18
|
||||
#define IPCC_CLIENT_TME 23
|
||||
#define IPCC_CLIENT_WPSS 24
|
||||
#define IPCC_CLIENT_GPDSP0 31
|
||||
#define IPCC_CLIENT_GPDSP1 32
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user