Merge tag 'mtd/fixes-for-4.19-rc5' of git://git.infradead.org/linux-mtd
Boris writes:
"- Fixes a bug in the ->read/write_reg() implementation of the m25p80
driver
- Make sure of_node_get/put() calls are balanced in the partition
parsing code
- Fix a race in the denali NAND controller driver
- Fix false positive WARN_ON() in the marvell NAND controller driver"
* tag 'mtd/fixes-for-4.19-rc5' of git://git.infradead.org/linux-mtd:
mtd: devices: m25p80: Make sure the buffer passed in op is DMA-able
mtd: partitions: fix unbalanced of_node_get/put()
mtd: rawnand: denali: fix a race condition when DMA is kicked
mtd: rawnand: marvell: prevent harmless warnings
This commit is contained in:
@@ -39,13 +39,23 @@ static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(len, val, 1));
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SPI_MEM_OP_DATA_IN(len, NULL, 1));
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void *scratchbuf;
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int ret;
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scratchbuf = kmalloc(len, GFP_KERNEL);
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if (!scratchbuf)
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return -ENOMEM;
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op.data.buf.in = scratchbuf;
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ret = spi_mem_exec_op(flash->spimem, &op);
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if (ret < 0)
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dev_err(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
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code);
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else
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memcpy(val, scratchbuf, len);
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kfree(scratchbuf);
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return ret;
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}
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@@ -56,9 +66,19 @@ static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(len, buf, 1));
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SPI_MEM_OP_DATA_OUT(len, NULL, 1));
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void *scratchbuf;
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int ret;
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return spi_mem_exec_op(flash->spimem, &op);
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scratchbuf = kmemdup(buf, len, GFP_KERNEL);
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if (!scratchbuf)
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return -ENOMEM;
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op.data.buf.out = scratchbuf;
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ret = spi_mem_exec_op(flash->spimem, &op);
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kfree(scratchbuf);
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return ret;
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}
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static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
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@@ -873,8 +873,11 @@ static int mtd_part_of_parse(struct mtd_info *master,
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int ret, err = 0;
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np = mtd_get_of_node(master);
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if (!mtd_is_partition(master))
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if (mtd_is_partition(master))
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of_node_get(np);
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else
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np = of_get_child_by_name(np, "partitions");
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of_property_for_each_string(np, "compatible", prop, compat) {
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parser = mtd_part_get_compatible_parser(compat);
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if (!parser)
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@@ -596,6 +596,12 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
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}
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iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
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/*
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* The ->setup_dma() hook kicks DMA by using the data/command
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* interface, which belongs to a different AXI port from the
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* register interface. Read back the register to avoid a race.
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*/
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ioread32(denali->reg + DMA_ENABLE);
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denali_reset_irq(denali);
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denali->setup_dma(denali, dma_addr, page, write);
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@@ -1547,7 +1547,7 @@ static void marvell_nfc_parse_instructions(struct nand_chip *chip,
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for (op_id = 0; op_id < subop->ninstrs; op_id++) {
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unsigned int offset, naddrs;
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const u8 *addrs;
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int len = nand_subop_get_data_len(subop, op_id);
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int len;
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instr = &subop->instrs[op_id];
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@@ -1593,6 +1593,7 @@ static void marvell_nfc_parse_instructions(struct nand_chip *chip,
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nfc_op->ndcb[0] |=
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NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
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NDCB0_LEN_OVRD;
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len = nand_subop_get_data_len(subop, op_id);
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nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
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}
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nfc_op->data_delay_ns = instr->delay_ns;
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@@ -1606,6 +1607,7 @@ static void marvell_nfc_parse_instructions(struct nand_chip *chip,
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nfc_op->ndcb[0] |=
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NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
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NDCB0_LEN_OVRD;
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len = nand_subop_get_data_len(subop, op_id);
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nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
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}
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nfc_op->data_delay_ns = instr->delay_ns;
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