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Merge tag 'socfpga_dts_updates_for_v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt

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SoCFPGA DTS updates for v6.8
- Fix dtbs_check warnings for nand, usb, FPGA firmware, and pin-controller
- Clean up of DTS for Agilex5

* tag 'socfpga_dts_updates_for_v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: intel: minor whitespace cleanup around '='
  arm64: dts: socfpga: agilex: drop redundant status
  arm64: dts: socfpga: agilex: add unit address to soc node
  arm64: dts: socfpga: agilex: move firmware out of soc node
  arm64: dts: socfpga: agilex: move FPGA region out of soc node
  arm64: dts: socfpga: agilex: align pin-controller name with bindings
  arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties
  arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings
  arm64: dts: socfpga: stratix10: add unit address to soc node
  arm64: dts: socfpga: stratix10: move firmware out of soc node
  arm64: dts: socfpga: stratix10: move FPGA region out of soc node
  arm64: dts: socfpga: stratix10: align pincfg nodes with bindings
  arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB
  arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
  ARM: dts: socfpga: align NAND controller name with bindings
  ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size

Link: https://lore.kernel.org/r/20240104001354.152410-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-01-05 11:15:29 +01:00
parent b236329750 16615a2aa5
commit 3f2f25b5ae
17 changed files with 53 additions and 77 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
+1 -1
View File
@@ -768,7 +768,7 @@
status = "disabled";
};
nand0: nand@ff900000 {
nand0: nand-controller@ff900000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "altr,socfpga-denali-nand";
arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
+1 -1
View File
@@ -669,7 +669,7 @@
status = "disabled";
};
nand: nand@ffb90000 {
nand: nand-controller@ffb90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-denali-nand";
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_qspi.dts
-2
View File
@@ -17,8 +17,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <3>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dts
-2
View File
@@ -124,8 +124,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts
-2
View File
@@ -129,8 +129,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dts
-2
View File
@@ -174,8 +174,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dts
-2
View File
@@ -121,8 +121,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dts
-4
View File
@@ -229,8 +229,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
@@ -246,8 +244,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+21 -20
View File
@@ -59,6 +59,25 @@
};
};
firmware {
svc {
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <&service_reserved>;
fpga_mgr: fpga-mgr {
compatible = "intel,stratix10-soc-fpga-mgr";
};
};
};
fpga-region {
compatible = "fpga-region";
#address-cells = <0x2>;
#size-cells = <0x2>;
fpga-mgr = <&fpga_mgr>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 170 4>,
@@ -125,7 +144,7 @@
};
};
soc {
soc@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -133,13 +152,6 @@
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
base_fpga_region {
#address-cells = <0x2>;
#size-cells = <0x2>;
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr>;
};
clkmgr: clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
@@ -510,6 +522,7 @@
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
clocks = <&clkmgr STRATIX10_USB_CLK>;
clock-names = "otg";
iommus = <&smmu 7>;
status = "disabled";
};
@@ -620,18 +633,6 @@
status = "disabled";
};
firmware {
svc {
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <&service_reserved>;
fpga_mgr: fpga-mgr {
compatible = "intel,stratix10-soc-fpga-mgr";
};
};
};
};
usbphy0: usbphy0 {
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+3 -5
View File
@@ -51,7 +51,7 @@
regulator-max-microvolt = <330000>;
};
soc {
soc@0 {
eccmgr {
sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
@@ -66,14 +66,14 @@
};
&pinctrl0 {
i2c1_pmx_func: i2c1-pmx-func {
i2c1_pmx_func: i2c1-pmx-func-pins {
pinctrl-single,pins = <
0x78 0x4 /* I2C1_SDA (IO6-B) PIN30SEL) */
0x7c 0x4 /* I2C1_SCL (IO7-B) PIN31SEL */
>;
};
i2c1_pmx_func_gpio: i2c1-pmx-func-gpio {
i2c1_pmx_func_gpio: i2c1-pmx-func-gpio-pins {
pinctrl-single,pins = <
0x78 0x8 /* I2C1_SDA (IO6-B) PIN30SEL) */
0x7c 0x8 /* I2C1_SCL (IO7-B) PIN31SEL */
@@ -187,8 +187,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <1>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
+2 -4
View File
@@ -51,7 +51,7 @@
regulator-max-microvolt = <330000>;
};
soc {
soc@0 {
eccmgr {
sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
@@ -102,7 +102,7 @@
&nand {
status = "okay";
flash@0 {
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
@@ -176,8 +176,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <1>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts
-2
View File
@@ -80,8 +80,6 @@
&mmc {
status = "okay";
altr,dw-mshc-ciu-div = <0x3>;
altr,dw-mshc-sdr-timing = <0x0 0x3>;
cap-sd-highspeed;
cap-mmc-highspeed;
broken-cd;
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+21 -21
View File
@@ -60,6 +60,25 @@
};
};
firmware {
svc {
compatible = "intel,agilex-svc";
method = "smc";
memory-region = <&service_reserved>;
fpga_mgr: fpga-mgr {
compatible = "intel,agilex-soc-fpga-mgr";
};
};
};
fpga-region {
compatible = "fpga-region";
#address-cells = <0x2>;
#size-cells = <0x2>;
fpga-mgr = <&fpga_mgr>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
@@ -130,7 +149,7 @@
compatible = "usb-nop-xceiv";
};
soc {
soc@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -138,13 +157,6 @@
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
base_fpga_region {
#address-cells = <0x2>;
#size-cells = <0x2>;
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr>;
};
clkmgr: clock-controller@ffd10000 {
compatible = "intel,agilex-clkmgr";
reg = <0xffd10000 0x1000>;
@@ -368,7 +380,7 @@
pinctrl-single,function-mask = <0x0000000f>;
};
pinctrl1: pinconf@ffd13100 {
pinctrl1: pinctrl@ffd13100 {
compatible = "pinctrl-single";
#pinctrl-cells = <1>;
reg = <0xffd13100 0x20>;
@@ -659,17 +671,5 @@
status = "disabled";
};
firmware {
svc {
compatible = "intel,agilex-svc";
method = "smc";
memory-region = <&service_reserved>;
fpga_mgr: fpga-mgr {
compatible = "intel,agilex-soc-fpga-mgr";
};
};
};
};
};
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+2 -2
View File
@@ -73,7 +73,7 @@
ranges;
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells =<2>;
#size-cells = <2>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
@@ -315,7 +315,7 @@
num-cs = <4>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
dmas = <&dmac0 2>, <&dmac0 3>;
dma-names ="tx", "rx";
dma-names = "tx", "rx";
status = "disabled";
};
arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
+1 -1
View File
@@ -26,7 +26,7 @@
reg = <0 0x80000000 0 0>;
};
soc {
soc@0 {
bus@80000000 {
compatible = "simple-bus";
reg = <0x80000000 0x60000000>,
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
-2
View File
@@ -113,8 +113,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <2>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+1 -4
View File
@@ -25,12 +25,11 @@
reg = <0 0x80000000 0 0>;
};
soc {
soc@0 {
sdram_edac: memory-controller@f87f8000 {
compatible = "snps,ddrc-3.80a";
reg = <0xf87f8000 0x400>;
interrupts = <0 175 4>;
status = "okay";
};
};
};
@@ -91,8 +90,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <2>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;