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PCI: tegra: Configure L1 power save parameters

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Programmed bits of register RP_VEND_XP_PAD_PWRDN are defined as follows,

L1(bit[0]):
 This bit, when set, causes the analog pads to power down when we're in L1.
 When clear, the LTSSM still enters L1 as required, but the analog pads
 are left at full power.
DYNAMIC(bit[1]):
 This bit, when set, causes unused analog pads to power down after
 "Dynamic Link Width Re-negotiation" takes place.  When clear, all analog
 pads remain powered up, even those that are no longer being used after
 "Dynamic Link Width Re-negotiation" down-sizes the link.
DISABLED(bit[2]):
 This bit, when set, causes the analog pads to power down when we're in the
 DISABLED_DOWN state. When clear, the LTSSM still enters DISBLED_DOWN as
 required, but the analog pads are left at full power.
L1_CLKREQ(bit[15]):
 This bit, when set, causes the analog pads to power down to
 SLEEP_MODE_L1_REQ when clkreq signal is deasserted in L1.
 (NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1 needs to be set in order to power
 down pad in L1.)  Also, when clkreq is asserted in L1, ltssm will exit L1
 immediately. When clear, the clkreq signal doesn't affect the power
 management.
SLEEP_MODE_L1(bits[4:3]):
 It defines the 2-bit sleep-mode coding in the pad when LTSSM is in the L1
 state or DISABLED state.
SLEEP_MODE_DYNAMIC(bits[6:5]):
 It defines the 2-bit sleep-mode coding in the pad when the lane shut down
 due to dynamic link downsizing.
SLEEP_MODE_L1_CLKREQ(bits[17:16]):
 It defines the 2-bit sleep-mode coding when clkreq is deasserted in L1.
The 2-bit sleep-mode encoding is defined as:
 - L0 (0x0): Normal power-up mode
 - L1 (0x1): L1 power-down mode; Tx common mode on, Rx e-idle detect on
 - L1P (0x2): L1 power-down mode; Tx common mode off, Rx e-idle detect on
 - L1PP (0x3): L1 power-down mode; Tx common mode off, Rx e-idle detect off

bug 200420606

Change-Id: I74aa9c1460d882084b1ecccb9c0168dd667c9d84
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786547
(cherry picked from commit d7899c186f89ecf503812003b743adbae07c4cbe)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407873
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Manikanta Maddireddy
2018-07-16 16:00:29 +05:30
committed by Thomas Makin
parent dd0f08b513
commit 2b7a4256cc
1 changed files with 20 additions and 0 deletions
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20
drivers/pci/controller/pci-tegra.c
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@@ -231,6 +231,15 @@
#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD (0xf << 24)
#define RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE (1 << 31)
#define RP_VEND_XP_PAD_PWRDN 0x00000f50
#define RP_VEND_XP_PAD_PWRDN_L1_EN (1 << 0)
#define RP_VEND_XP_PAD_PWRDN_DYNAMIC_EN (1 << 1)
#define RP_VEND_XP_PAD_PWRDN_DISABLED_EN (1 << 2)
#define RP_VEND_XP_PAD_PWRDN_L1_CLKREQ_EN (1 << 15)
#define RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1PP (3 << 5)
#define RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1PP (3 << 3)
#define RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_CLKREQ_L1PP (3 << 16)
#define RP_LINK_CONTROL_STATUS 0x00000090
#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
@@ -622,6 +631,17 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
value = readl(port->base + RP_VEND_XP1);
value |= RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT;
writel(value, port->base + RP_VEND_XP1);
/* Power saving configuration for L1 sleep/idle */
value = readl(port->base + RP_VEND_XP_PAD_PWRDN);
value |= RP_VEND_XP_PAD_PWRDN_DISABLED_EN;
value |= RP_VEND_XP_PAD_PWRDN_DYNAMIC_EN;
value |= RP_VEND_XP_PAD_PWRDN_L1_EN;
value |= RP_VEND_XP_PAD_PWRDN_L1_CLKREQ_EN;
value |= RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1PP;
value |= RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1PP;
value |= RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_CLKREQ_L1PP;
writel(value, port->base + RP_VEND_XP_PAD_PWRDN);
}
}