soc: qcom: llcc: Enable LLCC_WRCACHE at boot on X1

commit 35d8bc131de0f0f280f0db42499512d79f05f456 upstream.

The Last Level Cache is split into many slices, each one of which can
be toggled on or off.

Only certain slices are recommended to be turned on unconditionally,
in order to reach optimal performance/latency/power levels.

Enable WRCACHE on X1 at boot, in accordance with internal
recommendations.

No significant performance difference is expected.

Fixes: b3cf69a435 ("soc: qcom: llcc: Add configuration data for X1E80100")
Cc: stable@vger.kernel.org
Reviewed-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241219-topic-llcc_x1e_wrcache-v3-1-b9848d9c3d63@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

This commit is contained in:

Konrad Dybcio

2024-12-19 19:53:29 +01:00

committed by

Greg Kroah-Hartman

parent 270d7917b0

commit 2153c78328

1 changed files with 1 additions and 0 deletions

									
										drivers/soc/qcom/llcc-qcom.c
									
		+1
		
												View File
												
				@@ -2511,6 +2511,7 @@ static const struct llcc_slice_config x1e80100_data[] = {

						.fixed_size = true,

						.bonus_ways = 0xfff,

						.cache_mode = 0,

						.activate_on_init = true,

					}, {

						.usecase_id = LLCC_CAMEXP0,

						.slice_id = 4,