Merge tag 'timers-v6.2-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clockevent/source driver updates from Daniel Lezcano:
- Add DT bindings for the Rockchip rk3128 timer (Johan Jonker)
- Change the DT bindings for the npcm7xx timer in order to specify
multiple clocks and enable the clock for the timer1 on WPCM450
(Jonathan Neuschäfer)
- Fix the timer duration being too long the ARM architected timer in
order to prevent an integer overflow leading to a negative value and
an immediate interruption (Joe Korty)
- Fix an unused pointer warning reported by lkp and some cleanups in
the timer TI dm (Tony Lindgren)
- Fix a missing call to clk_disable_unprepare() in the error path at
init time on the timer TI dm (Yang Yingliang)
- Use kstrtobool() instead of strtobool() in the ARM architected timer
(Christophe JAILLET)
- Add DT bindings for r8a779g0 on Renesas platform (Wolfram Sang)
Link: https://lore.kernel.org/all/3c4c3bb2-b849-0c87-0948-8a36984bdde4@linaro.org
This commit is contained in:
@@ -25,7 +25,13 @@ properties:
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- description: The timer interrupt of timer 0
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clocks:
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maxItems: 1
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items:
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- description: The reference clock for timer 0
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- description: The reference clock for timer 1
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- description: The reference clock for timer 2
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- description: The reference clock for timer 3
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- description: The reference clock for timer 4
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minItems: 1
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required:
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- compatible
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@@ -102,12 +102,14 @@ properties:
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- enum:
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- renesas,r8a779a0-cmt0 # 32-bit CMT0 on R-Car V3U
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- renesas,r8a779f0-cmt0 # 32-bit CMT0 on R-Car S4-8
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- renesas,r8a779g0-cmt0 # 32-bit CMT0 on R-Car V4H
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- const: renesas,rcar-gen4-cmt0 # 32-bit CMT0 on R-Car Gen4
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- items:
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- enum:
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- renesas,r8a779a0-cmt1 # 48-bit CMT on R-Car V3U
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- renesas,r8a779f0-cmt1 # 48-bit CMT on R-Car S4-8
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- renesas,r8a779g0-cmt1 # 48-bit CMT on R-Car V4H
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- const: renesas,rcar-gen4-cmt1 # 48-bit CMT on R-Car Gen4
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reg:
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@@ -38,6 +38,7 @@ properties:
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- renesas,tmu-r8a77995 # R-Car D3
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- renesas,tmu-r8a779a0 # R-Car V3U
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- renesas,tmu-r8a779f0 # R-Car S4-8
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- renesas,tmu-r8a779g0 # R-Car V4H
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- const: renesas,tmu
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reg:
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@@ -18,6 +18,7 @@ properties:
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- enum:
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- rockchip,rv1108-timer
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- rockchip,rk3036-timer
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- rockchip,rk3128-timer
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- rockchip,rk3188-timer
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- rockchip,rk3228-timer
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- rockchip,rk3229-timer
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@@ -18,6 +18,7 @@
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#include <linux/clocksource.h>
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#include <linux/clocksource_ids.h>
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#include <linux/interrupt.h>
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#include <linux/kstrtox.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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@@ -97,7 +98,7 @@ static bool evtstrm_enable __ro_after_init = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EV
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static int __init early_evtstrm_cfg(char *buf)
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{
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return strtobool(buf, &evtstrm_enable);
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return kstrtobool(buf, &evtstrm_enable);
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}
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early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
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@@ -806,6 +807,9 @@ static u64 __arch_timer_check_delta(void)
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/*
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* XGene-1 implements CVAL in terms of TVAL, meaning
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* that the maximum timer range is 32bit. Shame on them.
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*
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* Note that TVAL is signed, thus has only 31 of its
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* 32 bits to express magnitude.
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*/
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MIDR_ALL_VERSIONS(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,
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APM_CPU_PART_POTENZA)),
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@@ -813,8 +817,8 @@ static u64 __arch_timer_check_delta(void)
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};
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if (is_midr_in_range_list(read_cpuid_id(), broken_cval_midrs)) {
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pr_warn_once("Broken CNTx_CVAL_EL1, limiting width to 32bits");
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return CLOCKSOURCE_MASK(32);
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pr_warn_once("Broken CNTx_CVAL_EL1, using 32 bit TVAL instead.\n");
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return CLOCKSOURCE_MASK(31);
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}
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#endif
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return CLOCKSOURCE_MASK(arch_counter_get_width());
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@@ -188,6 +188,7 @@ static void __init npcm7xx_clocksource_init(void)
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static int __init npcm7xx_timer_init(struct device_node *np)
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{
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struct clk *clk;
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int ret;
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ret = timer_of_init(np, &npcm7xx_to);
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@@ -199,6 +200,15 @@ static int __init npcm7xx_timer_init(struct device_node *np)
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npcm7xx_to.of_clk.rate = npcm7xx_to.of_clk.rate /
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(NPCM7XX_Tx_MIN_PRESCALE + 1);
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/* Enable the clock for timer1, if it exists */
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clk = of_clk_get(np, 1);
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if (clk) {
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if (!IS_ERR(clk))
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clk_prepare_enable(clk);
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else
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pr_warn("%pOF: Failed to get clock for timer1: %pe", np, clk);
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}
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npcm7xx_clocksource_init();
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npcm7xx_clockevents_init();
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@@ -345,8 +345,10 @@ static int __init dmtimer_systimer_init_clock(struct dmtimer_systimer *t,
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return error;
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r = clk_get_rate(clock);
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if (!r)
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if (!r) {
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clk_disable_unprepare(clock);
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return -ENODEV;
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}
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if (is_ick)
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t->ick = clock;
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@@ -633,6 +633,8 @@ static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *n
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static int omap_dm_timer_free(struct omap_dm_timer *cookie)
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{
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struct dmtimer *timer;
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struct device *dev;
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int rc;
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timer = to_dmtimer(cookie);
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if (unlikely(!timer))
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@@ -640,10 +642,21 @@ static int omap_dm_timer_free(struct omap_dm_timer *cookie)
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WARN_ON(!timer->reserved);
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timer->reserved = 0;
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dev = &timer->pdev->dev;
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rc = pm_runtime_resume_and_get(dev);
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if (rc)
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return rc;
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/* Clear timer configuration */
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dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
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pm_runtime_put_sync(dev);
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return 0;
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}
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int omap_dm_timer_get_irq(struct omap_dm_timer *cookie)
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static int omap_dm_timer_get_irq(struct omap_dm_timer *cookie)
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{
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struct dmtimer *timer = to_dmtimer(cookie);
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if (timer)
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@@ -1135,6 +1148,10 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
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goto err_disable;
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}
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__omap_dm_timer_init_regs(timer);
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/* Clear timer configuration */
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dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
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pm_runtime_put(dev);
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}
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@@ -1258,7 +1275,7 @@ static struct platform_driver omap_dm_timer_driver = {
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.remove = omap_dm_timer_remove,
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.driver = {
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.name = "omap_timer",
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.of_match_table = of_match_ptr(omap_timer_match),
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.of_match_table = omap_timer_match,
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.pm = &omap_dm_timer_pm_ops,
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},
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};
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@@ -62,8 +62,6 @@
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struct omap_dm_timer {
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};
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int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
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u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
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/*
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