tmakin/ack-tegra
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge a940d9a43e ("Merge tag 'soc-arm-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc") into android-mainline

Browse Source 
Steps on the way to 6.12-rc1

Bug: 367265496
Change-Id: Icab83c4e515d6482f6f506f3cd2c0032a85e7207
Signed-off-by: Matthias Maennich <maennich@google.com>
This commit is contained in:
Matthias Maennich
2024-09-25 09:06:49 +00:00
parent f3a29e7eb6 a940d9a43e
commit 16b2568505
987 changed files with 53494 additions and 12532 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
+12 -4
View File
@@ -25,10 +25,18 @@ select:
properties:
compatible:
items:
- const: amlogic,meson-gx-ao-secure
- const: syscon
oneOf:
- items:
- const: amlogic,meson-gx-ao-secure
- const: syscon
- items:
- enum:
- amlogic,a4-ao-secure
- amlogic,c3-ao-secure
- amlogic,s4-ao-secure
- amlogic,t7-ao-secure
- const: amlogic,meson-gx-ao-secure
- const: syscon
reg:
maxItems: 1
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+3
View File
@@ -79,6 +79,7 @@ properties:
- aspeed,ast2600-evb-a1
- asus,x4tf-bmc
- facebook,bletchley-bmc
- facebook,catalina-bmc
- facebook,cloudripper-bmc
- facebook,elbert-bmc
- facebook,fuji-bmc
@@ -86,7 +87,9 @@ properties:
- facebook,harma-bmc
- facebook,minerva-cmc
- facebook,yosemite4-bmc
- ibm,blueridge-bmc
- ibm,everest-bmc
- ibm,fuji-bmc
- ibm,rainier-bmc
- ibm,system1-bmc
- ibm,tacoma-bmc
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+4 -2
View File
@@ -11,7 +11,8 @@ PIT Timer required properties:
shared across all System Controller members.
PIT64B Timer required properties:
- compatible: Should be "microchip,sam9x60-pit64b"
- compatible: Should be "microchip,sam9x60-pit64b" or
"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for PIT64B timer
- clocks: Should contain the available clock sources for PIT64B timer.
@@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties:
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
"microchip,sam9x60-ddramc",
"microchip,sama7g5-uddrc"
"microchip,sama7g5-uddrc",
"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
- reg: Should contain registers location and length
Examples:
Documentation/devicetree/bindings/arm/fsl.yaml
+28 -10
View File
@@ -809,19 +809,19 @@ properties:
- const: kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM
- const: fsl,imx6ull
- description: TQ Systems TQMa6ULLx SoM on MBa6ULx board
- description: TQ-Systems TQMa6ULLx SoM on MBa6ULx board
items:
- enum:
- tq,imx6ull-tqma6ull2-mba6ulx
- const: tq,imx6ull-tqma6ull2 # MCIMX6Y2
- tq,imx6ull-tqma6ull2-mba6ulx # TQMa6ULL socketable SoM with MCIMX6Y2 on MBa6ULx EVK
- const: tq,imx6ull-tqma6ull2 # TQMa6ULL socketable SoM with MCIMX6Y2
- const: fsl,imx6ull
- description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board
- description: TQ-Systems TQMa6ULLxL SoM on MBa6ULx[L] board
items:
- enum:
- tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter
- tq,imx6ull-tqma6ull2l-mba6ulxl
- const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant
- tq,imx6ull-tqma6ull2l-mba6ulx # TQMa6ULLxL LGA SoM with socketable Adapter on MBa6ULx EVK
- tq,imx6ull-tqma6ull2l-mba6ulxl # TQMa6ULLxL LGA SoM on MBa6ULxL gateway board
- const: tq,imx6ull-tqma6ull2l # TQMa6ULLxL LGA SoM with MCIMX6Y2
- const: fsl,imx6ull
- description: Seeed Stuido i.MX6ULL SoM on dev boards
@@ -939,8 +939,8 @@ properties:
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
- fsl,imx8mm-evkb # i.MX8MM EVKB Board
- gateworks,imx8mm-gw75xx-0x # i.MX8MM Gateworks Board
- gateworks,imx8mm-gw7904
- gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
@@ -953,7 +953,6 @@ properties:
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
- const: fsl,imx8mm
@@ -1082,7 +1081,7 @@ properties:
- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
@@ -1168,6 +1167,12 @@ properties:
- const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
- const: fsl,imx8mp
- description: Variscite VAR-SOM-MX8M Plus based boards
items:
- const: variscite,var-som-mx8mp-symphony
- const: variscite,var-som-mx8mp
- const: fsl,imx8mp
- description: i.MX8MQ based Boards
items:
- enum:
@@ -1293,6 +1298,7 @@ properties:
- enum:
- fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
- fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board
- const: fsl,imx93
- description: i.MX95 based Boards
@@ -1344,6 +1350,12 @@ properties:
- const: variscite,var-som-mx93
- const: fsl,imx93
- description: Kontron OSM-S i.MX93 SoM based boards
items:
- const: kontron,imx93-bl-osm-s # Kontron BL i.MX93 OSM-S board
- const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM
- const: fsl,imx93
- description:
Freescale Vybrid Platform Device Tree Bindings
@@ -1523,6 +1535,12 @@ properties:
- fsl,ls2080a-rdb
- const: fsl,ls2080a
- description: LS2081A based Boards
items:
- enum:
- fsl,ls2081a-rdb
- const: fsl,ls2081a
- description: LS2088A based Boards
items:
- enum:
Documentation/devicetree/bindings/arm/qcom.yaml
+19
View File
@@ -155,6 +155,11 @@ properties:
- const: qcom,msm8926
- const: qcom,msm8226
- items:
- enum:
- wingtech,wt82918hd
- const: qcom,msm8929
- items:
- enum:
- huawei,kiwi
@@ -162,6 +167,8 @@ properties:
- samsung,a7
- sony,kanuti-tulip
- square,apq8039-t2
- wingtech,wt82918
- wingtech,wt82918hdhw39
- const: qcom,msm8939
- items:
@@ -228,12 +235,15 @@ properties:
- samsung,grandprimelte
- samsung,gt510
- samsung,gt58
- samsung,j3ltetw
- samsung,j5
- samsung,j5x
- samsung,rossa
- samsung,serranove
- thwc,uf896
- thwc,ufi001c
- wingtech,wt86518
- wingtech,wt86528
- wingtech,wt88047
- yiming,uz801-v3
- const: qcom,msm8916
@@ -250,6 +260,7 @@ properties:
- items:
- enum:
- lg,bullhead
- lg,h815
- microsoft,talkman
- xiaomi,libra
- const: qcom,msm8992
@@ -1038,10 +1049,18 @@ properties:
- qcom,sm8650-qrd
- const: qcom,sm8650
- items:
- enum:
- lenovo,thinkpad-t14s
- const: qcom,x1e78100
- const: qcom,x1e80100
- items:
- enum:
- asus,vivobook-s15
- lenovo,yoga-slim7x
- microsoft,romulus13
- microsoft,romulus15
- qcom,x1e80100-crd
- qcom,x1e80100-qcp
- const: qcom,x1e80100
Documentation/devicetree/bindings/arm/rockchip.yaml
+39 -3
View File
@@ -96,6 +96,13 @@ properties:
- const: coolpi,pi-cm5
- const: rockchip,rk3588
- description: Cool Pi CM5 GenBook
items:
- enum:
- coolpi,pi-cm5-genbook
- const: coolpi,pi-cm5
- const: rockchip,rk3588
- description: Cool Pi 4 Model B
items:
- const: coolpi,pi-4b
@@ -148,6 +155,12 @@ properties:
- const: engicam,px30-core
- const: rockchip,px30
- description: Firefly Core-PX30-JD4 on MB-JD4-PX30 baseboard
items:
- const: firefly,px30-jd4-core-mb
- const: firefly,px30-jd4-core
- const: rockchip,px30
- description: Firefly Firefly-RK3288
items:
- enum:
@@ -216,6 +229,7 @@ properties:
- friendlyarm,nanopi-r2c
- friendlyarm,nanopi-r2c-plus
- friendlyarm,nanopi-r2s
- friendlyarm,nanopi-r2s-plus
- const: rockchip,rk3328
- description: FriendlyElec NanoPi4 series boards
@@ -243,9 +257,11 @@ properties:
- friendlyarm,nanopi-r6s
- const: rockchip,rk3588s
- description: FriendlyElec NanoPC T6
- description: FriendlyElec NanoPC T6 series boards
items:
- const: friendlyarm,nanopc-t6
- enum:
- friendlyarm,nanopc-t6
- friendlyarm,nanopc-t6-lts
- const: rockchip,rk3588
- description: FriendlyElec CM3588-based boards
@@ -255,6 +271,11 @@ properties:
- const: friendlyarm,cm3588
- const: rockchip,rk3588
- description: GameForce Ace
items:
- const: gameforce,ace
- const: rockchip,rk3588s
- description: GameForce Chi
items:
- const: gameforce,chi
@@ -581,9 +602,19 @@ properties:
- description: Hardkernel Odroid M1
items:
- const: rockchip,rk3568-odroid-m1
- const: hardkernel,odroid-m1
- const: rockchip,rk3568
- description: Hardkernel Odroid M1S
items:
- const: hardkernel,odroid-m1s
- const: rockchip,rk3566
- description: Hardkernel Odroid M2
items:
- const: hardkernel,odroid-m2
- const: rockchip,rk3588s
- description: Hugsun X99 TV Box
items:
- const: hugsun,x99
@@ -622,6 +653,11 @@ properties:
- const: leez,p710
- const: rockchip,rk3399
- description: LCKFB Taishan Pi RK3566
items:
- const: lckfb,tspi-rk3566
- const: rockchip,rk3566
- description: Lunzn FastRhino R66S / R68S
items:
- enum:
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
+2
View File
@@ -26,6 +26,7 @@ select:
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- rockchip,rk3576-pmu
- rockchip,rk3588-pmu
- rockchip,rv1126-pmu
@@ -43,6 +44,7 @@ properties:
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- rockchip,rk3576-pmu
- rockchip,rk3588-pmu
- rockchip,rv1126-pmu
- const: syscon
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+8
View File
@@ -54,6 +54,8 @@ properties:
- description: ST STM32MP151 based Boards
items:
- enum:
- prt,mecio1r0 # Protonic MECIO1r0
- prt,mect1s # Protonic MECT1S
- prt,prtt1a # Protonic PRTT1A
- prt,prtt1c # Protonic PRTT1C
- prt,prtt1s # Protonic PRTT1S
@@ -71,6 +73,12 @@ properties:
- const: dh,stm32mp151a-dhcor-som
- const: st,stm32mp151
- description: ST STM32MP153 based Boards
items:
- enum:
- prt,mecio1r1 # Protonic MECIO1r1
- const: st,stm32mp153
- description: DH STM32MP153 DHCOM SoM based Boards
items:
- const: dh,stm32mp153c-dhcom-drc02
Documentation/devicetree/bindings/arm/sunxi.yaml
+7 -2
View File
@@ -61,14 +61,19 @@ properties:
- const: anbernic,rg35xx-2024
- const: allwinner,sun50i-h700
- description: Anbernic RG35XX H
items:
- const: anbernic,rg35xx-h
- const: allwinner,sun50i-h700
- description: Anbernic RG35XX Plus
items:
- const: anbernic,rg35xx-plus
- const: allwinner,sun50i-h700
- description: Anbernic RG35XX H
- description: Anbernic RG35XX SP
items:
- const: anbernic,rg35xx-h
- const: anbernic,rg35xx-sp
- const: allwinner,sun50i-h700
- description: Amarula A64 Relic
Documentation/devicetree/bindings/arm/tegra.yaml
+42
View File
@@ -127,6 +127,48 @@ properties:
- nvidia,norrin
- const: nvidia,tegra132
- const: nvidia,tegra124
- items:
- const: google,nyan-blaze-rev10
- const: google,nyan-blaze-rev9
- const: google,nyan-blaze-rev8
- const: google,nyan-blaze-rev7
- const: google,nyan-blaze-rev6
- const: google,nyan-blaze-rev5
- const: google,nyan-blaze-rev4
- const: google,nyan-blaze-rev3
- const: google,nyan-blaze-rev2
- const: google,nyan-blaze-rev1
- const: google,nyan-blaze-rev0
- const: google,nyan-blaze
- const: google,nyan
- const: nvidia,tegra124
- items:
- const: google,nyan-big-rev10
- const: google,nyan-big-rev9
- const: google,nyan-big-rev8
- const: google,nyan-big-rev7
- const: google,nyan-big-rev6
- const: google,nyan-big-rev5
- const: google,nyan-big-rev4
- const: google,nyan-big-rev3
- const: google,nyan-big-rev2
- const: google,nyan-big-rev1
- const: google,nyan-big-rev0
- const: google,nyan-big
- const: google,nyan
- const: nvidia,tegra124
- items:
- const: google,nyan-big-rev7
- const: google,nyan-big-rev6
- const: google,nyan-big-rev5
- const: google,nyan-big-rev4
- const: google,nyan-big-rev3
- const: google,nyan-big-rev2
- const: google,nyan-big-rev1
- const: google,nyan-big-rev0
- const: google,nyan-big
- const: google,nyan
- const: nvidia,tegra124
- items:
- enum:
- nvidia,darcy
Documentation/devicetree/bindings/arm/ti/k3.yaml
+1
View File
@@ -140,6 +140,7 @@ properties:
- description: K3 J722S SoC and Boards
items:
- enum:
- beagle,am67a-beagley-ai
- ti,j722s-evm
- const: ti,j722s
Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
+5 -2
View File
@@ -24,11 +24,13 @@ properties:
items:
- description: input top pll
- description: input mclk pll
- description: input fix pll
clock-names:
items:
- const: top
- const: mclk
- const: fix
"#clock-cells":
const: 1
@@ -52,8 +54,9 @@ examples:
compatible = "amlogic,c3-pll-clkc";
reg = <0x0 0x8000 0x0 0x1a4>;
clocks = <&scmi_clk 2>,
<&scmi_clk 5>;
clock-names = "top", "mclk";
<&scmi_clk 5>,
<&scmi_clk 12>;
clock-names = "top", "mclk", "fix";
#clock-cells = <1>;
};
};
Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
+2
View File
@@ -31,6 +31,8 @@ properties:
- description: USB PCIE wrapper pipe clock source
'#power-domain-cells': false
'#interconnect-cells':
const: 1
required:
- compatible
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
+1 -1
View File
@@ -139,7 +139,7 @@ examples:
- |
rpm {
rpm-requests {
compatible = "qcom,rpm-msm8916";
compatible = "qcom,rpm-msm8916", "qcom,smd-rpm";
qcom,smd-channels = "rpm_requests";
clock-controller {
Documentation/devicetree/bindings/clock/qcom,sm4450-camcc.yaml
+63
View File
@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
properties:
compatible:
const: qcom,sm4450-camcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Camera AHB clock source from GCC
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@ade0000 {
compatible = "qcom,sm4450-camcc";
reg = <0x0ade0000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml
+71
View File
@@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
properties:
compatible:
const: qcom,sm4450-dispcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Display AHB clock source from GCC
- description: sleep clock source
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@af00000 {
compatible = "qcom,sm4450-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy_pll_out_byteclk>,
<&dsi0_phy_pll_out_dsiclk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/qcom,sm8150-camcc.yaml
+77
View File
@@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM8150
maintainers:
- Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and
power domains on SM8150.
See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
properties:
compatible:
const: qcom,sm8150-camcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Camera AHB clock from GCC
power-domains:
maxItems: 1
description:
A phandle and PM domain specifier for the MMCX power domain.
required-opps:
maxItems: 1
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@ad00000 {
compatible = "qcom,sm8150-camcc";
reg = <0x0ad00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>;
power-domains = <&rpmhpd SM8150_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+2
View File
@@ -14,6 +14,7 @@ description: |
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,sm4450-gpucc.h
include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
@@ -23,6 +24,7 @@ description: |
properties:
compatible:
enum:
- qcom,sm4450-gpucc
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
+80
View File
@@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
and control of clock signals for the IP modules, generation and control of resets,
and control over booting, low power consumption and power supply domains.
properties:
compatible:
const: renesas,r9a09g057-cpg
reg:
maxItems: 1
clocks:
items:
- description: AUDIO_EXTAL clock input
- description: RTXIN clock input
- description: QEXTAL clock input
clock-names:
items:
- const: audio_extal
- const: rtxin
- const: qextal
'#clock-cells':
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number. The module number is calculated as the CLKON register
offset index multiplied by 16, plus the actual bit in the register
used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
calculation is (1 * 16 + 3) = 0x13.
const: 2
'#power-domain-cells':
const: 0
'#reset-cells':
description:
The single reset specifier cell must be the reset number. The reset number
is calculated as the reset register offset index multiplied by 16, plus the
actual bit in the register used to reset the specific IP block. For example,
for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
clock-controller@10420000 {
compatible = "renesas,r9a09g057-cpg";
reg = <0x10420000 0x10000>;
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
clock-names = "audio_extal", "rtxin", "qextal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
+19
View File
@@ -35,6 +35,7 @@ properties:
- samsung,exynosautov9-cmu-top
- samsung,exynosautov9-cmu-busmc
- samsung,exynosautov9-cmu-core
- samsung,exynosautov9-cmu-dpum
- samsung,exynosautov9-cmu-fsys0
- samsung,exynosautov9-cmu-fsys1
- samsung,exynosautov9-cmu-fsys2
@@ -109,6 +110,24 @@ allOf:
- const: oscclk
- const: dout_clkcmu_core_bus
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-dpum
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: DPU Main bus clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- if:
properties:
compatible:
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
+162
View File
@@ -0,0 +1,162 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung ExynosAuto v920 SoC clock controller
maintainers:
- Sunyeal Hong <sunyeal.hong@samsung.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
description: |
ExynosAuto v920 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. Root clocks in that clock tree are
two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
The external OSCCLK must be defined as fixed-rate clock in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other clocks of function blocks (other CMUs) are usually
derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'include/dt-bindings/clock/samsung,exynosautov920.h' header.
properties:
compatible:
enum:
- samsung,exynosautov920-cmu-top
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
- samsung,exynosautov920-cmu-misc
- samsung,exynosautov920-cmu-hsi0
- samsung,exynosautov920-cmu-hsi1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
"#clock-cells":
const: 1
reg:
maxItems: 1
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynosautov920-cmu-top
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
clock-names:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
enum:
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_PERICn NOC clock (from CMU_TOP)
- description: CMU_PERICn IP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- const: ip
- if:
properties:
compatible:
enum:
- samsung,exynosautov920-cmu-misc
- samsung,exynosautov920-cmu-hsi0
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- if:
properties:
compatible:
contains:
const: samsung,exynosautov920-cmu-hsi1
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_HSI1 NOC clock (from CMU_TOP)
- description: CMU_HSI1 USBDRD clock (from CMU_TOP)
- description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- const: usbdrd
- const: mmc_card
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
- reg
additionalProperties: false
examples:
# Clock controller node for CMU_PERIC0
- |
#include <dt-bindings/clock/samsung,exynosautov920.h>
cmu_peric0: clock-controller@10800000 {
compatible = "samsung,exynosautov920-cmu-peric0";
reg = <0x10800000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
clock-names = "oscclk",
"noc",
"ip";
};
...
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
+19 -1
View File
@@ -22,6 +22,9 @@ description: |
[0] https://developer.arm.com/documentation/den0056/latest
anyOf:
- $ref: /schemas/firmware/nxp,imx95-scmi.yaml
properties:
$nodename:
const: scmi
@@ -121,6 +124,13 @@ properties:
atomic mode of operation, even if requested.
default: 0
max-rx-timeout-ms:
description:
An optional time value, expressed in milliseconds, representing the
transport maximum timeout value for the receive channel. The value should
be a non-zero value if set.
minimum: 1
arm,smc-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
@@ -145,6 +155,14 @@ properties:
required:
- '#power-domain-cells'
protocol@12:
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x12
protocol@13:
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
@@ -284,7 +302,7 @@ properties:
required:
- reg
additionalProperties: false
unevaluatedProperties: false
$defs:
protocol-node:
Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml
+43
View File
@@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2024 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/nxp,imx95-scmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX95 System Control and Management Interface(SCMI) Vendor Protocols Extension
maintainers:
- Peng Fan <peng.fan@nxp.com>
properties:
protocol@81:
$ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x81
protocol@84:
$ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x84
nxp,ctrl-ids:
description:
Each entry consists of 2 integers, represents the ctrl id and the value
items:
items:
- description: the ctrl id index
enum: [0, 1, 2, 3, 4, 5, 6, 7, 0x8000, 0x8001, 0x8002, 0x8003,
0x8004, 0x8005, 0x8006, 0x8007]
- description: the value assigned to the ctrl id
minItems: 1
maxItems: 16
$ref: /schemas/types.yaml#/definitions/uint32-matrix
additionalProperties: true
Documentation/devicetree/bindings/iio/adc/adi,ad4000.yaml
+197
View File
@@ -0,0 +1,197 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/adi,ad4000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD4000 and similar Analog to Digital Converters
maintainers:
- Marcelo Schmitt <marcelo.schmitt@analog.com>
description: |
Analog Devices AD4000 family of Analog to Digital Converters with SPI support.
Specifications can be found at:
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4000-4004-4008.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4001-4005.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4002-4006-4010.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4003-4007-4011.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4020-4021-4022.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4001.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4003.pdf
$ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
oneOf:
- const: adi,ad4000
- items:
- enum:
- adi,ad4004
- adi,ad4008
- const: adi,ad4000
- const: adi,ad4001
- items:
- enum:
- adi,ad4005
- const: adi,ad4001
- const: adi,ad4002
- items:
- enum:
- adi,ad4006
- adi,ad4010
- const: adi,ad4002
- const: adi,ad4003
- items:
- enum:
- adi,ad4007
- adi,ad4011
- const: adi,ad4003
- const: adi,ad4020
- items:
- enum:
- adi,ad4021
- adi,ad4022
- const: adi,ad4020
- const: adi,adaq4001
- const: adi,adaq4003
reg:
maxItems: 1
spi-max-frequency:
maximum: 102040816 # for VIO > 2.7 V, 81300813 for VIO > 1.7 V
adi,sdi-pin:
$ref: /schemas/types.yaml#/definitions/string
enum: [ high, low, cs, sdi ]
default: sdi
description:
Describes how the ADC SDI pin is wired. A value of "sdi" indicates that
the ADC SDI is connected to host SDO. "high" indicates that the ADC SDI
pin is hard-wired to logic high (VIO). "low" indicates that it is
hard-wired low (GND). "cs" indicates that the ADC SDI pin is connected to
the host CS line.
'#daisy-chained-devices': true
vdd-supply:
description: A 1.8V supply that powers the chip (VDD).
vio-supply:
description:
A 1.8V to 5.5V supply for the digital inputs and outputs (VIO).
ref-supply:
description:
A 2.5 to 5V supply for the external reference voltage (REF).
cnv-gpios:
description:
When provided, this property indicates the GPIO that is connected to the
CNV pin.
maxItems: 1
adi,high-z-input:
type: boolean
description:
High-Z mode allows the amplifier and RC filter in front of the ADC to be
chosen based on the signal bandwidth of interest, rather than the settling
requirements of the switched capacitor SAR ADC inputs.
adi,gain-milli:
description: |
The hardware gain applied to the ADC input (in milli units).
The gain provided by the ADC input scaler is defined by the hardware
connections between chip pins OUT+, R1K-, R1K1-, R1K+, R1K1+, and OUT-.
If not present, default to 1000 (no actual gain applied).
$ref: /schemas/types.yaml#/definitions/uint16
enum: [454, 909, 1000, 1900]
default: 1000
interrupts:
description:
The SDO pin can also function as a busy indicator. This node should be
connected to an interrupt that is triggered when the SDO line goes low
while the SDI line is high and the CNV line is low ("3-wire" mode) or the
SDI line is low and the CNV line is high ("4-wire" mode); or when the SDO
line goes high while the SDI and CNV lines are high (chain mode),
maxItems: 1
required:
- compatible
- reg
- vdd-supply
- vio-supply
- ref-supply
allOf:
# The configuration register can only be accessed if SDI is connected to MOSI
- if:
required:
- adi,sdi-pin
then:
properties:
adi,high-z-input: false
# chain mode has lower SCLK max rate
- if:
required:
- '#daisy-chained-devices'
then:
properties:
spi-max-frequency:
maximum: 50000000 # for VIO > 2.7 V, 40000000 for VIO > 1.7 V
# Gain property only applies to ADAQ devices
- if:
properties:
compatible:
not:
contains:
enum:
- adi,adaq4001
- adi,adaq4003
then:
properties:
adi,gain-milli: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
adc@0 {
compatible = "adi,ad4020";
reg = <0>;
spi-max-frequency = <71000000>;
vdd-supply = <&supply_1_8V>;
vio-supply = <&supply_1_8V>;
ref-supply = <&supply_5V>;
adi,sdi-pin = "cs";
cnv-gpios = <&gpio0 88 GPIO_ACTIVE_HIGH>;
};
};
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
adc@0 {
compatible = "adi,adaq4003";
reg = <0>;
spi-max-frequency = <80000000>;
vdd-supply = <&supply_1_8V>;
vio-supply = <&supply_1_8V>;
ref-supply = <&supply_5V>;
adi,high-z-input;
adi,gain-milli = /bits/ 16 <454>;
};
};
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt
-37
View File
@@ -1,37 +0,0 @@
BCM2836 per-CPU interrupt controller
The BCM2836 has a per-cpu interrupt controller for the timer, PMU
events, and SMP IPIs. One of the CPUs may receive interrupts for the
peripheral (GPU) events, which chain to the BCM2835-style interrupt
controller.
Required properties:
- compatible: Should be "brcm,bcm2836-l1-intc"
- reg: Specifies base physical address and size of the
registers
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value shall be 2
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
The interrupt sources are as follows:
0: CNTPSIRQ
1: CNTPNSIRQ
2: CNTHPIRQ
3: CNTVIRQ
8: GPU_FAST
9: PMU_FAST
Example:
local_intc: local_intc {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&local_intc>;
};
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.yaml
+51
View File
@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2836-l1-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: BCM2836 per-CPU interrupt controller
maintainers:
- Stefan Wahren <wahrenst@gmx.net>
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
description:
The BCM2836 has a per-cpu interrupt controller for the timer, PMU
events, and SMP IPIs. One of the CPUs may receive interrupts for the
peripheral (GPU) events, which chain to the BCM2835-style interrupt
controller.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
const: brcm,bcm2836-l1-intc
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
local_intc: interrupt-controller@40000000 {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&local_intc>;
};
...
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+1
View File
@@ -67,6 +67,7 @@ properties:
- allwinner,sun20i-d1-plic
- sophgo,cv1800b-plic
- sophgo,cv1812h-plic
- sophgo,sg2002-plic
- sophgo,sg2042-plic
- thead,th1520-plic
- const: thead,c900-plic
Documentation/devicetree/bindings/media/s5p-mfc.txt
View File
Documentation/devicetree/bindings/memory-controllers/fsl/fsl,imx-weim.yaml
+11 -14
View File
@@ -134,9 +134,8 @@ allOf:
properties:
fsl,weim-cs-timing:
items:
items:
- description: CSxU
- description: CSxL
- description: CSxU
- description: CSxL
- if:
properties:
compatible:
@@ -151,10 +150,9 @@ allOf:
properties:
fsl,weim-cs-timing:
items:
items:
- description: CSCRxU
- description: CSCRxL
- description: CSCRxA
- description: CSCRxU
- description: CSCRxL
- description: CSCRxA
- if:
properties:
compatible:
@@ -171,13 +169,12 @@ allOf:
properties:
fsl,weim-cs-timing:
items:
items:
- description: CSxGCR1
- description: CSxGCR2
- description: CSxRCR1
- description: CSxRCR2
- description: CSxWCR1
- description: CSxWCR2
- description: CSxGCR1
- description: CSxGCR2
- description: CSxRCR1
- description: CSxRCR2
- description: CSxWCR1
- description: CSxWCR2
additionalProperties: false
Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
+3 -1
View File
@@ -67,7 +67,9 @@ properties:
- const: dirmap
- const: wbuf
clocks: true
clocks:
minItems: 1
maxItems: 2
interrupts:
maxItems: 1
Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
+1 -1
View File
@@ -274,7 +274,7 @@ properties:
Defines the work frequency of DC-DC in kHz.
patternProperties:
"^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo)$":
"^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo|boost)$":
$ref: /schemas/regulator/regulator.yaml#
type: object
unevaluatedProperties: false
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
-178
View File
@@ -1,178 +0,0 @@
* Atmel AT91 Pinmux Controller
The AT91 Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
8 muxing options (called periph modes). Since different modules require
different PAD settings (like pull up, keeper, etc) the controller controls
also the PAD settings parameters.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Atmel AT91 pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and config
of the pins in that group. The 'pins' selects the function mode(also named pin
mode) this pin can work on and the 'config' configures various pad settings
such as pull-up, multi drive, etc.
Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
How to create such array:
Each column will represent the possible peripheral of the pinctrl
Each line will represent a pio bank
Take an example on the 9260
Peripheral: 2 ( A and B)
Bank: 3 (A, B and C)
=>
/* A B */
0xffffffff 0xffc00c3b /* pioA */
0xffffffff 0x7fff3ccf /* pioB */
0xffffffff 0x007fffff /* pioC */
For each peripheral/bank we will describe in a u32 if a pin can be
configured in it by putting 1 to the pin bit (1 << pin)
Let's take the pioA on peripheral B
From the datasheet Table 10-2.
Peripheral B
PA0 MCDB0
PA1 MCCDB
PA2
PA3 MCDB3
PA4 MCDB2
PA5 MCDB1
PA6
PA7
PA8
PA9
PA10 ETX2
PA11 ETX3
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22 ETXER
PA23 ETX2
PA24 ETX3
PA25 ERX2
PA26 ERX3
PA27 ERXCK
PA28 ECRS
PA29 ECOL
PA30 RXD4
PA31 TXD4
=> 0xffc00c3b
Required properties for pin configuration node:
- atmel,pins: 4 integers array, represents a group of pins mux and config
setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
Bits used for CONFIG:
PULL_UP (1 << 0): indicate this pin needs a pull up.
MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
Multi-drive is equivalent to open-drain type output.
DEGLITCH (1 << 2): indicate this pin needs deglitch.
PULL_DOWN (1 << 3): indicate this pin needs a pull down.
DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger.
DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
following values:
00 - No change (reset state value kept)
01 - Low
10 - Medium
11 - High
OUTPUT (1 << 7): indicate this pin need to be configured as an output.
OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low)
SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable
DEBOUNCE (1 << 16): indicate this pin needs debounce.
DEBOUNCE_VAL (0x3fff << 17): debounce value.
NOTE:
Some requirements for using atmel,at91rm9200-pinctrl binding:
1. We have pin function node defined under at91 controller node to represent
what pinmux functions this SoC supports.
2. The driver can use the function node's name and pin configuration node's
name describe the pin function and group hierarchy.
For example, Linux at91 pinctrl driver takes the function node's name
as the function name and pin configuration node's name as group name to
create the map table.
3. Each pin configuration node should have a phandle, devices can set pins
configurations by referring to the phandle of that pin configuration node.
4. The gpio controller must be describe in the pinctrl simple-bus.
For each bank the required properties are:
- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
"microchip,sam9x60-gpio"
or "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"
- reg: physical base address and length of the controller's registers
- interrupts: interrupt outputs from the controller
- interrupt-controller: marks the device node as an interrupt controller
- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt
for more details.
- gpio-controller
- #gpio-cells: should be 2; the first cell is the GPIO number and the second
cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>.
- clocks: bank clock
Examples:
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
reg = <0xfffff400 0x600>;
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
atmel,mux-mask = <
/* A B */
0xffffffff 0xffc00c3b /* pioA */
0xffffffff 0x7fff3ccf /* pioB */
0xffffffff 0x007fffff /* pioC */
>;
/* shared pinctrl settings */
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<1 14 0x1 0x0 /* PB14 periph A */
1 15 0x1 0x1>; /* PB15 periph A with pullup */
};
};
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
interrupts = <1 4 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
};
Documentation/devicetree/bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml
+184
View File
@@ -0,0 +1,184 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PIO3 Pinmux Controller
maintainers:
- Manikandan Muralidharan <manikandan.m@microchip.com>
description:
The AT91 Pinmux Controller, enables the IC to share one PAD to several
functional blocks. The sharing is done by multiplexing the PAD input/output
signals. For each PAD there are up to 8 muxing options (called periph modes).
Since different modules require different PAD settings (like pull up, keeper,
etc) the controller controls also the PAD settings parameters.
properties:
compatible:
oneOf:
- items:
- enum:
- atmel,at91rm9200-pinctrl
- atmel,at91sam9x5-pinctrl
- atmel,sama5d3-pinctrl
- microchip,sam9x60-pinctrl
- const: simple-mfd
- items:
- enum:
- microchip,sam9x7-pinctrl
- const: microchip,sam9x60-pinctrl
- const: simple-mfd
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges: true
atmel,mux-mask:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
Array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to
be described.
#How to create such array:
Each column will represent the possible peripheral of the pinctrl
Each line will represent a pio bank
#Example:
In at91sam9260.dtsi,
Peripheral: 2 ( A and B)
Bank: 3 (A, B and C)
# A B
0xffffffff 0xffc00c3b # pioA
0xffffffff 0x7fff3ccf # pioB
0xffffffff 0x007fffff # pioC
For each peripheral/bank we will describe in a u32 if a pin can be
configured in it by putting 1 to the pin bit (1 << pin)
Let's take the pioA on peripheral B whose value is 0xffc00c3b
From the datasheet Table 10-2.
Peripheral B
PA0 MCDB0
PA1 MCCDB
PA2
PA3 MCDB3
PA4 MCDB2
PA5 MCDB1
PA6
PA7
PA8
PA9
PA10 ETX2
PA11 ETX3
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22 ETXER
PA23 ETX2
PA24 ETX3
PA25 ERX2
PA26 ERX3
PA27 ERXCK
PA28 ECRS
PA29 ECOL
PA30 RXD4
PA31 TXD4
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- ranges
- "#address-cells"
- "#size-cells"
- atmel,mux-mask
patternProperties:
'gpio@[0-9a-f]+$':
$ref: /schemas/gpio/atmel,at91rm9200-gpio.yaml
unevaluatedProperties: false
additionalProperties:
type: object
additionalProperties:
type: object
additionalProperties: false
properties:
atmel,pins:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
Each entry consists of 4 integers and represents the pins
mux and config setting.The format is
atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
Supported pin number and mux varies for different SoCs, and
are defined in <include/dt-bindings/pinctrl/at91.h>.
items:
items:
- description:
Pin bank
- description:
Pin bank index
- description:
Peripheral function
- description:
Pad configuration
examples:
- |
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/at91.h>
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x600>;
atmel,mux-mask = <
/* A B */
0xffffffff 0xffc00c3b /* pioA */
0xffffffff 0x7fff3ccf /* pioB */
0xffffffff 0x007fffff /* pioC */
>;
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
};
...
Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
+1
View File
@@ -25,6 +25,7 @@ properties:
- renesas,r8a7745-sysc # RZ/G1E
- renesas,r8a77470-sysc # RZ/G1C
- renesas,r8a774a1-sysc # RZ/G2M
- renesas,r8a774a3-sysc # RZ/G2M v3.0
- renesas,r8a774b1-sysc # RZ/G2N
- renesas,r8a774c0-sysc # RZ/G2E
- renesas,r8a774e1-sysc # RZ/G2H
Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
+24
View File
@@ -50,6 +50,7 @@ properties:
- rockchip,rk3188-io-voltage-domain
- rockchip,rk3228-io-voltage-domain
- rockchip,rk3288-io-voltage-domain
- rockchip,rk3308-io-voltage-domain
- rockchip,rk3328-io-voltage-domain
- rockchip,rk3368-io-voltage-domain
- rockchip,rk3368-pmu-io-voltage-domain
@@ -71,6 +72,7 @@ allOf:
- $ref: "#/$defs/rk3188"
- $ref: "#/$defs/rk3228"
- $ref: "#/$defs/rk3288"
- $ref: "#/$defs/rk3308"
- $ref: "#/$defs/rk3328"
- $ref: "#/$defs/rk3368"
- $ref: "#/$defs/rk3368-pmu"
@@ -194,6 +196,28 @@ $defs:
wifi-supply:
description: The supply connected to APIO3_VDD. Also known as SDIO0.
rk3308:
if:
properties:
compatible:
contains:
const: rockchip,rk3308-io-voltage-domain
then:
properties:
vccio0-supply:
description: The supply connected to VCCIO0.
vccio1-supply:
description: The supply connected to VCCIO1.
vccio2-supply:
description: The supply connected to VCCIO2.
vccio3-supply:
description: The supply connected to VCCIO3.
vccio4-supply:
description: The supply connected to VCCIO4.
vccio5-supply:
description: The supply connected to VCCIO5.
rk3328:
if:
properties:
Documentation/devicetree/bindings/regulator/mediatek,mt6397-regulator.yaml
+238
View File
@@ -0,0 +1,238 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/mediatek,mt6397-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT6397 Regulator
maintainers:
- Sen Chu <sen.chu@mediatek.com>
- Macpaul Lin <macpaul.lin@mediatek.com>
description:
Regulator node of the PMIC. This node should under the PMIC's device node.
All voltage regulators provided by the PMIC are described as sub-nodes of
this node.
properties:
compatible:
items:
- const: mediatek,mt6397-regulator
patternProperties:
"^(buck_)?v(core|drm|gpu|io18|pca(7|15)|sramca(7|15))$":
description: Buck regulators
type: object
$ref: regulator.yaml#
properties:
regulator-allowed-modes:
description: |
BUCK regulators can set regulator-initial-mode and regulator-allowed-modes to
values specified in dt-bindings/regulator/mediatek,mt6397-regulator.h
items:
enum: [0, 1]
unevaluatedProperties: false
"^(ldo_)?v(tcxo|(a|io)28)$":
description: LDOs with fixed 2.8V output and 0~100/10mV tuning
type: object
$ref: regulator.yaml#
properties:
regulator-allowed-modes: false
unevaluatedProperties: false
"^(ldo_)?vusb$":
description: LDOs with fixed 3.0V output and 0~100/10mV tuning
type: object
$ref: regulator.yaml#
properties:
regulator-allowed-modes: false
unevaluatedProperties: false
"^(ldo_)?v(cama|emc3v3|gp[123456]|ibr|mc|mch)$":
description: LDOs with variable output and 0~100/10mV tuning
type: object
$ref: regulator.yaml#
properties:
regulator-allowed-modes: false
unevaluatedProperties: false
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
mt6397_regulators: regulators {
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-name = "vpca15";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <200>;
};
mt6397_vpca7_reg: buck_vpca7 {
regulator-name = "vpca7";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vsramca15_reg: buck_vsramca15 {
regulator-name = "vsramca15";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vsramca7_reg: buck_vsramca7 {
regulator-name = "vsramca7";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vcore_reg: buck_vcore {
regulator-name = "vcore";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vgpu_reg: buck_vgpu {
regulator-name = "vgpu";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vdrm_reg: buck_vdrm {
regulator-name = "vdrm";
regulator-min-microvolt = < 800000>;
regulator-max-microvolt = <1400000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <500>;
};
mt6397_vio18_reg: buck_vio18 {
regulator-name = "vio18";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2120000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <500>;
};
mt6397_vtcxo_reg: ldo_vtcxo {
regulator-name = "vtcxo";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <90>;
};
mt6397_va28_reg: ldo_va28 {
regulator-name = "va28";
/* fixed output 2.8 V */
regulator-enable-ramp-delay = <218>;
};
mt6397_vcama_reg: ldo_vcama {
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vio28_reg: ldo_vio28 {
regulator-name = "vio28";
/* fixed output 2.8 V */
regulator-enable-ramp-delay = <240>;
};
mt6397_usb_reg: ldo_vusb {
regulator-name = "vusb";
/* fixed output 3.3 V */
regulator-enable-ramp-delay = <218>;
};
mt6397_vmc_reg: ldo_vmc {
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vmch_reg: ldo_vmch {
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
regulator-name = "vemc_3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp1_reg: ldo_vgp1 {
regulator-name = "vcamd";
regulator-min-microvolt = <1220000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <240>;
};
mt6397_vgp2_reg: ldo_vgp2 {
regulator-name = "vcamio";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp3_reg: ldo_vgp3 {
regulator-name = "vcamaf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp5_reg: ldo_vgp5 {
regulator-name = "vgp5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp6_reg: ldo_vgp6 {
regulator-name = "vgp6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vibr_reg: ldo_vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
};
Documentation/devicetree/bindings/regulator/microchip,mcp16502.yaml
+20
View File
@@ -28,6 +28,21 @@ properties:
reg:
maxItems: 1
lvin-supply:
description: Input supply phandle for LDO1 and LDO2
pvin1-supply:
description: Input supply phandle for VDD_IO (BUCK1)
pvin2-supply:
description: Input supply phandle for VDD_DDR (BUCK2)
pvin3-supply:
description: Input supply phandle for VDD_CORE (BUCK3)
pvin4-supply:
description: Input supply phandle for VDD_OTHER (BUCK4)
regulators:
type: object
additionalProperties: false
@@ -68,6 +83,11 @@ examples:
pmic@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
lvin-supply = <&reg_5v>;
pvin1-supply = <&reg_5v>;
pvin2-supply = <&reg_5v>;
pvin3-supply = <&reg_5v>;
pvin4-supply = <&reg_5v>;
regulators {
VDD_IO {
Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
-220
View File
@@ -1,220 +0,0 @@
Mediatek MT6397 Regulator
Required properties:
- compatible: "mediatek,mt6397-regulator"
- mt6397regulator: List of regulators provided by this controller. It is named
according to its regulator type, buck_<name> and ldo_<name>.
The definition for each of these nodes is defined using the standard binding
for regulators at Documentation/devicetree/bindings/regulator/regulator.txt.
The valid names for regulators are::
BUCK:
buck_vpca15, buck_vpca7, buck_vsramca15, buck_vsramca7, buck_vcore, buck_vgpu,
buck_vdrm, buck_vio18
LDO:
ldo_vtcxo, ldo_va28, ldo_vcama, ldo_vio28, ldo_vusb, ldo_vmc, ldo_vmch,
ldo_vemc3v3, ldo_vgp1, ldo_vgp2, ldo_vgp3, ldo_vgp4, ldo_vgp5, ldo_vgp6,
ldo_vibr
BUCK regulators can set regulator-initial-mode and regulator-allowed-modes to
values specified in dt-bindings/regulator/mediatek,mt6397-regulator.h
Example:
pmic {
compatible = "mediatek,mt6397";
mt6397regulator: mt6397regulator {
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-compatible = "buck_vpca15";
regulator-name = "vpca15";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <200>;
};
mt6397_vpca7_reg: buck_vpca7 {
regulator-compatible = "buck_vpca7";
regulator-name = "vpca7";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vsramca15_reg: buck_vsramca15 {
regulator-compatible = "buck_vsramca15";
regulator-name = "vsramca15";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vsramca7_reg: buck_vsramca7 {
regulator-compatible = "buck_vsramca7";
regulator-name = "vsramca7";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vcore_reg: buck_vcore {
regulator-compatible = "buck_vcore";
regulator-name = "vcore";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vgpu_reg: buck_vgpu {
regulator-compatible = "buck_vgpu";
regulator-name = "vgpu";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vdrm_reg: buck_vdrm {
regulator-compatible = "buck_vdrm";
regulator-name = "vdrm";
regulator-min-microvolt = < 800000>;
regulator-max-microvolt = <1400000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <500>;
};
mt6397_vio18_reg: buck_vio18 {
regulator-compatible = "buck_vio18";
regulator-name = "vio18";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2120000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <500>;
};
mt6397_vtcxo_reg: ldo_vtcxo {
regulator-compatible = "ldo_vtcxo";
regulator-name = "vtcxo";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <90>;
};
mt6397_va28_reg: ldo_va28 {
regulator-compatible = "ldo_va28";
regulator-name = "va28";
/* fixed output 2.8 V */
regulator-enable-ramp-delay = <218>;
};
mt6397_vcama_reg: ldo_vcama {
regulator-compatible = "ldo_vcama";
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vio28_reg: ldo_vio28 {
regulator-compatible = "ldo_vio28";
regulator-name = "vio28";
/* fixed output 2.8 V */
regulator-enable-ramp-delay = <240>;
};
mt6397_usb_reg: ldo_vusb {
regulator-compatible = "ldo_vusb";
regulator-name = "vusb";
/* fixed output 3.3 V */
regulator-enable-ramp-delay = <218>;
};
mt6397_vmc_reg: ldo_vmc {
regulator-compatible = "ldo_vmc";
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vmch_reg: ldo_vmch {
regulator-compatible = "ldo_vmch";
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
regulator-compatible = "ldo_vemc3v3";
regulator-name = "vemc_3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp1_reg: ldo_vgp1 {
regulator-compatible = "ldo_vgp1";
regulator-name = "vcamd";
regulator-min-microvolt = <1220000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <240>;
};
mt6397_vgp2_reg: ldo_vgp2 {
egulator-compatible = "ldo_vgp2";
regulator-name = "vcamio";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp3_reg: ldo_vgp3 {
regulator-compatible = "ldo_vgp3";
regulator-name = "vcamaf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-compatible = "ldo_vgp4";
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp5_reg: ldo_vgp5 {
regulator-compatible = "ldo_vgp5";
regulator-name = "vgp5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp6_reg: ldo_vgp6 {
regulator-compatible = "ldo_vgp6";
regulator-name = "vgp6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vibr_reg: ldo_vibr {
regulator-compatible = "ldo_vibr";
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
};
};
Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
+21 -1
View File
@@ -18,6 +18,7 @@ properties:
compatible:
enum:
- qcom,qca6390-pmu
- qcom,wcn6855-pmu
- qcom,wcn7850-pmu
vdd-supply:
@@ -65,7 +66,11 @@ properties:
bt-enable-gpios:
maxItems: 1
description: GPIO line enabling the ATH11K Bluetooth module supplied by the PMU
description: GPIO line enabling the Bluetooth module supplied by the PMU
swctrl-gpios:
maxItems: 1
description: GPIO line indicating the state of the clock supply to the BT module
clocks:
maxItems: 1
@@ -104,6 +109,21 @@ allOf:
- vddpcie1p3-supply
- vddpcie1p9-supply
- vddio-supply
- if:
properties:
compatible:
contains:
const: qcom,wcn6855-pmu
then:
required:
- vddio-supply
- vddaon-supply
- vddpmu-supply
- vddrfa0p95-supply
- vddrfa1p3-supply
- vddrfa1p9-supply
- vddpcie1p3-supply
- vddpcie1p9-supply
- if:
properties:
compatible:
Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml
+1 -1
View File
@@ -90,7 +90,7 @@ examples:
qcom,rpm-msg-ram = <&rpm_msg_ram>;
rpm-requests {
compatible = "qcom,rpm-msm8996";
compatible = "qcom,rpm-msm8996", "qcom,glink-smd-rpm";
qcom,glink-channels = "rpm_requests";
/* ... */
Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml
+2 -2
View File
@@ -142,7 +142,7 @@ examples:
qcom,smd-edge = <15>;
rpm-requests {
compatible = "qcom,rpm-msm8916";
compatible = "qcom,rpm-msm8916", "qcom,smd-rpm";
qcom,smd-channels = "rpm_requests";
/* ... */
};
@@ -163,7 +163,7 @@ examples:
mboxes = <&apcs_glb 0>;
rpm-requests {
compatible = "qcom,rpm-qcm2290";
compatible = "qcom,rpm-qcm2290", "qcom,glink-smd-rpm";
qcom,glink-channels = "rpm_requests";
/* ... */
};
Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
+1
View File
@@ -19,6 +19,7 @@ properties:
- amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
- amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
- amlogic,c3-reset # Reset Controller on C3 and compatible SoCs
- amlogic,t7-reset
reg:
maxItems: 1
Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml
-43
View File
@@ -1,43 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/mobileye,eyeq5-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mobileye EyeQ5 reset controller
description:
The EyeQ5 reset driver handles three reset domains. Its registers live in a
shared region called OLB.
maintainers:
- Grégory Clement <gregory.clement@bootlin.com>
- Théo Lebrun <theo.lebrun@bootlin.com>
- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
properties:
compatible:
const: mobileye,eyeq5-reset
reg:
maxItems: 3
reg-names:
items:
- const: d0
- const: d1
- const: d2
"#reset-cells":
const: 2
description:
The first cell is the domain (0 to 2 inclusive) and the second one is the
reset index inside that domain.
required:
- compatible
- reg
- reg-names
- "#reset-cells"
additionalProperties: false
Documentation/devicetree/bindings/reset/renesas,rst.yaml
+1
View File
@@ -29,6 +29,7 @@ properties:
- renesas,r8a7745-rst # RZ/G1E
- renesas,r8a77470-rst # RZ/G1C
- renesas,r8a774a1-rst # RZ/G2M
- renesas,r8a774a3-rst # RZ/G2M v3.0
- renesas,r8a774b1-rst # RZ/G2N
- renesas,r8a774c0-rst # RZ/G2E
- renesas,r8a774e1-rst # RZ/G2H
Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml
+6 -2
View File
@@ -38,13 +38,17 @@ properties:
minItems: 1
maxItems: 2
clock-names: true
clock-names:
minItems: 1
maxItems: 2
resets:
minItems: 1
maxItems: 2
reset-names: true
reset-names:
minItems: 1
maxItems: 2
allOf:
- if:
Documentation/devicetree/bindings/riscv/sophgo.yaml
+5
View File
@@ -26,6 +26,11 @@ properties:
- enum:
- sophgo,huashan-pi
- const: sophgo,cv1812h
- items:
- enum:
- sipeed,licheerv-nano-b
- const: sipeed,licheerv-nano
- const: sophgo,sg2002
- items:
- enum:
- milkv,pioneer
Documentation/devicetree/bindings/soc/bcm/brcm,bcm2711-avs-monitor.yaml
+44
View File
@@ -0,0 +1,44 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm2711-avs-monitor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom AVS Monitor
maintainers:
- Stefan Wahren <wahrenst@gmx.net>
properties:
compatible:
items:
- const: brcm,bcm2711-avs-monitor
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
thermal:
$ref: /schemas/thermal/brcm,avs-ro-thermal.yaml
description: Broadcom AVS ring oscillator thermal
required:
- compatible
- reg
- thermal
additionalProperties: false
examples:
- |
avs-monitor@7d5d2000 {
compatible = "brcm,bcm2711-avs-monitor", "syscon", "simple-mfd";
reg = <0x7d5d2000 0xf00>;
thermal: thermal {
compatible = "brcm,bcm2711-thermal";
#thermal-sensor-cells = <0>;
};
};
...
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml
+210
View File
@@ -0,0 +1,210 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PowerQUICC QE Time-slot assigner (TSA) controller
maintainers:
- Herve Codina <herve.codina@bootlin.com>
description:
The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
Its purpose is to route some TDM time-slots to other internal serial
controllers.
properties:
compatible:
items:
- enum:
- fsl,mpc8321-tsa
- const: fsl,qe-tsa
reg:
items:
- description: SI (Serial Interface) register base
- description: SI RAM base
reg-names:
items:
- const: si_regs
- const: si_ram
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^tdm@[0-3]$':
description:
The TDM managed by this controller
type: object
additionalProperties: false
properties:
reg:
minimum: 0
maximum: 3
description:
The TDM number for this TDM, 0 for TDMa, 1 for TDMb, 2 for TDMc and 3
for TDMd.
fsl,common-rxtx-pins:
$ref: /schemas/types.yaml#/definitions/flag
description:
The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
Without the 'fsl,common-rxtx-pins' property, the four pins are used.
With the 'fsl,common-rxtx-pins' property, two pins are used.
clocks:
minItems: 2
items:
- description: Receive sync clock
- description: Receive data clock
- description: Transmit sync clock
- description: Transmit data clock
clock-names:
minItems: 2
items:
- const: rsync
- const: rclk
- const: tsync
- const: tclk
fsl,rx-frame-sync-delay-bits:
enum: [0, 1, 2, 3]
default: 0
description: |
Receive frame sync delay in number of bits.
Indicates the delay between the Rx sync and the first bit of the Rx
frame.
fsl,tx-frame-sync-delay-bits:
enum: [0, 1, 2, 3]
default: 0
description: |
Transmit frame sync delay in number of bits.
Indicates the delay between the Tx sync and the first bit of the Tx
frame.
fsl,clock-falling-edge:
$ref: /schemas/types.yaml#/definitions/flag
description:
Data is sent on falling edge of the clock (and received on the rising
edge). If not present, data is sent on the rising edge (and received
on the falling edge).
fsl,fsync-rising-edge:
$ref: /schemas/types.yaml#/definitions/flag
description:
Frame sync pulses are sampled with the rising edge of the channel
clock. If not present, pulses are sampled with the falling edge.
fsl,fsync-active-low:
$ref: /schemas/types.yaml#/definitions/flag
description:
Frame sync signals are active on low logic level.
If not present, sync signals are active on high level.
fsl,double-speed-clock:
$ref: /schemas/types.yaml#/definitions/flag
description:
The channel clock is twice the data rate.
patternProperties:
'^fsl,[rt]x-ts-routes$':
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
A list of tuple that indicates the Tx or Rx time-slots routes.
items:
items:
- description:
The number of time-slots
minimum: 1
maximum: 64
- description: |
The source (Tx) or destination (Rx) serial interface
(dt-bindings/soc/qe-fsl,tsa.h defines these values)
- 0: No destination
- 1: UCC1
- 2: UCC2
- 3: UCC3
- 4: UCC4
- 5: UCC5
enum: [0, 1, 2, 3, 4, 5]
minItems: 1
maxItems: 64
allOf:
# If fsl,common-rxtx-pins is present, only 2 clocks are needed.
# Else, the 4 clocks must be present.
- if:
required:
- fsl,common-rxtx-pins
then:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
else:
properties:
clocks:
minItems: 4
clock-names:
minItems: 4
required:
- reg
- clocks
- clock-names
required:
- compatible
- reg
- reg-names
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/qe-fsl,tsa.h>
tsa@ae0 {
compatible = "fsl,mpc8321-tsa", "fsl,qe-tsa";
reg = <0xae0 0x10>,
<0xc00 0x200>;
reg-names = "si_regs", "si_ram";
#address-cells = <1>;
#size-cells = <0>;
tdm@0 {
/* TDMa */
reg = <0>;
clocks = <&clk_l1rsynca>, <&clk_l1rclka>;
clock-names = "rsync", "rclk";
fsl,common-rxtx-pins;
fsl,fsync-rising-edge;
fsl,tx-ts-routes = <2 0>, /* TS 0..1 */
<24 FSL_QE_TSA_UCC4>, /* TS 2..25 */
<1 0>, /* TS 26 */
<5 FSL_QE_TSA_UCC3>; /* TS 27..31 */
fsl,rx-ts-routes = <2 0>, /* TS 0..1 */
<24 FSL_QE_TSA_UCC4>, /* 2..25 */
<1 0>, /* TS 26 */
<5 FSL_QE_TSA_UCC3>; /* TS 27..31 */
};
};
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml
+197
View File
@@ -0,0 +1,197 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PowerQUICC QE QUICC Multichannel Controller (QMC)
maintainers:
- Herve Codina <herve.codina@bootlin.com>
description:
The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one
serial controller using the same TDM physical interface routed from TSA.
properties:
compatible:
items:
- enum:
- fsl,mpc8321-ucc-qmc
- const: fsl,qe-ucc-qmc
reg:
items:
- description: UCC (Unified communication controller) register base
- description: Dual port ram base
reg-names:
items:
- const: ucc_regs
- const: dpram
interrupts:
maxItems: 1
description: UCC interrupt line in the QE interrupt controller
fsl,tsa-serial:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to TSA node
- enum: [1, 2, 3, 4, 5]
description: |
TSA serial interface (dt-bindings/soc/qe-fsl,tsa.h defines these
values)
- 1: UCC1
- 2: UCC2
- 3: UCC3
- 4: UCC4
- 5: UCC5
description:
Should be a phandle/number pair. The phandle to TSA node and the TSA
serial interface to use.
fsl,soft-qmc:
$ref: /schemas/types.yaml#/definitions/string
description:
Soft QMC firmware name to load. If this property is omitted, no firmware
are used.
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^channel@([0-9]|[1-5][0-9]|6[0-3])$':
description:
A channel managed by this controller
type: object
additionalProperties: false
properties:
compatible:
items:
- enum:
- fsl,mpc8321-ucc-qmc-hdlc
- const: fsl,qe-ucc-qmc-hdlc
- const: fsl,qmc-hdlc
reg:
minimum: 0
maximum: 63
description:
The channel number
fsl,operational-mode:
$ref: /schemas/types.yaml#/definitions/string
enum: [transparent, hdlc]
default: transparent
description: |
The channel operational mode
- hdlc: The channel handles HDLC frames
- transparent: The channel handles raw data without any processing
fsl,reverse-data:
$ref: /schemas/types.yaml#/definitions/flag
description:
The bit order as seen on the channels is reversed,
transmitting/receiving the MSB of each octet first.
This flag is used only in 'transparent' mode.
fsl,tx-ts-mask:
$ref: /schemas/types.yaml#/definitions/uint64
description:
Channel assigned Tx time-slots within the Tx time-slots routed by the
TSA to this cell.
fsl,rx-ts-mask:
$ref: /schemas/types.yaml#/definitions/uint64
description:
Channel assigned Rx time-slots within the Rx time-slots routed by the
TSA to this cell.
fsl,framer:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the framer node. The framer is in charge of an E1/T1 line
interface connected to the TDM bus. It can be used to get the E1/T1 line
status such as link up/down.
allOf:
- if:
properties:
compatible:
not:
contains:
const: fsl,qmc-hdlc
then:
properties:
fsl,framer: false
required:
- reg
- fsl,tx-ts-mask
- fsl,rx-ts-mask
required:
- compatible
- reg
- reg-names
- interrupts
- fsl,tsa-serial
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/qe-fsl,tsa.h>
qmc@a60 {
compatible = "fsl,mpc8321-ucc-qmc", "fsl,qe-ucc-qmc";
reg = <0x3200 0x200>,
<0x10000 0x1000>;
reg-names = "ucc_regs", "dpram";
interrupts = <35>;
interrupt-parent = <&qeic>;
fsl,soft-qmc = "fsl_qe_ucode_qmc_8321_11.bin";
#address-cells = <1>;
#size-cells = <0>;
fsl,tsa-serial = <&tsa FSL_QE_TSA_UCC4>;
channel@16 {
/* Ch16 : First 4 even TS from all routed from TSA */
reg = <16>;
fsl,operational-mode = "transparent";
fsl,reverse-data;
fsl,tx-ts-mask = <0x00000000 0x000000aa>;
fsl,rx-ts-mask = <0x00000000 0x000000aa>;
};
channel@17 {
/* Ch17 : First 4 odd TS from all routed from TSA */
reg = <17>;
fsl,operational-mode = "transparent";
fsl,reverse-data;
fsl,tx-ts-mask = <0x00000000 0x00000055>;
fsl,rx-ts-mask = <0x00000000 0x00000055>;
};
channel@19 {
/* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
compatible = "fsl,mpc8321-ucc-qmc-hdlc",
"fsl,qe-ucc-qmc-hdlc",
"fsl,qmc-hdlc";
reg = <19>;
fsl,operational-mode = "hdlc";
fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
fsl,framer = <&framer>;
};
};
Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml
+5
View File
@@ -30,6 +30,11 @@ properties:
- qcom,sm8450-pmic-glink
- qcom,sm8550-pmic-glink
- const: qcom,pmic-glink
- items:
- enum:
- qcom,sm7325-pmic-glink
- const: qcom,qcm6490-pmic-glink
- const: qcom,pmic-glink
- items:
- enum:
- qcom,sm8650-pmic-glink
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
+33 -41
View File
@@ -30,31 +30,37 @@ maintainers:
properties:
compatible:
enum:
- qcom,rpm-apq8084
- qcom,rpm-ipq6018
- qcom,rpm-ipq9574
- qcom,rpm-mdm9607
- qcom,rpm-msm8226
- qcom,rpm-msm8610
- qcom,rpm-msm8909
- qcom,rpm-msm8916
- qcom,rpm-msm8917
- qcom,rpm-msm8936
- qcom,rpm-msm8937
- qcom,rpm-msm8952
- qcom,rpm-msm8953
- qcom,rpm-msm8974
- qcom,rpm-msm8976
- qcom,rpm-msm8994
- qcom,rpm-msm8996
- qcom,rpm-msm8998
- qcom,rpm-qcm2290
- qcom,rpm-qcs404
- qcom,rpm-sdm660
- qcom,rpm-sm6115
- qcom,rpm-sm6125
- qcom,rpm-sm6375
oneOf:
- items:
- enum:
- qcom,rpm-apq8084
- qcom,rpm-mdm9607
- qcom,rpm-msm8226
- qcom,rpm-msm8610
- qcom,rpm-msm8909
- qcom,rpm-msm8916
- qcom,rpm-msm8917
- qcom,rpm-msm8936
- qcom,rpm-msm8937
- qcom,rpm-msm8952
- qcom,rpm-msm8953
- qcom,rpm-msm8974
- qcom,rpm-msm8976
- qcom,rpm-msm8994
- const: qcom,smd-rpm
- items:
- enum:
- qcom,rpm-ipq6018
- qcom,rpm-ipq9574
- qcom,rpm-msm8996
- qcom,rpm-msm8998
- qcom,rpm-qcm2290
- qcom,rpm-qcs404
- qcom,rpm-sdm660
- qcom,rpm-sm6115
- qcom,rpm-sm6125
- qcom,rpm-sm6375
- const: qcom,glink-smd-rpm
clock-controller:
$ref: /schemas/clock/qcom,rpmcc.yaml#
@@ -84,21 +90,7 @@ if:
properties:
compatible:
contains:
enum:
- qcom,rpm-apq8084
- qcom,rpm-mdm9607
- qcom,rpm-msm8226
- qcom,rpm-msm8610
- qcom,rpm-msm8909
- qcom,rpm-msm8916
- qcom,rpm-msm8917
- qcom,rpm-msm8936
- qcom,rpm-msm8937
- qcom,rpm-msm8952
- qcom,rpm-msm8953
- qcom,rpm-msm8974
- qcom,rpm-msm8976
- qcom,rpm-msm8994
const: qcom,smd-rpm
then:
properties:
qcom,glink-channels: false
@@ -129,7 +121,7 @@ examples:
qcom,smd-edge = <15>;
rpm-requests {
compatible = "qcom,rpm-msm8916";
compatible = "qcom,rpm-msm8916", "qcom,smd-rpm";
qcom,smd-channels = "rpm_requests";
clock-controller {
Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml
+1 -1
View File
@@ -56,7 +56,7 @@ examples:
qcom,smd-edge = <15>;
rpm-requests {
compatible = "qcom,rpm-msm8974";
compatible = "qcom,rpm-msm8974", "qcom,smd-rpm";
qcom,smd-channels = "rpm_requests";
clock-controller {
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+14
View File
@@ -127,6 +127,18 @@ properties:
- const: hoperun,hihope-rzg2m
- const: renesas,r8a774a1
- description: RZ/G2M v3.0 (R8A774A3)
items:
- enum:
- hoperun,hihope-rzg2m # HopeRun HiHope RZ/G2M platform
- const: renesas,r8a774a3
- items:
- enum:
- hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms
- const: hoperun,hihope-rzg2m
- const: renesas,r8a774a3
- description: RZ/G2N (R8A774B1)
items:
- enum:
@@ -515,6 +527,8 @@ properties:
- description: RZ/V2H(P) (R9A09G057)
items:
- enum:
- renesas,rzv2h-evk # RZ/V2H EVK
- enum:
- renesas,r9a09g057h41 # RZ/V2H
- renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+16
View File
@@ -20,6 +20,20 @@ properties:
- rockchip,rk3568-pipe-grf
- rockchip,rk3568-pipe-phy-grf
- rockchip,rk3568-usb2phy-grf
- rockchip,rk3576-bigcore-grf
- rockchip,rk3576-cci-grf
- rockchip,rk3576-gpu-grf
- rockchip,rk3576-litcore-grf
- rockchip,rk3576-npu-grf
- rockchip,rk3576-php-grf
- rockchip,rk3576-pipe-phy-grf
- rockchip,rk3576-pmu1-grf
- rockchip,rk3576-sdgmac-grf
- rockchip,rk3576-sys-grf
- rockchip,rk3576-usb-grf
- rockchip,rk3576-usbdpphy-grf
- rockchip,rk3576-vo0-grf
- rockchip,rk3576-vop-grf
- rockchip,rk3588-bigcore0-grf
- rockchip,rk3588-bigcore1-grf
- rockchip,rk3588-hdptxphy-grf
@@ -64,6 +78,8 @@ properties:
- rockchip,rk3399-pmugrf
- rockchip,rk3568-grf
- rockchip,rk3568-pmugrf
- rockchip,rk3576-ioc-grf
- rockchip,rk3576-pmu0-grf
- rockchip,rk3588-usb2phy-grf
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
+9 -6
View File
@@ -32,11 +32,16 @@ properties:
- enum:
- samsung,exynos850-usi
reg: true
reg:
maxItems: 1
clocks: true
clocks:
maxItems: 2
clock-names: true
clock-names:
items:
- const: pclk
- const: ipclk
ranges: true
@@ -113,9 +118,7 @@ then:
- description: Operating clock for UART/SPI/I2C protocol
clock-names:
items:
- const: pclk
- const: ipclk
maxItems: 2
required:
- reg
Documentation/devicetree/bindings/soc/ti/ti,am654-serdes-ctrl.yaml
+2 -1
View File
@@ -14,6 +14,7 @@ properties:
items:
- const: ti,am654-serdes-ctrl
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
@@ -31,7 +32,7 @@ additionalProperties: false
examples:
- |
clock@4080 {
compatible = "ti,am654-serdes-ctrl", "syscon";
compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd";
reg = <0x4080 0x4>;
mux-controller {
Documentation/devicetree/bindings/spi/cdns,xspi.yaml
+28 -4
View File
@@ -15,24 +15,27 @@ description: |
single, dual, quad or octal wire transmission modes for
read/write access to slaves such as SPI-NOR flash.
allOf:
- $ref: spi-controller.yaml#
properties:
compatible:
const: cdns,xspi-nor
enum:
- cdns,xspi-nor
- marvell,cn10-xspi-nor
reg:
items:
- description: address and length of the controller register set
- description: address and length of the Slave DMA data port
- description: address and length of the auxiliary registers
- description: address and length of the xfer registers
minItems: 3
reg-names:
items:
- const: io
- const: sdma
- const: aux
- const: xfer
minItems: 3
interrupts:
maxItems: 1
@@ -42,6 +45,27 @@ required:
- reg
- interrupts
allOf:
- $ref: spi-controller.yaml#
- if:
properties:
compatible:
contains:
enum:
- marvell,cn10-xspi-nor
then:
properties:
reg:
minItems: 4
reg-names:
minItems: 4
else:
properties:
reg:
maxItems: 3
reg-names:
maxItems: 3
unevaluatedProperties: false
examples:
Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
+1
View File
@@ -33,6 +33,7 @@ properties:
- const: mediatek,mt6765-spi
- items:
- enum:
- mediatek,mt7981-spi-ipm
- mediatek,mt7986-spi-ipm
- mediatek,mt8188-spi-ipm
- const: mediatek,spi-ipm
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+6 -1
View File
@@ -17,9 +17,14 @@ properties:
compatible:
oneOf:
- items:
- const: microchip,mpfs-qspi
- enum:
- microchip,mpfs-qspi
- microchip,pic64gx-qspi
- const: microchip,coreqspi-rtl-v2
- const: microchip,coreqspi-rtl-v2 # FPGA QSPI
- items:
- const: microchip,pic64gx-spi
- const: microchip,mpfs-spi
- const: microchip,mpfs-spi
reg:
Documentation/devicetree/bindings/spi/nxp,sc18is.yaml
+51
View File
@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nxp,sc18is.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP SC18IS602/SC18IS603 I2C to SPI bridge
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
enum:
- nxp,sc18is602
- nxp,sc18is602b
- nxp,sc18is603
reg:
maxItems: 1
clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
default: 7372000
description:
external oscillator clock frequency. The clock-frequency property is
relevant and needed only if the chip has an external oscillator
(SC18IS603).
allOf:
- $ref: spi-controller.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
spi@28 {
compatible = "nxp,sc18is603";
reg = <0x28>;
clock-frequency = <14744000>;
};
};
Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml
+1
View File
@@ -21,6 +21,7 @@ properties:
- nxp,imx8mm-fspi
- nxp,imx8mp-fspi
- nxp,imx8qxp-fspi
- nxp,imx8ulp-fspi
- nxp,lx2160a-fspi
- items:
- enum:
Documentation/devicetree/bindings/spi/spi-rockchip.yaml
+1
View File
@@ -35,6 +35,7 @@ properties:
- rockchip,rk3368-spi
- rockchip,rk3399-spi
- rockchip,rk3568-spi
- rockchip,rk3576-spi
- rockchip,rk3588-spi
- rockchip,rv1126-spi
- const: rockchip,rk3066-spi
Documentation/devicetree/bindings/spi/spi-sc18is602.txt
-23
View File
@@ -1,23 +0,0 @@
NXP SC18IS602/SCIS603
Required properties:
- compatible : Should be one of
"nxp,sc18is602"
"nxp,sc18is602b"
"nxp,sc18is603"
- reg: I2C bus address
Optional properties:
- clock-frequency : external oscillator clock frequency. If not
specified, the SC18IS602 default frequency (7372000) will be used.
The clock-frequency property is relevant and needed only if the chip has an
external oscillator (SC18IS603).
Example:
sc18is603@28 {
compatible = "nxp,sc18is603";
reg = <0x28>;
clock-frequency = <14744000>;
}
Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
-22
View File
@@ -1,22 +0,0 @@
BCM2835 System Timer
The System Timer peripheral provides four 32-bit timer channels and a
single 64-bit free running counter. Each channel has an output compare
register, which is compared against the 32 least significant bits of the
free running counter values, and generates an interrupt.
Required properties:
- compatible : should be "brcm,bcm2835-system-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : A list of 4 interrupt sinks; one per timer channel.
- clock-frequency : The frequency of the clock that drives the counter, in Hz.
Example:
timer {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7e003000 0x1000>;
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
clock-frequency = <1000000>;
};
Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.yaml
+50
View File
@@ -0,0 +1,50 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/brcm,bcm2835-system-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: BCM2835 System Timer
maintainers:
- Stefan Wahren <wahrenst@gmx.net>
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
description:
The System Timer peripheral provides four 32-bit timer channels and a
single 64-bit free running counter. Each channel has an output compare
register, which is compared against the 32 least significant bits of the
free running counter values, and generates an interrupt.
properties:
compatible:
const: brcm,bcm2835-system-timer
reg:
maxItems: 1
interrupts:
items:
- description: System Timer Compare 0 match (used by VideoCore GPU)
- description: System Timer Compare 1 match (usable for ARM core)
- description: System Timer Compare 2 match (used by VideoCore GPU)
- description: System Timer Compare 3 match (usable for ARM core)
clock-frequency: true
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
timer@7e003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7e003000 0x1000>;
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
clock-frequency = <1000000>;
};
...
Documentation/devicetree/bindings/trivial-devices.yaml
+2
View File
@@ -110,6 +110,8 @@ properties:
- domintech,dmard09
# DMARD10: 3-axis Accelerometer
- domintech,dmard10
# Elgin SPI-controlled LCD
- elgin,jg10309-01
# MMA7660FC: 3-Axis Orientation/Motion Detection Sensor
- fsl,mma7660
# MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
View File
@@ -804,6 +804,8 @@ patternProperties:
description: Lantiq Semiconductor
"^lattice,.*":
description: Lattice Semiconductor
"^lckfb,.*":
description: Shenzhen JLC Technology Group Co., Ltd.
"^lctech,.*":
description: Shenzen LC Technology Co., Ltd.
"^leadtek,.*":
Documentation/spi/spi-summary.rst
+83
View File
@@ -614,6 +614,89 @@ queue, and then start some asynchronous transfer engine (unless it's
already running).
Extensions to the SPI protocol
------------------------------
The fact that SPI doesn't have a formal specification or standard permits chip
manufacturers to implement the SPI protocol in slightly different ways. In most
cases, SPI protocol implementations from different vendors are compatible among
each other. For example, in SPI mode 0 (CPOL=0, CPHA=0) the bus lines may behave
like the following:
::
nCSx ___ ___
\_________________________________________________________________/
• •
• •
SCLK ___ ___ ___ ___ ___ ___ ___ ___
_______/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \_____
• : ; : ; : ; : ; : ; : ; : ; : ; •
• : ; : ; : ; : ; : ; : ; : ; : ; •
MOSI XXX__________ _______ _______ ________XXX
0xA5 XXX__/ 1 \_0_____/ 1 \_0_______0_____/ 1 \_0_____/ 1 \_XXX
• ; ; ; ; ; ; ; ; •
• ; ; ; ; ; ; ; ; •
MISO XXX__________ _______________________ _______ XXX
0xBA XXX__/ 1 \_____0_/ 1 1 1 \_____0__/ 1 \____0__XXX
Legend::
• marks the start/end of transmission;
: marks when data is clocked into the peripheral;
; marks when data is clocked into the controller;
X marks when line states are not specified.
In some few cases, chips extend the SPI protocol by specifying line behaviors
that other SPI protocols don't (e.g. data line state for when CS is not
asserted). Those distinct SPI protocols, modes, and configurations are supported
by different SPI mode flags.
MOSI idle state configuration
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Common SPI protocol implementations don't specify any state or behavior for the
MOSI line when the controller is not clocking out data. However, there do exist
peripherals that require specific MOSI line state when data is not being clocked
out. For example, if the peripheral expects the MOSI line to be high when the
controller is not clocking out data (``SPI_MOSI_IDLE_HIGH``), then a transfer in
SPI mode 0 would look like the following:
::
nCSx ___ ___
\_________________________________________________________________/
• •
• •
SCLK ___ ___ ___ ___ ___ ___ ___ ___
_______/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \_____
• : ; : ; : ; : ; : ; : ; : ; : ; •
• : ; : ; : ; : ; : ; : ; : ; : ; •
MOSI _____ _______ _______ _______________ ___
0x56 \_0_____/ 1 \_0_____/ 1 \_0_____/ 1 1 \_0_____/
• ; ; ; ; ; ; ; ; •
• ; ; ; ; ; ; ; ; •
MISO XXX__________ _______________________ _______ XXX
0xBA XXX__/ 1 \_____0_/ 1 1 1 \_____0__/ 1 \____0__XXX
Legend::
• marks the start/end of transmission;
: marks when data is clocked into the peripheral;
; marks when data is clocked into the controller;
X marks when line states are not specified.
In this extension to the usual SPI protocol, the MOSI line state is specified to
be kept high when CS is asserted but the controller is not clocking out data to
the peripheral and also when CS is not asserted.
Peripherals that require this extension must request it by setting the
``SPI_MOSI_IDLE_HIGH`` bit into the mode attribute of their ``struct
spi_device`` and call spi_setup(). Controllers that support this extension
should indicate it by setting ``SPI_MOSI_IDLE_HIGH`` in the mode_bits attribute
of their ``struct spi_controller``. The configuration to idle MOSI low is
analogous but uses the ``SPI_MOSI_IDLE_LOW`` mode bit.
THANKS TO
---------
Contributors to Linux-SPI discussions include (in alphabetical order,
MAINTAINERS
+23 -3
View File
@@ -1210,6 +1210,13 @@ W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
F: drivers/iio/dac/ad3552r.c
ANALOG DEVICES INC AD4000 DRIVER
M: Marcelo Schmitt <marcelo.schmitt@analog.com>
L: linux-iio@vger.kernel.org
S: Supported
W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/iio/adc/adi,ad4000.yaml
ANALOG DEVICES INC AD4130 DRIVER
M: Cosmin Tanislav <cosmin.tanislav@analog.com>
L: linux-iio@vger.kernel.org
@@ -9044,6 +9051,7 @@ M: Herve Codina <herve.codina@bootlin.com>
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml
F: drivers/soc/fsl/qe/qmc.c
F: include/soc/fsl/qe/qmc.h
@@ -9059,9 +9067,11 @@ M: Herve Codina <herve.codina@bootlin.com>
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml
F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml
F: drivers/soc/fsl/qe/tsa.c
F: drivers/soc/fsl/qe/tsa.h
F: include/dt-bindings/soc/cpm1-fsl,tsa.h
F: include/dt-bindings/soc/qe-fsl,tsa.h
FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
L: netdev@vger.kernel.org
@@ -18963,6 +18973,7 @@ L: linux-arm-msm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
F: drivers/soc/qcom/icc-bwmon.c
F: drivers/soc/qcom/trace_icc-bwmon.h
QUALCOMM IOMMU
M: Rob Clark <robdclark@gmail.com>
@@ -20239,6 +20250,16 @@ B: mailto:linux-samsung-soc@vger.kernel.org
F: Documentation/devicetree/bindings/sound/samsung*
F: sound/soc/samsung/
SAMSUNG EXYNOS850 SoC SUPPORT
M: Sam Protsenko <semen.protsenko@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-samsung-soc@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
F: arch/arm64/boot/dts/exynos/exynos850*
F: drivers/clk/samsung/clk-exynos850.c
F: include/dt-bindings/clock/exynos850.h
SAMSUNG EXYNOS PSEUDO RANDOM NUMBER GENERATOR (RNG) DRIVER
M: Krzysztof Kozlowski <krzk@kernel.org>
L: linux-crypto@vger.kernel.org
@@ -23303,9 +23324,8 @@ TQ SYSTEMS BOARD & DRIVER SUPPORT
L: linux@ew.tq-group.com
S: Supported
W: https://www.tq-group.com/en/products/tq-embedded/
F: arch/arm/boot/dts/imx*mba*.dts*
F: arch/arm/boot/dts/imx*tqma*.dts*
F: arch/arm/boot/dts/mba*.dtsi
F: arch/arm/boot/dts/nxp/imx/*mba*.dts*
F: arch/arm/boot/dts/nxp/imx/*tqma*.dts*
F: arch/arm64/boot/dts/freescale/fsl-*tqml*.dts*
F: arch/arm64/boot/dts/freescale/imx*mba*.dts*
F: arch/arm64/boot/dts/freescale/imx*tqma*.dts*
arch/arm/boot/dts/amlogic/meson8b-ec100.dts
-2
View File
@@ -34,8 +34,6 @@
gpio-keys {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
pal-switch {
arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi
+1 -1
View File
@@ -103,7 +103,7 @@
};
/* PMU with one IRQ line per core */
pmu: pmu@0 {
pmu: pmu {
compatible = "arm,arm11mpcore-pmu";
interrupt-parent = <&intc>;
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
arch/arm/boot/dts/arm/arm-realview-pb11mp.dts
+1 -1
View File
@@ -92,7 +92,7 @@
<0x1f000100 0x100>;
};
L2: cache-controller {
L2: cache-controller@1f002000 {
compatible = "arm,l220-cache";
reg = <0x1f002000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
arch/arm/boot/dts/arm/arm-realview-pba8.dts
+1 -1
View File
@@ -40,7 +40,7 @@
};
};
pmu: pmu@0 {
pmu: pmu {
compatible = "arm,cortex-a8-pmu";
interrupt-parent = <&intc>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
arch/arm/boot/dts/arm/arm-realview-pbx-a9.dts
+1 -1
View File
@@ -97,7 +97,7 @@
interrupts = <1 14 0xf04>;
};
pmu: pmu@0 {
pmu: pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&intc>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
arch/arm/boot/dts/aspeed/Makefile
+3
View File
@@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-bytedance-g220a.dtb \
aspeed-bmc-delta-ahe50dc.dtb \
aspeed-bmc-facebook-bletchley.dtb \
aspeed-bmc-facebook-catalina.dtb \
aspeed-bmc-facebook-cmm.dtb \
aspeed-bmc-facebook-elbert.dtb \
aspeed-bmc-facebook-fuji.dtb \
@@ -32,8 +33,10 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-facebook-yamp.dtb \
aspeed-bmc-facebook-yosemitev2.dtb \
aspeed-bmc-facebook-yosemite4.dtb \
aspeed-bmc-ibm-blueridge.dtb \
aspeed-bmc-ibm-bonnell.dtb \
aspeed-bmc-ibm-everest.dtb \
aspeed-bmc-ibm-fuji.dtb \
aspeed-bmc-ibm-rainier.dtb \
aspeed-bmc-ibm-rainier-1s4u.dtb \
aspeed-bmc-ibm-rainier-4u.dtb \
arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts
+16 -4
View File
@@ -49,6 +49,11 @@
*/
i2c80 = &nvme_m2_0;
i2c81 = &nvme_m2_1;
/*
* i2c bus 82 assigned to OCP slot
*/
i2c82 = &ocpslot;
};
chosen {
@@ -420,6 +425,17 @@
reg = <0x70>;
i2c-mux-idle-disconnect;
ocpslot: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
ocpslot_temp: temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
};
nvmeslot_0_7: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
@@ -672,10 +688,6 @@
memory-region = <&gfx_memory>;
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts
+154
View File
@@ -15,6 +15,32 @@
serial7 = &uart8;
serial8 = &uart9;
/*
* I2C temperature alias port
*/
i2c20 = &i2c4_bus70_chn0;
i2c21 = &i2c4_bus70_chn1;
i2c22 = &i2c4_bus70_chn2;
i2c23 = &i2c4_bus70_chn3;
/*
* i2c bus 30-31 assigned to OCP slot 0-1
*/
i2c30 = &ocpslot_0;
i2c31 = &ocpslot_1;
/*
* i2c bus 32-33 assigned to Riser slot 0-1
*/
i2c32 = &i2c_riser0;
i2c33 = &i2c_riser1;
/*
* i2c bus 38-39 assigned to FRU on Riser slot 0-1
*/
i2c38 = &i2c_riser0_chn_0;
i2c39 = &i2c_riser1_chn_0;
/*
* I2C NVMe alias port
*/
@@ -87,6 +113,37 @@
};
};
leds {
compatible = "gpio-leds";
/*
* Use gpio-leds to configure GPIOW5 (bmc-ready) pin to be reseted when
* watchdog timeout.
*/
led-bmc-ready {
gpios = <&gpio0 ASPEED_GPIO(W, 5) (GPIO_ACTIVE_HIGH | GPIO_TRANSITORY)>;
};
led-sw-heartbeat {
gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_HIGH>;
};
led-identify {
gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
};
led-fault {
gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
};
led-fan-fault {
gpios = <&gpio_expander1 0 GPIO_ACTIVE_HIGH>;
};
led-psu-fault {
gpios = <&gpio_expander1 1 GPIO_ACTIVE_HIGH>;
};
};
voltage_mon_reg: voltage-mon-regulator {
compatible = "regulator-fixed";
regulator-name = "ltc2497_reg";
@@ -515,6 +572,80 @@
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
ocpslot_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
ocpslot_0_temp: temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
};
ocpslot_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
ocpslot_1_temp: temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
};
i2c_riser0: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
i2c-mux@72 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72>;
i2c-mux-idle-disconnect;
i2c_riser0_chn_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
};
};
i2c_riser1: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
i2c-mux@72 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72>;
i2c-mux-idle-disconnect;
i2c_riser1_chn_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
};
};
};
};
@@ -790,6 +921,10 @@
};
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
ssif-bmc@10 {
@@ -812,6 +947,25 @@
};
};
&i2c15 {
status = "okay";
gpio_expander1: gpio-expander@22 {
compatible = "nxp,pca9535";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"fan-fault","psu-fault",
"","",
"","",
"","",
"","",
"","",
"","",
"","";
};
};
&adc0 {
status = "okay";
arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts
-4
View File
@@ -200,10 +200,6 @@
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&gpio {
pin_gpio_c7 {
gpio-hog;
arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-spc621d8hm3.dts
+8 -4
View File
@@ -110,11 +110,15 @@
compatible = "st,24c128", "atmel,24c128";
reg = <0x50>;
pagesize = <16>;
#address-cells = <1>;
#size-cells = <1>;
eth0_macaddress: macaddress@3f80 {
reg = <0x3f80 6>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eth0_macaddress: macaddress@3f80 {
reg = <0x3f80 6>;
};
};
};
arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x570d4u.dts
-4
View File
@@ -254,10 +254,6 @@
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&vhub {
status = "okay";
};
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts
+1110
View File
File diff suppressed because it is too large Load Diff
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts
+1 -1
View File
@@ -201,7 +201,7 @@
&i2c12 {
status = "okay";
temperature-sensor@4f {
compatible = "lm75";
compatible = "national,lm75";
reg = <0x4f>;
};
};
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts
+132 -45
View File
@@ -20,10 +20,6 @@
i2c21 = &imux21;
i2c22 = &imux22;
i2c23 = &imux23;
i2c24 = &imux24;
i2c25 = &imux25;
i2c26 = &imux26;
i2c27 = &imux27;
i2c28 = &imux28;
i2c29 = &imux29;
i2c30 = &imux30;
@@ -70,19 +66,19 @@
};
};
spi_gpio: spi-gpio {
spi_gpio: spi {
status = "okay";
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
tpmdev@0 {
tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
spi-max-frequency = <33000000>;
reg = <0>;
@@ -137,7 +133,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii4_default>;
use-ncsi;
mellanox,multi-host;
};
&rtc {
@@ -198,6 +193,35 @@
#address-cells = <1>;
#size-cells = <0>;
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <1000>;
};
power-sensor@41 {
compatible = "ti,ina238";
reg = <0x41>;
shunt-resistor = <1000>;
};
power-sensor@44 {
compatible = "ti,ina238";
reg = <0x44>;
shunt-resistor = <1000>;
};
power-sensor@45 {
compatible = "ti,ina238";
reg = <0x45>;
shunt-resistor = <1000>;
};
temperature-sensor@4b {
compatible = "ti,tmp75";
reg = <0x4b>;
};
};
&i2c1 {
@@ -224,6 +248,35 @@
#address-cells = <1>;
#size-cells = <0>;
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <1000>;
};
power-sensor@41 {
compatible = "ti,ina238";
reg = <0x41>;
shunt-resistor = <1000>;
};
power-sensor@44 {
compatible = "ti,ina238";
reg = <0x44>;
shunt-resistor = <1000>;
};
power-sensor@45 {
compatible = "ti,ina238";
reg = <0x45>;
shunt-resistor = <1000>;
};
temperature-sensor@4b {
compatible = "ti,tmp75";
reg = <0x4b>;
};
};
&i2c3 {
@@ -276,11 +329,15 @@
reg = <0x49>;
};
power-monitor@22 {
compatible = "lltc,ltc4286";
reg = <0x22>;
adi,vrange-low-enable;
shunt-resistor-micro-ohms = <500>;
power-monitor@44 {
compatible = "lltc,ltc4287";
reg = <0x44>;
shunt-resistor-micro-ohms = <250>;
};
power-monitor@40 {
compatible = "infineon,xdp710";
reg = <0x40>;
};
};
@@ -321,6 +378,14 @@
&i2c9 {
status = "okay";
mctp-controller;
multi-master;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
gpio@30 {
compatible = "nxp,pca9555";
reg = <0x30>;
@@ -340,33 +405,6 @@
"","","","";
};
i2c-mux@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
imux24: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux25: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux26: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux27: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
// PTTV FRU
eeprom@52 {
compatible = "atmel,24c64";
@@ -376,6 +414,31 @@
&i2c11 {
status = "okay";
gpio@30 {
compatible = "nxp,pca9555";
reg = <0x30>;
gpio-controller;
#gpio-cells = <2>;
};
gpio@31 {
compatible = "nxp,pca9555";
reg = <0x31>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"","","","",
"","","presence-cmm","",
"","","","",
"","","","";
};
// Aegis FRU
eeprom@52 {
compatible = "atmel,24c64";
reg = <0x52>;
};
};
&i2c12 {
@@ -399,6 +462,30 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
power-monitor@61 {
compatible = "isil,isl69260";
reg = <0x61>;
};
power-monitor@62 {
compatible = "isil,isl69260";
reg = <0x62>;
};
power-monitor@63 {
compatible = "isil,isl69260";
reg = <0x63>;
};
power-monitor@64 {
compatible = "infineon,xdpe152c4";
reg = <0x64>;
};
power-monitor@66 {
compatible = "infineon,xdpe152c4";
reg = <0x66>;
};
power-monitor@68 {
compatible = "infineon,xdpe152c4";
reg = <0x68>;
};
};
imux29: i2c@1 {
#address-cells = <1>;
@@ -497,13 +584,14 @@
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "power-button","power-host-control",
"reset-button","","led-power","","","",
/*Q0-Q7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","power-chassis-control","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","led-identify-gate","",
/*V0-V7*/ "","","","",
"rtc-battery-voltage-read-enable","","","",
"rtc-battery-voltage-read-enable","",
"power-chassis-good","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
@@ -521,7 +609,6 @@
&sgpiom0 {
status = "okay";
max-ngpios = <128>;
ngpios = <128>;
bus-frequency = <2000000>;
gpio-line-names =
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts
+374 -144
View File
@@ -11,7 +11,8 @@
compatible = "facebook,minerva-cmc", "aspeed,ast2600";
aliases {
serial5 = &uart5;
serial4 = &uart5;
serial5 = &uart6;
/*
* PCA9548 (2-0077) provides 8 channels connecting to
* 6 pcs of FCB (Fan Controller Board).
@@ -22,6 +23,8 @@
i2c19 = &imux19;
i2c20 = &imux20;
i2c21 = &imux21;
spi1 = &spi_gpio;
};
chosen {
@@ -43,11 +46,54 @@
leds {
compatible = "gpio-leds";
led-fan-fault {
label = "led-fan-fault";
led-0 {
label = "bmc_heartbeat_amber";
gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led-1 {
label = "fp_id_amber";
default-state = "off";
gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
};
led-2 {
label = "power_blue";
default-state = "off";
gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
};
led-3 {
label = "fan_status_led";
gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-4 {
label = "fan_fault_led_n";
gpios = <&leds_gpio 10 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
spi_gpio: spi {
status = "okay";
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
spi-max-frequency = <33000000>;
reg = <0>;
};
};
};
@@ -77,6 +123,10 @@
};
};
&mdio3 {
status = "okay";
};
&fmc {
status = "okay";
flash@0 {
@@ -94,10 +144,6 @@
};
};
&rtc {
status = "okay";
};
&sgpiom0 {
status = "okay";
ngpios = <128>;
@@ -119,14 +165,15 @@
shunt-resistor = <1000>;
};
power-monitor@67 {
compatible = "adi,ltc2945";
reg = <0x67>;
power-monitor@44 {
compatible = "lltc,ltc4287";
reg = <0x44>;
shunt-resistor-micro-ohms = <2000>;
};
power-monitor@68 {
compatible = "adi,ltc2945";
reg = <0x68>;
power-monitor@43 {
compatible = "infineon,xdp710";
reg = <0x43>;
};
leds_gpio: gpio@19 {
@@ -145,9 +192,9 @@
reg = <0x4b>;
};
temperature-sensor@48 {
temperature-sensor@4f {
compatible = "ti,tmp75";
reg = <0x48>;
reg = <0x4f>;
};
eeprom@54 {
@@ -182,6 +229,35 @@
#address-cells = <1>;
#size-cells = <0>;
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <1000>;
};
power-sensor@41 {
compatible = "ti,ina238";
reg = <0x41>;
shunt-resistor = <1000>;
};
power-sensor@44 {
compatible = "ti,ina238";
reg = <0x44>;
shunt-resistor = <1000>;
};
power-sensor@45 {
compatible = "ti,ina238";
reg = <0x45>;
shunt-resistor = <1000>;
};
temperature-sensor@4b {
compatible = "ti,tmp75";
reg = <0x4b>;
};
};
imux17: i2c@1 {
@@ -200,6 +276,35 @@
#address-cells = <1>;
#size-cells = <0>;
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <1000>;
};
power-sensor@41 {
compatible = "ti,ina238";
reg = <0x41>;
shunt-resistor = <1000>;
};
power-sensor@44 {
compatible = "ti,ina238";
reg = <0x44>;
shunt-resistor = <1000>;
};
power-sensor@45 {
compatible = "ti,ina238";
reg = <0x45>;
shunt-resistor = <1000>;
};
temperature-sensor@4b {
compatible = "ti,tmp75";
reg = <0x4b>;
};
};
imux18: i2c@2 {
@@ -218,6 +323,35 @@
#address-cells = <1>;
#size-cells = <0>;
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <1000>;
};
power-sensor@41 {
compatible = "ti,ina238";
reg = <0x41>;
shunt-resistor = <1000>;
};
power-sensor@44 {
compatible = "ti,ina238";
reg = <0x44>;
shunt-resistor = <1000>;
};
power-sensor@45 {
compatible = "ti,ina238";
reg = <0x45>;
shunt-resistor = <1000>;
};
temperature-sensor@4b {
compatible = "ti,tmp75";
reg = <0x4b>;
};
};
imux19: i2c@3 {
@@ -236,9 +370,38 @@
#address-cells = <1>;
#size-cells = <0>;
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <1000>;
};
power-sensor@41 {
compatible = "ti,ina238";
reg = <0x41>;
shunt-resistor = <1000>;
};
power-sensor@44 {
compatible = "ti,ina238";
reg = <0x44>;
shunt-resistor = <1000>;
};
power-sensor@45 {
compatible = "ti,ina238";
reg = <0x45>;
shunt-resistor = <1000>;
};
temperature-sensor@4b {
compatible = "ti,tmp75";
reg = <0x4b>;
};
};
imux20: i2c@4 {
imux20: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
@@ -254,9 +417,37 @@
#address-cells = <1>;
#size-cells = <0>;
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <1000>;
};
power-sensor@41 {
compatible = "ti,ina238";
reg = <0x41>;
shunt-resistor = <1000>;
};
power-sensor@44 {
compatible = "ti,ina238";
reg = <0x44>;
shunt-resistor = <1000>;
};
power-sensor@45 {
compatible = "ti,ina238";
reg = <0x45>;
shunt-resistor = <1000>;
};
temperature-sensor@4b {
compatible = "ti,tmp75";
reg = <0x4b>;
};
};
imux21: i2c@5 {
imux21: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
@@ -272,6 +463,34 @@
#address-cells = <1>;
#size-cells = <0>;
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <1000>;
};
power-sensor@41 {
compatible = "ti,ina238";
reg = <0x41>;
shunt-resistor = <1000>;
};
power-sensor@44 {
compatible = "ti,ina238";
reg = <0x44>;
shunt-resistor = <1000>;
};
power-sensor@45 {
compatible = "ti,ina238";
reg = <0x45>;
shunt-resistor = <1000>;
};
temperature-sensor@4b {
compatible = "ti,tmp75";
reg = <0x4b>;
};
};
};
};
@@ -302,14 +521,16 @@
&i2c9 {
status = "okay";
};
&i2c10 {
status = "okay";
};
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
&i2c11 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&i2c12 {
@@ -338,6 +559,11 @@
compatible = "atmel,24c128";
reg = <0x50>;
};
eeprom@56 {
compatible = "atmel,24c64";
reg = <0x56>;
};
};
&adc0 {
@@ -355,6 +581,10 @@
pinctrl-0 = <&pinctrl_adc10_default>;
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
@@ -381,12 +611,12 @@
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","power-chassis-control","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","host0-ready",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","BAT_DETECT","","","",
/*V0-V7*/ "","","","","BAT_DETECT","","power-chassis-good","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","BLADE_UART_SEL3","","","","","",
/*Y0-Y7*/ "","","","","","","","",
@@ -397,118 +627,118 @@
gpio-line-names =
/*"input pin","output pin"*/
/*A0 - A7*/
"PRSNT_MTIA_BLADE0_N","PWREN_MTIA_BLADE0_EN",
"PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN",
"PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN",
"PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN",
"PRSNT_MTIA_BLADE4_N","PWREN_MTIA_BLADE4_EN",
"PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN",
"PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN",
"PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN",
"PRSNT_MTIA_BLADE0_N","PWREN_MTIA_BLADE0_EN_N",
"PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN_N",
"PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN_N",
"PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN_N",
"PRSNT_MTIA_BLADE4_N","PWREN_MTIA_BLADE4_EN_N",
"PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN_N",
"PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN_N",
"PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN_N",
/*B0 - B7*/
"PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN",
"PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN",
"PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN",
"PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN",
"PRSNT_MTIA_BLADE12_N","PWREN_MTIA_BLADE12_EN",
"PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN",
"PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN",
"PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN",
"PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN_N",
"PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN_N",
"PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN_N",
"PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN_N",
"PRSNT_MTIA_BLADE12_N","PWREN_MTIA_BLADE12_EN_N",
"PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN_N",
"PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN_N",
"PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN_N",
/*C0 - C7*/
"PRSNT_NW_BLADE0_N","PWREN_NW_BLADE0_EN",
"PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN",
"PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN",
"PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN",
"PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN",
"PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN",
"PRSNT_FCB_TOP_0_N","PWREN_MTIA_BLADE0_HSC_EN",
"PRSNT_FCB_TOP_1_N","PWREN_MTIA_BLADE1_HSC_EN",
"PRSNT_NW_BLADE0_N","PWREN_NW_BLADE0_EN_N",
"PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN_N",
"PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN_N",
"PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN_N",
"PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN_N",
"PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN_N",
"PRSNT_FCB_TOP_0_N","PWREN_MTIA_BLADE0_HSC_EN_N",
"PRSNT_FCB_TOP_1_N","PWREN_MTIA_BLADE1_HSC_EN_N",
/*D0 - D7*/
"PRSNT_FCB_MIDDLE_0_N","PWREN_MTIA_BLADE2_HSC_EN",
"PRSNT_FCB_MIDDLE_1_N","PWREN_MTIA_BLADE3_HSC_EN",
"PRSNT_FCB_BOTTOM_0_N","PWREN_MTIA_BLADE4_HSC_EN",
"PRSNT_FCB_BOTTOM_1_N","PWREN_MTIA_BLADE5_HSC_EN",
"PWRGD_MTIA_BLADE0_PWROK_L_BUF","PWREN_MTIA_BLADE6_HSC_EN",
"PWRGD_MTIA_BLADE1_PWROK_L_BUF","PWREN_MTIA_BLADE7_HSC_EN",
"PWRGD_MTIA_BLADE2_PWROK_L_BUF","PWREN_MTIA_BLADE8_HSC_EN",
"PWRGD_MTIA_BLADE3_PWROK_L_BUF","PWREN_MTIA_BLADE9_HSC_EN",
"PRSNT_FCB_MIDDLE_0_N","PWREN_MTIA_BLADE2_HSC_EN_N",
"PRSNT_FCB_MIDDLE_1_N","PWREN_MTIA_BLADE3_HSC_EN_N",
"PRSNT_FCB_BOTTOM_1_N","PWREN_MTIA_BLADE4_HSC_EN_N",
"PRSNT_FCB_BOTTOM_0_N","PWREN_MTIA_BLADE5_HSC_EN_N",
"PWRGD_MTIA_BLADE0_PWROK_N","PWREN_MTIA_BLADE6_HSC_EN_N",
"PWRGD_MTIA_BLADE1_PWROK_N","PWREN_MTIA_BLADE7_HSC_EN_N",
"PWRGD_MTIA_BLADE2_PWROK_N","PWREN_MTIA_BLADE8_HSC_EN_N",
"PWRGD_MTIA_BLADE3_PWROK_N","PWREN_MTIA_BLADE9_HSC_EN_N",
/*E0 - E7*/
"PWRGD_MTIA_BLADE4_PWROK_L_BUF","PWREN_MTIA_BLADE10_HSC_EN",
"PWRGD_MTIA_BLADE5_PWROK_L_BUF","PWREN_MTIA_BLADE11_HSC_EN",
"PWRGD_MTIA_BLADE6_PWROK_L_BUF","PWREN_MTIA_BLADE12_HSC_EN",
"PWRGD_MTIA_BLADE7_PWROK_L_BUF","PWREN_MTIA_BLADE13_HSC_EN",
"PWRGD_MTIA_BLADE8_PWROK_L_BUF","PWREN_MTIA_BLADE14_HSC_EN",
"PWRGD_MTIA_BLADE9_PWROK_L_BUF","PWREN_MTIA_BLADE15_HSC_EN",
"PWRGD_MTIA_BLADE10_PWROK_L_BUF","PWREN_NW_BLADE0_HSC_EN",
"PWRGD_MTIA_BLADE11_PWROK_L_BUF","PWREN_NW_BLADE1_HSC_EN",
"PWRGD_MTIA_BLADE4_PWROK_N","PWREN_MTIA_BLADE10_HSC_EN_N",
"PWRGD_MTIA_BLADE5_PWROK_N","PWREN_MTIA_BLADE11_HSC_EN_N",
"PWRGD_MTIA_BLADE6_PWROK_N","PWREN_MTIA_BLADE12_HSC_EN_N",
"PWRGD_MTIA_BLADE7_PWROK_N","PWREN_MTIA_BLADE13_HSC_EN_N",
"PWRGD_MTIA_BLADE8_PWROK_N","PWREN_MTIA_BLADE14_HSC_EN_N",
"PWRGD_MTIA_BLADE9_PWROK_N","PWREN_MTIA_BLADE15_HSC_EN_N",
"PWRGD_MTIA_BLADE10_PWROK_N","PWREN_NW_BLADE0_HSC_EN_N",
"PWRGD_MTIA_BLADE11_PWROK_N","PWREN_NW_BLADE1_HSC_EN_N",
/*F0 - F7*/
"PWRGD_MTIA_BLADE12_PWROK_L_BUF","PWREN_NW_BLADE2_HSC_EN",
"PWRGD_MTIA_BLADE13_PWROK_L_BUF","PWREN_NW_BLADE3_HSC_EN",
"PWRGD_MTIA_BLADE14_PWROK_L_BUF","PWREN_NW_BLADE4_HSC_EN",
"PWRGD_MTIA_BLADE15_PWROK_L_BUF","PWREN_NW_BLADE5_HSC_EN",
"PWRGD_NW_BLADE0_PWROK_L_BUF","PWREN_FCB_TOP_L_EN",
"PWRGD_NW_BLADE1_PWROK_L_BUF","PWREN_FCB_TOP_R_EN",
"PWRGD_NW_BLADE2_PWROK_L_BUF","PWREN_FCB_MIDDLE_L_EN",
"PWRGD_NW_BLADE3_PWROK_L_BUF","PWREN_FCB_MIDDLE_R_EN",
"PWRGD_MTIA_BLADE12_PWROK_N","PWREN_NW_BLADE2_HSC_EN_N",
"PWRGD_MTIA_BLADE13_PWROK_N","PWREN_NW_BLADE3_HSC_EN_N",
"PWRGD_MTIA_BLADE14_PWROK_N","PWREN_NW_BLADE4_HSC_EN_N",
"PWRGD_MTIA_BLADE15_PWROK_N","PWREN_NW_BLADE5_HSC_EN_N",
"PWRGD_NW_BLADE0_PWROK_N","PWREN_FCB_TOP_0_EN_N",
"PWRGD_NW_BLADE1_PWROK_N","PWREN_FCB_TOP_1_EN_N",
"PWRGD_NW_BLADE2_PWROK_N","PWREN_FCB_MIDDLE_0_EN_N",
"PWRGD_NW_BLADE3_PWROK_N","PWREN_FCB_MIDDLE_1_EN_N",
/*G0 - G7*/
"PWRGD_NW_BLADE4_PWROK_L_BUF","PWREN_FCB_BOTTOM_L_EN",
"PWRGD_NW_BLADE5_PWROK_L_BUF","PWREN_FCB_BOTTOM_R_EN",
"PWRGD_FCB_TOP_0_PWROK_L_BUF","FM_CMM_AC_CYCLE_N",
"PWRGD_FCB_TOP_1_PWROK_L_BUF","MGMT_SFP_TX_DIS",
"PWRGD_FCB_MIDDLE_0_PWROK_L_BUF","",
"PWRGD_FCB_MIDDLE_1_PWROK_L_BUF","RST_I2CRST_MTIA_BLADE0_1_N",
"PWRGD_FCB_BOTTOM_0_PWROK_L_BUF","RST_I2CRST_MTIA_BLADE2_3_N",
"PWRGD_FCB_BOTTOM_1_PWROK_L_BUF","RST_I2CRST_MTIA_BLADE4_5_N",
"PWRGD_NW_BLADE4_PWROK_N","PWREN_FCB_BOTTOM_1_EN_N",
"PWRGD_NW_BLADE5_PWROK_N","PWREN_FCB_BOTTOM_0_EN_N",
"PWRGD_FCB_TOP_0_PWROK_N","FM_CMM_AC_CYCLE_N",
"PWRGD_FCB_TOP_1_PWROK_N","MGMT_SFP_TX_DIS",
"PWRGD_FCB_MIDDLE_0_PWROK_N","FM_MDIO_SW_SEL",
"PWRGD_FCB_MIDDLE_1_PWROK_N","FM_P24V_SMPWR_EN",
"PWRGD_FCB_BOTTOM_1_PWROK_N","",
"PWRGD_FCB_BOTTOM_0_PWROK_N","",
/*H0 - H7*/
"LEAK_DETECT_MTIA_BLADE0_N_BUF","RST_I2CRST_MTIA_BLADE6_7_N",
"LEAK_DETECT_MTIA_BLADE1_N_BUF","RST_I2CRST_MTIA_BLADE8_9_N",
"LEAK_DETECT_MTIA_BLADE2_N_BUF","RST_I2CRST_MTIA_BLADE10_11_N",
"LEAK_DETECT_MTIA_BLADE3_N_BUF","RST_I2CRST_MTIA_BLADE12_13_N",
"LEAK_DETECT_MTIA_BLADE4_N_BUF","RST_I2CRST_MTIA_BLADE14_15_N",
"LEAK_DETECT_MTIA_BLADE5_N_BUF","RST_I2CRST_NW_BLADE0_1_2_N",
"LEAK_DETECT_MTIA_BLADE6_N_BUF","RST_I2CRST_NW_BLADE3_4_5_N",
"LEAK_DETECT_MTIA_BLADE7_N_BUF","RST_I2CRST_FCB_N",
"LEAK_DETECT_MTIA_BLADE0_N","",
"LEAK_DETECT_MTIA_BLADE1_N","",
"LEAK_DETECT_MTIA_BLADE2_N","",
"LEAK_DETECT_MTIA_BLADE3_N","",
"LEAK_DETECT_MTIA_BLADE4_N","",
"LEAK_DETECT_MTIA_BLADE5_N","",
"LEAK_DETECT_MTIA_BLADE6_N","",
"LEAK_DETECT_MTIA_BLADE7_N","",
/*I0 - I7*/
"LEAK_DETECT_MTIA_BLADE8_N_BUF","RST_I2CRST_FCB_B_L_N",
"LEAK_DETECT_MTIA_BLADE9_N_BUF","RST_I2CRST_FCB_B_R_N",
"LEAK_DETECT_MTIA_BLADE10_N_BUF","RST_I2CRST_FCB_M_L_N",
"LEAK_DETECT_MTIA_BLADE11_N_BUF","RST_I2CRST_FCB_M_R_N",
"LEAK_DETECT_MTIA_BLADE12_N_BUF","RST_I2CRST_FCB_T_L_N",
"LEAK_DETECT_MTIA_BLADE13_N_BUF","RST_I2CRST_FCB_T_R_N",
"LEAK_DETECT_MTIA_BLADE14_N_BUF","BMC_READY",
"LEAK_DETECT_MTIA_BLADE15_N_BUF","wFM_88E6393X_BIN_UPDATE_EN_N",
"LEAK_DETECT_MTIA_BLADE8_N","RST_I2CRST_FCB_BOTTOM_1_N",
"LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_BOTTOM_0_N",
"LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_MIDDLE_0_N",
"LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_MIDDLE_1_N",
"LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_TOP_0_N",
"LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_TOP_1_N",
"LEAK_DETECT_MTIA_BLADE14_N","BMC_READY",
"LEAK_DETECT_MTIA_BLADE15_N","FM_88E6393X_BIN_UPDATE_EN_N",
/*J0 - J7*/
"LEAK_DETECT_NW_BLADE0_N_BUF","WATER_VALVE_CLOSED_N",
"LEAK_DETECT_NW_BLADE1_N_BUF","",
"LEAK_DETECT_NW_BLADE2_N_BUF","",
"LEAK_DETECT_NW_BLADE3_N_BUF","",
"LEAK_DETECT_NW_BLADE4_N_BUF","",
"LEAK_DETECT_NW_BLADE5_N_BUF","",
"MTIA_BLADE0_STATUS_LED","",
"MTIA_BLADE1_STATUS_LED","",
"LEAK_DETECT_NW_BLADE0_N","WATER_VALVE_CLOSED_N",
"LEAK_DETECT_NW_BLADE1_N","",
"LEAK_DETECT_NW_BLADE2_N","",
"LEAK_DETECT_NW_BLADE3_N","",
"LEAK_DETECT_NW_BLADE4_N","",
"LEAK_DETECT_NW_BLADE5_N","",
"PWRGD_MTIA_BLADE0_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE1_HSC_PWROK_N","",
/*K0 - K7*/
"MTIA_BLADE2_STATUS_LED","",
"MTIA_BLADE3_STATUS_LED","",
"MTIA_BLADE4_STATUS_LED","",
"MTIA_BLADE5_STATUS_LED","",
"MTIA_BLADE6_STATUS_LED","",
"MTIA_BLADE7_STATUS_LED","",
"MTIA_BLADE8_STATUS_LED","",
"MTIA_BLADE9_STATUS_LED","",
"PWRGD_MTIA_BLADE2_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE3_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE4_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE5_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE6_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE7_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE8_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE9_HSC_PWROK_N","",
/*L0 - L7*/
"MTIA_BLADE10_STATUS_LED","",
"MTIA_BLADE11_STATUS_LED","",
"MTIA_BLADE12_STATUS_LED","",
"MTIA_BLADE13_STATUS_LED","",
"MTIA_BLADE14_STATUS_LED","",
"MTIA_BLADE15_STATUS_LED","",
"NW_BLADE0_STATUS_LED","",
"NW_BLADE1_STATUS_LED","",
"PWRGD_MTIA_BLADE10_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE11_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE12_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE13_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE14_HSC_PWROK_N","",
"PWRGD_MTIA_BLADE15_HSC_PWROK_N","",
"PWRGD_NW_BLADE0_HSC_PWROK_N","",
"PWRGD_NW_BLADE1_HSC_PWROK_N","",
/*M0 - M7*/
"NW_BLADE2_STATUS_LED","",
"NW_BLADE3_STATUS_LED","",
"NW_BLADE4_STATUS_LED","",
"NW_BLADE5_STATUS_LED","",
"PWRGD_NW_BLADE2_HSC_PWROK_N","",
"PWRGD_NW_BLADE3_HSC_PWROK_N","",
"PWRGD_NW_BLADE4_HSC_PWROK_N","",
"PWRGD_NW_BLADE5_HSC_PWROK_N","",
"RPU_READY","",
"IT_GEAR_RPU_LINK_N","",
"IT_GEAR_LEAK","",
@@ -516,28 +746,28 @@
/*N0 - N7*/
"VALVE_STS0","",
"VALVE_STS1","",
"VALVE_STS2","",
"VALVE_STS3","",
"CR_TOGGLE_BOOT_BUF_N","",
"CMM_LC_RDY_LED_N","",
"CMM_LC_UNRDY_LED_N","",
"PCA9555_IRQ0_N","",
"PCA9555_IRQ1_N","",
"CR_TOGGLE_BOOT_N","",
"IRQ_FCB_TOP0_N","",
"IRQ_FCB_TOP1_N","",
"CMM_CABLE_CARTRIDGE_PRSNT_BOT_N","",
/*O0 - O7*/
"CMM_CABLE_CARTRIDGE_PRSNT_TOP_N","",
"BOT_BCB_CABLE_PRSNT_N","",
"TOP_BCB_CABLE_PRSNT_N","",
"CHASSIS0_LEAK_Q_N","",
"CHASSIS1_LEAK_Q_N","",
"LEAK0_DETECT","",
"LEAK1_DETECT","",
"MGMT_SFP_PRSNT_N","",
"IRQ_FCB_MID0_N","",
"IRQ_FCB_MID1_N","",
"CHASSIS_LEAK0_DETECT_N","",
"CHASSIS_LEAK1_DETECT_N","",
"VALVE_RMON_A_1","",
/*P0 - P7*/
"MGMT_SFP_TX_FAULT","",
"MGMT_SFP_RX_LOS","",
"","",
"","",
"","",
"","",
"","",
"","";
"VALVE_RMON_A_2","",
"VALVE_RMON_B_1","",
"VALVE_RMON_B_2","",
"RPU_READY_SPARE","",
"IT_GEAR_LEAK_SPARE","",
"IT_GEAR_RPU_LINK_SPARE_N","",
"IRQ_FCB_BOT0_N","",
"IRQ_FCB_BOT0_N","";
};
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge-4u.dts
+21
View File
@@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2024 IBM Corp.
/dts-v1/;
#include "aspeed-bmc-ibm-blueridge.dts"
/ {
model = "Blueridge 4U";
};
&i2c3 {
power-supply@6a {
compatible = "ibm,cffps";
reg = <0x6a>;
};
power-supply@6b {
compatible = "ibm,cffps";
reg = <0x6b>;
};
};
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts
+1686
View File
File diff suppressed because it is too large Load Diff
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts
-5
View File
@@ -570,11 +570,6 @@
status = "okay";
};
&xdma {
status = "okay";
memory-region = <&vga_memory>;
};
&kcs2 {
status = "okay";
aspeed,lpc-io-reg = <0xca8 0xcac>;
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts
-5
View File
@@ -2486,11 +2486,6 @@
status = "okay";
};
&xdma {
status = "okay";
memory-region = <&vga_memory>;
};
&kcs2 {
status = "okay";
aspeed,lpc-io-reg = <0xca8 0xcac>;
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts
+3876
View File
File diff suppressed because it is too large Load Diff
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts
-5
View File
@@ -1722,11 +1722,6 @@
status = "okay";
};
&xdma {
status = "okay";
memory-region = <&vga_memory>;
};
&kcs2 {
status = "okay";
aspeed,lpc-io-reg = <0xca8 0xcac>;
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-system1.dts
+3 -3
View File
@@ -1138,7 +1138,7 @@
reg = <6>;
temperature-sensor@4c {
compatible = "ti,tmp423";
compatible = "ti,tmp432";
reg = <0x4c>;
};
};
@@ -1599,7 +1599,7 @@
reg = <6>;
temperature-sensor@4c {
compatible = "ti,tmp423";
compatible = "ti,tmp432";
reg = <0x4c>;
};
};
@@ -1615,7 +1615,7 @@
};
temperature-sensor@4c {
compatible = "ti,tmp423";
compatible = "ti,tmp432";
reg = <0x4c>;
};
};
arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts
-4
View File
@@ -814,10 +814,6 @@
memory-region = <&gfx_memory>;
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&wdt1 {
aspeed,reset-type = "none";
aspeed,external-signal;
arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-on5263m5.dts
-4
View File
@@ -123,10 +123,6 @@
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
arch/arm/boot/dts/aspeed/aspeed-bmc-intel-s2600wf.dts
-4
View File
@@ -118,10 +118,6 @@
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts
-4
View File
@@ -263,10 +263,6 @@
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&gpio {
pin_gpio_b0 {
gpio-hog;
arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts
-4
View File
@@ -284,10 +284,6 @@
memory-region = <&gfx_memory>;
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&ibt {
status = "okay";
};
arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts
-4
View File
@@ -289,10 +289,6 @@
memory-region = <&gfx_memory>;
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
arch/arm/boot/dts/aspeed/aspeed-bmc-opp-swift.dts
-4
View File
@@ -938,10 +938,6 @@
memory-region = <&gfx_memory>;
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&wdt1 {
aspeed,reset-type = "none";
aspeed,external-signal;
arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts
-5
View File
@@ -870,11 +870,6 @@
<&pinctrl_lsirq_default>;
};
&xdma {
status = "okay";
memory-region = <&vga_memory>;
};
&kcs2 {
status = "okay";
aspeed,lpc-io-reg = <0xca8 0xcac>;
arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts
-9
View File
@@ -661,10 +661,6 @@
memory-region = <&gfx_memory>;
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&wdt1 {
aspeed,reset-type = "none";
aspeed,external-signal;
@@ -696,9 +692,4 @@
memory-region = <&video_engine_memory>;
};
&xdma {
status = "okay";
memory-region = <&vga_memory>;
};
#include "ibm-power9-dual.dtsi"

Some files were not shown because too many files have changed in this diff Show More