dt-bindings: clock: qoriq-clock: convert to yaml format
Convert qoria-clock DT binding to yaml format. Split to two files qoriq-clock.yaml and qoriq-clock-legancy.yaml. Addtional change: - Remove clock consumer part in example - Fixed example dts error - Deprecated legancy node - fsl,b4420-clockgen and fsl,b4860-clockgen fallback to fsl,b4-clockgen. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240701205809.1978389-1-Frank.Li@nxp.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Frank Li
Stephen Boyd
@@ -0,0 +1,84 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Legacy Clock Block on Freescale QorIQ Platforms
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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description: |
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These nodes are deprecated. Kernels should continue to support
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device trees with these nodes, but new device trees should not use them.
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Most of the bindings are from the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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properties:
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compatible:
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enum:
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- fsl,qoriq-core-pll-1.0
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- fsl,qoriq-core-pll-2.0
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- fsl,qoriq-core-mux-1.0
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- fsl,qoriq-core-mux-2.0
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- fsl,qoriq-sysclk-1.0
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- fsl,qoriq-sysclk-2.0
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- fsl,qoriq-platform-pll-1.0
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- fsl,qoriq-platform-pll-2.0
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 4
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clock-names:
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minItems: 1
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maxItems: 4
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clock-output-names:
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minItems: 1
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maxItems: 8
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'#clock-cells':
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minimum: 0
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maximum: 1
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required:
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- compatible
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- '#clock-cells'
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,qoriq-sysclk-1.0
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- fsl,qoriq-sysclk-2.0
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then:
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properties:
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'#clock-cells':
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const: 0
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,qoriq-core-pll-1.0
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- fsl,qoriq-core-pll-2.0
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then:
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properties:
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'#clock-cells':
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const: 1
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description: |
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* 0 - equal to the PLL frequency
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* 1 - equal to the PLL frequency divided by 2
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* 2 - equal to the PLL frequency divided by 4
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@@ -0,0 +1,207 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Clock Block on Freescale QorIQ Platforms
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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description: |
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Freescale QorIQ chips take primary clocking input from the external
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SYSCLK signal. The SYSCLK input (frequency) is multiplied using
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multiple phase locked loops (PLL) to create a variety of frequencies
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which can then be passed to a variety of internal logic, including
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cores and peripheral IP blocks.
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Please refer to the Reference Manual for details.
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All references to "1.0" and "2.0" refer to the QorIQ chassis version to
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which the chip complies.
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Chassis Version Example Chips
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--------------- -------------
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1.0 p4080, p5020, p5040
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2.0 t4240
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Clock Provider
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The clockgen node should act as a clock provider, though in older device
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trees the children of the clockgen node are the clock providers.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- fsl,p2041-clockgen
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- fsl,p3041-clockgen
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- fsl,p4080-clockgen
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- fsl,p5020-clockgen
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- fsl,p5040-clockgen
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- const: fsl,qoriq-clockgen-1.0
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- items:
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- enum:
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- fsl,t1023-clockgen
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- fsl,t1024-clockgen
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- fsl,t1040-clockgen
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- fsl,t1042-clockgen
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- fsl,t2080-clockgen
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- fsl,t2081-clockgen
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- fsl,t4240-clockgen
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- const: fsl,qoriq-clockgen-2.0
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- items:
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- enum:
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- fsl,b4420-clockgen
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- fsl,b4860-clockgen
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- const: fsl,b4-clockgen
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- items:
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- enum:
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- fsl,ls1012a-clockgen
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- fsl,ls1021a-clockgen
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- fsl,ls1028a-clockgen
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- fsl,ls1043a-clockgen
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- fsl,ls1046a-clockgen
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- fsl,ls1088a-clockgen
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- fsl,ls2080a-clockgen
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- fsl,lx2160a-clockgen
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reg:
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maxItems: 1
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ranges: true
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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'#clock-cells':
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const: 2
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description: |
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The first cell of the clock specifier is the clock type, and the
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second cell is the clock index for the specified type.
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Type# Name Index Cell
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0 sysclk must be 0
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1 cmux index (n in CLKCnCSR)
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2 hwaccel index (n in CLKCGnHWACSR)
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3 fman 0 for fm1, 1 for fm2
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4 platform pll n=pll/(n+1). For example, when n=1,
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that means output_freq=PLL_freq/2.
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5 coreclk must be 0
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clock-frequency:
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description: Input system clock frequency (SYSCLK)
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clocks:
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items:
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- description:
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sysclk may be provided as an input clock. Either clock-frequency
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or clocks must be provided.
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- description:
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A second input clock, called "coreclk", may be provided if
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core PLLs are based on a different input clock from the
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platform PLL.
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minItems: 1
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clock-names:
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items:
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- const: sysclk
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- const: coreclk
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patternProperties:
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'^mux[0-9]@[a-f0-9]+$':
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deprecated: true
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$ref: fsl,qoriq-clock-legacy.yaml
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'^sysclk(-[a-z0-9]+)?$':
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deprecated: true
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$ref: fsl,qoriq-clock-legacy.yaml
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'^pll[0-9]@[a-f0-9]+$':
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deprecated: true
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$ref: fsl,qoriq-clock-legacy.yaml
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'^platform\-pll@[a-f0-9]+$':
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deprecated: true
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$ref: fsl,qoriq-clock-legacy.yaml
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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/* clock provider example */
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global-utilities@e1000 {
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compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
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reg = <0xe1000 0x1000>;
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clock-frequency = <133333333>;
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#clock-cells = <2>;
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};
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- |
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/* Legacy example */
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global-utilities@e1000 {
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compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
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reg = <0xe1000 0x1000>;
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ranges = <0x0 0xe1000 0x1000>;
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clock-frequency = <133333333>;
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#address-cells = <1>;
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#size-cells = <1>;
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#clock-cells = <2>;
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sysclk: sysclk {
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compatible = "fsl,qoriq-sysclk-1.0";
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clock-output-names = "sysclk";
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#clock-cells = <0>;
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};
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pll0: pll0@800 {
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compatible = "fsl,qoriq-core-pll-1.0";
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reg = <0x800 0x4>;
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#clock-cells = <1>;
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clocks = <&sysclk>;
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clock-output-names = "pll0", "pll0-div2";
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};
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pll1: pll1@820 {
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compatible = "fsl,qoriq-core-pll-1.0";
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reg = <0x820 0x4>;
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#clock-cells = <1>;
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clocks = <&sysclk>;
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clock-output-names = "pll1", "pll1-div2";
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};
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mux0: mux0@0 {
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compatible = "fsl,qoriq-core-mux-1.0";
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reg = <0x0 0x4>;
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#clock-cells = <0>;
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clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
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clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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clock-output-names = "cmux0";
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};
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mux1: mux1@20 {
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compatible = "fsl,qoriq-core-mux-1.0";
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reg = <0x20 0x4>;
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#clock-cells = <0>;
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clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
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clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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clock-output-names = "cmux1";
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};
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platform-pll@c00 {
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#clock-cells = <1>;
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reg = <0xc00 0x4>;
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compatible = "fsl,qoriq-platform-pll-1.0";
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clocks = <&sysclk>;
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clock-output-names = "platform-pll", "platform-pll-div2";
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};
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};
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@@ -1,212 +0,0 @@
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* Clock Block on Freescale QorIQ Platforms
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Freescale QorIQ chips take primary clocking input from the external
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SYSCLK signal. The SYSCLK input (frequency) is multiplied using
|
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multiple phase locked loops (PLL) to create a variety of frequencies
|
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which can then be passed to a variety of internal logic, including
|
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cores and peripheral IP blocks.
|
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Please refer to the Reference Manual for details.
|
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All references to "1.0" and "2.0" refer to the QorIQ chassis version to
|
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which the chip complies.
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Chassis Version Example Chips
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--------------- -------------
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1.0 p4080, p5020, p5040
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2.0 t4240, b4860
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1. Clock Block Binding
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Required properties:
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- compatible: Should contain a chip-specific clock block compatible
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string and (if applicable) may contain a chassis-version clock
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compatible string.
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Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
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* "fsl,p2041-clockgen"
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* "fsl,p3041-clockgen"
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* "fsl,p4080-clockgen"
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* "fsl,p5020-clockgen"
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* "fsl,p5040-clockgen"
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* "fsl,t1023-clockgen"
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* "fsl,t1024-clockgen"
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* "fsl,t1040-clockgen"
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* "fsl,t1042-clockgen"
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* "fsl,t2080-clockgen"
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* "fsl,t2081-clockgen"
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* "fsl,t4240-clockgen"
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* "fsl,b4420-clockgen"
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* "fsl,b4860-clockgen"
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* "fsl,ls1012a-clockgen"
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* "fsl,ls1021a-clockgen"
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* "fsl,ls1028a-clockgen"
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* "fsl,ls1043a-clockgen"
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* "fsl,ls1046a-clockgen"
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* "fsl,ls1088a-clockgen"
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* "fsl,ls2080a-clockgen"
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* "fsl,lx2160a-clockgen"
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Chassis-version clock strings include:
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* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
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* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
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- reg: Describes the address of the device's resources within the
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address space defined by its parent bus, and resource zero
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represents the clock register set
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Optional properties:
|
||||
- ranges: Allows valid translation between child's address space and
|
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parent's. Must be present if the device has sub-nodes.
|
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- #address-cells: Specifies the number of cells used to represent
|
||||
physical base addresses. Must be present if the device has
|
||||
sub-nodes and set to 1 if present
|
||||
- #size-cells: Specifies the number of cells used to represent
|
||||
the size of an address. Must be present if the device has
|
||||
sub-nodes and set to 1 if present
|
||||
- clock-frequency: Input system clock frequency (SYSCLK)
|
||||
- clocks: If clock-frequency is not specified, sysclk may be provided
|
||||
as an input clock. Either clock-frequency or clocks must be
|
||||
provided.
|
||||
A second input clock, called "coreclk", may be provided if
|
||||
core PLLs are based on a different input clock from the
|
||||
platform PLL.
|
||||
- clock-names: Required if a coreclk is present. Valid names are
|
||||
"sysclk" and "coreclk".
|
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|
||||
2. Clock Provider
|
||||
|
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The clockgen node should act as a clock provider, though in older device
|
||||
trees the children of the clockgen node are the clock providers.
|
||||
|
||||
When the clockgen node is a clock provider, #clock-cells = <2>.
|
||||
The first cell of the clock specifier is the clock type, and the
|
||||
second cell is the clock index for the specified type.
|
||||
|
||||
Type# Name Index Cell
|
||||
0 sysclk must be 0
|
||||
1 cmux index (n in CLKCnCSR)
|
||||
2 hwaccel index (n in CLKCGnHWACSR)
|
||||
3 fman 0 for fm1, 1 for fm2
|
||||
4 platform pll n=pll/(n+1). For example, when n=1,
|
||||
that means output_freq=PLL_freq/2.
|
||||
5 coreclk must be 0
|
||||
|
||||
3. Example
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
clock-frequency = <133333333>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
...
|
||||
clocks = <&clockgen 3 0>;
|
||||
...
|
||||
};
|
||||
}
|
||||
4. Legacy Child Nodes
|
||||
|
||||
NOTE: These nodes are deprecated. Kernels should continue to support
|
||||
device trees with these nodes, but new device trees should not use them.
|
||||
|
||||
Most of the bindings are from the common clock binding[1].
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : Should include one of the following:
|
||||
* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
|
||||
* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
|
||||
* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
|
||||
* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
|
||||
* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
|
||||
It takes parent's clock-frequency as its clock.
|
||||
* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
|
||||
It takes parent's clock-frequency as its clock.
|
||||
* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
|
||||
* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
|
||||
- #clock-cells: From common clock binding. The number of cells in a
|
||||
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
|
||||
clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
|
||||
For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
|
||||
clock-specifier cell may take the following values:
|
||||
* 0 - equal to the PLL frequency
|
||||
* 1 - equal to the PLL frequency divided by 2
|
||||
* 2 - equal to the PLL frequency divided by 4
|
||||
|
||||
Recommended properties:
|
||||
- clocks: Should be the phandle of input parent clock
|
||||
- clock-names: From common clock binding, indicates the clock name
|
||||
- clock-output-names: From common clock binding, indicates the names of
|
||||
output clocks
|
||||
- reg: Should be the offset and length of clock block base address.
|
||||
The length should be 4.
|
||||
|
||||
Legacy Example:
|
||||
/ {
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
clock-frequency = <133333333>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
||||
platform-pll: platform-pll@c00 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0xc00 0x4>;
|
||||
compatible = "fsl,qoriq-platform-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "platform-pll", "platform-pll-div2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example for legacy clock consumer:
|
||||
|
||||
/ {
|
||||
cpu0: PowerPC,e5500@0 {
|
||||
...
|
||||
clocks = <&mux0>;
|
||||
...
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user