Merge tag 'omap-for-v5.11/genpd-am335x-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/omap-genpd
Update am335x to boot without platform data With the driver updates done for genpd support, we can now update am335x dts files to boot with genpd and simple-pm-bus, and drop the related platform data. To do that, we need to do the following changes for am335x: - Add the remaining power domain and reset controller instances - Configure interconnect clocks for system timers as those are now managed separately by the drivers/clocksource drivers - Update control module, RTC, gpmc, debugss, emif, ocmcram, instr, and mpuss for device tree data and drop the legacy platform data - Update the interconnect instances to boot with gendp and simple-pm-bus - Drop the remaining platform data for am335x - Add kconfig option for OMAP_HWMOD to build it only for the SoCs that need it * tag 'omap-for-v5.11/genpd-am335x-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Build hwmod related code as needed ARM: OMAP2+: Drop legacy remaining legacy platform data for am3 ARM: dts: Use simple-pm-bus for genpd for am3 l3 ARM: dts: Use simple-pm-bus for genpd for am3 l4_per ARM: dts: Use simple-pm-bus for genpd for am3 l4_fast ARM: dts: Use simple-pm-bus for genpd for am3 l4_wkup ARM: OMAP2+: Drop legacy platform data for am3 mpuss ARM: OMAP2+: Drop legacy platform data for am3 instr ARM: OMAP2+: Drop legacy platform data for am3 ocmcram ARM: OMAP2+: Drop legacy platform data for am3 emif ARM: OMAP2+: Drop legacy platform data for am3 debugss ARM: OMAP2+: Drop legacy platform data for am3 and am4 gpmc ARM: OMAP2+: Drop legacy platform data for am3 wkup_m3 ARM: dts: Configure interconnect target module for am3 wkup_m3 ARM: dts: Configure RTC powerdomain for am3 ARM: OMAP2+: Drop legacy platform data for am3 control module ARM: dts: Configure also interconnect clocks for am4 system timer ARM: dts: am33xx: add remaining PRM instances Link: https://lore.kernel.org/r/pull-1606806458-694517@atomide.com-2 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -238,7 +238,6 @@
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&gpmc {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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status = "okay";
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gpmc,num-waitpins = <2>;
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pinctrl-names = "default";
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@@ -1,5 +1,8 @@
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&l4_wkup { /* 0x44c00000 */
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compatible = "ti,am33xx-l4-wkup", "simple-bus";
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compatible = "ti,am33xx-l4-wkup", "simple-pm-bus";
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power-domains = <&prm_wkup>;
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clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
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clock-names = "fck";
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reg = <0x44c00000 0x800>,
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<0x44c00800 0x800>,
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<0x44c01000 0x400>,
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@@ -12,7 +15,7 @@
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<0x00200000 0x44e00000 0x100000>; /* segment 2 */
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segment@0 { /* 0x44c00000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
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@@ -22,7 +25,7 @@
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};
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segment@100000 { /* 0x44d00000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
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@@ -34,23 +37,27 @@
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x0 0x4>;
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reg-names = "rev";
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clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x4000>;
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status = "disabled";
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};
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ranges = <0x00000000 0x00000000 0x4000>,
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<0x00080000 0x00080000 0x2000>;
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target-module@80000 { /* 0x44d80000, ap 6 10.0 */
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compatible = "ti,sysc";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x80000 0x2000>;
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wkup_m3: cpu@0 {
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compatible = "ti,am3352-wkup-m3";
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reg = <0x00000000 0x4000>,
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<0x00080000 0x2000>;
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reg-names = "umem", "dmem";
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resets = <&prm_wkup 3>;
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reset-names = "rstctrl";
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ti,pm-firmware = "am335x-pm-firmware.elf";
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};
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};
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};
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segment@200000 { /* 0x44e00000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */
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@@ -274,6 +281,9 @@
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x10000 0x4>;
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reg-names = "rev";
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clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>;
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clock-names = "fck";
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ti,no-idle;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00010000 0x00010000>,
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@@ -433,6 +443,7 @@
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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/* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
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power-domains = <&prm_rtc>;
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clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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@@ -658,7 +669,10 @@
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};
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&l4_fast { /* 0x4a000000 */
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compatible = "ti,am33xx-l4-fast", "simple-bus";
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compatible = "ti,am33xx-l4-fast", "simple-pm-bus";
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power-domains = <&prm_per>;
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clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>;
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clock-names = "fck";
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reg = <0x4a000000 0x800>,
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<0x4a000800 0x800>,
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<0x4a001000 0x400>;
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@@ -668,7 +682,7 @@
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ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
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segment@0 { /* 0x4a000000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
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@@ -837,7 +851,10 @@
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};
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&l4_per { /* 0x48000000 */
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compatible = "ti,am33xx-l4-per", "simple-bus";
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compatible = "ti,am33xx-l4-per", "simple-pm-bus";
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power-domains = <&prm_per>;
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clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
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clock-names = "fck";
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reg = <0x48000000 0x800>,
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<0x48000800 0x800>,
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<0x48001000 0x400>,
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@@ -855,7 +872,7 @@
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<0x46400000 0x46400000 0x400000>; /* l3 data port */
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segment@0 { /* 0x48000000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
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@@ -1466,7 +1483,7 @@
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};
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segment@100000 { /* 0x48100000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */
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@@ -1850,13 +1867,31 @@
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};
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segment@200000 { /* 0x48200000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00200000 0x010000>;
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target-module@0 {
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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power-domains = <&prm_mpu>;
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clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>;
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clock-names = "fck";
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ti,no-idle;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x10000>;
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mpu@0 {
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compatible = "ti,omap3-mpu";
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pm-sram = <&pm_sram_code
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&pm_sram_data>;
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};
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};
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};
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segment@300000 { /* 0x48300000 */
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */
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+124
-57
@@ -144,11 +144,28 @@
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};
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};
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pmu@4b000000 {
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compatible = "arm,cortex-a8-pmu";
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interrupts = <3>;
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reg = <0x4b000000 0x1000000>;
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ti,hwmods = "debugss";
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target-module@4b000000 {
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
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clock-names = "fck";
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ti,no-idle;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x4b000000 0x1000000>;
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target-module@140000 {
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x140000 0xec0000>;
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pmu@0 {
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compatible = "arm,cortex-a8-pmu";
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interrupts = <3>;
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};
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};
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};
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/*
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@@ -157,12 +174,6 @@
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap3-mpu";
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ti,hwmods = "mpu";
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pm-sram = <&pm_sram_code
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&pm_sram_data>;
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};
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};
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/*
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@@ -173,21 +184,15 @@
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* the whole bus hierarchy.
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*/
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ocp: ocp {
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compatible = "simple-bus";
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compatible = "simple-pm-bus";
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power-domains = <&prm_per>;
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clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main";
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l4_wkup: interconnect@44c00000 {
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wkup_m3: wkup_m3@100000 {
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compatible = "ti,am3352-wkup-m3";
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reg = <0x100000 0x4000>,
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<0x180000 0x2000>;
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reg-names = "umem", "dmem";
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ti,hwmods = "wkup_m3";
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ti,pm-firmware = "am335x-pm-firmware.elf";
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};
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};
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l4_per: interconnect@48000000 {
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};
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@@ -458,53 +463,89 @@
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};
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};
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ocmcram: sram@40300000 {
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compatible = "mmio-sram";
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reg = <0x40300000 0x10000>; /* 64k */
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ranges = <0x0 0x40300000 0x10000>;
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target-module@40300000 {
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
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clock-names = "fck";
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ti,no-idle;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x40300000 0x10000>;
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pm_sram_code: pm-code-sram@0 {
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compatible = "ti,sram";
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reg = <0x0 0x1000>;
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protect-exec;
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};
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ocmcram: sram@0 {
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compatible = "mmio-sram";
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reg = <0 0x10000>; /* 64k */
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ranges = <0 0 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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pm_sram_data: pm-data-sram@1000 {
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compatible = "ti,sram";
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reg = <0x1000 0x1000>;
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pool;
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pm_sram_code: pm-code-sram@0 {
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compatible = "ti,sram";
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reg = <0x0 0x1000>;
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protect-exec;
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};
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pm_sram_data: pm-data-sram@1000 {
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compatible = "ti,sram";
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reg = <0x1000 0x1000>;
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pool;
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};
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};
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};
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emif: emif@4c000000 {
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compatible = "ti,emif-am3352";
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reg = <0x4c000000 0x1000000>;
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ti,hwmods = "emif";
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interrupts = <101>;
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sram = <&pm_sram_code
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&pm_sram_data>;
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target-module@4c000000 {
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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reg = <0x4c000000 0x4>;
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reg-names = "rev";
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clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
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clock-names = "fck";
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ti,no-idle;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x4c000000 0x1000000>;
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emif: emif@0 {
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compatible = "ti,emif-am3352";
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reg = <0 0x1000000>;
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interrupts = <101>;
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sram = <&pm_sram_code
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&pm_sram_data>;
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};
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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ti,no-idle-on-init;
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reg = <0x50000000 0x2000>;
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interrupts = <100>;
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dmas = <&edma 52 0>;
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dma-names = "rxtx";
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gpmc,num-cs = <7>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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target-module@50000000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x50000000 4>,
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<0x50000010 4>,
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<0x50000014 4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
|
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clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
|
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clock-names = "fck";
|
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
|
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#interrupt-cells = <2>;
|
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gpio-controller;
|
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#gpio-cells = <2>;
|
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status = "disabled";
|
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ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
|
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<0x00000000 0x00000000 0x40000000>; /* data */
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|
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gpmc: gpmc@50000000 {
|
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compatible = "ti,am3352-gpmc";
|
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reg = <0x50000000 0x2000>;
|
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interrupts = <100>;
|
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dmas = <&edma 52 0>;
|
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dma-names = "rxtx";
|
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gpmc,num-cs = <7>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
sham_target: target-module@53100000 {
|
||||
@@ -601,12 +642,20 @@
|
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compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0xc00 0x100>;
|
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#reset-cells = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_wkup: prm@d00 {
|
||||
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0xd00 0x100>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_mpu: prm@e00 {
|
||||
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0xe00 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_device: prm@f00 {
|
||||
@@ -615,16 +664,31 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
prm_rtc: prm@1000 {
|
||||
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1000 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_gfx: prm@1100 {
|
||||
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1100 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
prm_cefuse: prm@1200 {
|
||||
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1200 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Preferred always-on timer for clocksource */
|
||||
&timer1_target {
|
||||
clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
|
||||
<&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
|
||||
clock-names = "fck", "ick";
|
||||
ti,no-reset-on-init;
|
||||
ti,no-idle;
|
||||
timer@0 {
|
||||
@@ -635,6 +699,9 @@
|
||||
|
||||
/* Preferred timer for clockevent */
|
||||
&timer2_target {
|
||||
clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
|
||||
<&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
|
||||
clock-names = "fck", "ick";
|
||||
ti,no-reset-on-init;
|
||||
ti,no-idle;
|
||||
timer@0 {
|
||||
|
||||
@@ -434,24 +434,41 @@
|
||||
ranges = <0x0 0x54400000 0x80000>;
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
dmas = <&edma 52 0>;
|
||||
dma-names = "rxtx";
|
||||
clocks = <&l3s_gclk>;
|
||||
target-module@50000000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x50000000 4>,
|
||||
<0x50000010 4>,
|
||||
<0x50000014 4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
reg = <0x50000000 0x2000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpmc,num-cs = <7>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
|
||||
<0x00000000 0x00000000 0x40000000>; /* data */
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
dmas = <&edma 52 0>;
|
||||
dma-names = "rxtx";
|
||||
clocks = <&l3s_gclk>;
|
||||
clock-names = "fck";
|
||||
reg = <0x50000000 0x2000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpmc,num-cs = <7>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@47900000 {
|
||||
|
||||
@@ -2,11 +2,15 @@
|
||||
menu "TI OMAP/AM/DM/DRA Family"
|
||||
depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
|
||||
|
||||
config OMAP_HWMOD
|
||||
bool
|
||||
|
||||
config ARCH_OMAP2
|
||||
bool "TI OMAP2"
|
||||
depends on ARCH_MULTI_V6
|
||||
select ARCH_OMAP2PLUS
|
||||
select CPU_V6
|
||||
select OMAP_HWMOD
|
||||
select SOC_HAS_OMAP2_SDRC
|
||||
|
||||
config ARCH_OMAP3
|
||||
@@ -14,6 +18,7 @@ config ARCH_OMAP3
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARCH_OMAP2PLUS
|
||||
select ARM_CPU_SUSPEND if PM
|
||||
select OMAP_HWMOD
|
||||
select OMAP_INTERCONNECT
|
||||
select PM_OPP if PM
|
||||
select PM if CPU_IDLE
|
||||
@@ -30,6 +35,7 @@ config ARCH_OMAP4
|
||||
select ARM_GIC
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select OMAP_HWMOD
|
||||
select OMAP_INTERCONNECT
|
||||
select OMAP_INTERCONNECT_BARRIER
|
||||
select PL310_ERRATA_588369 if CACHE_L2X0
|
||||
@@ -49,6 +55,7 @@ config SOC_OMAP5
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select ARM_ERRATA_798181 if SMP
|
||||
select OMAP_HWMOD
|
||||
select OMAP_INTERCONNECT
|
||||
select OMAP_INTERCONNECT_BARRIER
|
||||
select PM_OPP if PM
|
||||
@@ -71,6 +78,7 @@ config SOC_AM43XX
|
||||
select HAVE_ARM_TWD
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_775420
|
||||
select OMAP_HWMOD
|
||||
select OMAP_INTERCONNECT
|
||||
select ARM_CPU_SUSPEND if PM
|
||||
|
||||
@@ -84,6 +92,7 @@ config SOC_DRA7XX
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select IRQ_CROSSBAR
|
||||
select ARM_ERRATA_798181 if SMP
|
||||
select OMAP_HWMOD
|
||||
select OMAP_INTERCONNECT
|
||||
select OMAP_INTERCONNECT_BARRIER
|
||||
select PM_OPP if PM
|
||||
|
||||
@@ -8,18 +8,20 @@ ccflags-y := -I$(srctree)/$(src)/include \
|
||||
|
||||
# Common support
|
||||
obj-y := id.o io.o control.o devices.o fb.o pm.o \
|
||||
common.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
|
||||
omap_device.o omap-headsmp.o sram.o
|
||||
common.o dma.o omap-headsmp.o sram.o
|
||||
|
||||
hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
|
||||
omap_hwmod_common_data.o
|
||||
omap_hwmod_common_data.o \
|
||||
omap_hwmod_common_ipblock_data.o \
|
||||
omap_device.o display.o hdq1w.o \
|
||||
i2c.o wd_timer.o
|
||||
clock-common = clock.o
|
||||
secure-common = omap-smc.o omap-secure.o
|
||||
|
||||
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
|
||||
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
|
||||
obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
|
||||
obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
|
||||
@@ -194,7 +196,6 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
|
||||
obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
|
||||
|
||||
# hwmod data
|
||||
obj-y += omap_hwmod_common_ipblock_data.o
|
||||
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
|
||||
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
|
||||
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
|
||||
@@ -205,9 +206,6 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o
|
||||
obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
|
||||
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
|
||||
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o
|
||||
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o
|
||||
obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o
|
||||
obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o
|
||||
obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o
|
||||
|
||||
@@ -567,8 +567,6 @@ void __init am33xx_init_early(void)
|
||||
omap2_prcm_base_init();
|
||||
am33xx_powerdomains_init();
|
||||
am33xx_clockdomains_init();
|
||||
am33xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_clk_soc_init = am33xx_dt_clk_init;
|
||||
omap_secure_init();
|
||||
}
|
||||
|
||||
@@ -26,7 +26,6 @@ extern struct omap_hwmod_ocp_if am33xx_mpu__prcm;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main;
|
||||
extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
|
||||
extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
|
||||
|
||||
@@ -41,7 +40,6 @@ extern struct omap_hwmod am33xx_prcm_hwmod;
|
||||
extern struct omap_hwmod am33xx_ocmcram_hwmod;
|
||||
extern struct omap_hwmod am33xx_smartreflex0_hwmod;
|
||||
extern struct omap_hwmod am33xx_smartreflex1_hwmod;
|
||||
extern struct omap_hwmod am33xx_gpmc_hwmod;
|
||||
|
||||
extern struct omap_hwmod_class am33xx_emif_hwmod_class;
|
||||
extern struct omap_hwmod_class am33xx_l4_hwmod_class;
|
||||
|
||||
@@ -74,14 +74,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3s cfg -> gpmc */
|
||||
struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
|
||||
.master = &am33xx_l3_s_hwmod,
|
||||
.slave = &am33xx_gpmc_hwmod,
|
||||
.clk = "l3s_gclk",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3 main -> ocmc */
|
||||
struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
|
||||
@@ -218,50 +218,16 @@ struct omap_hwmod_class am33xx_control_hwmod_class = {
|
||||
.name = "control",
|
||||
};
|
||||
|
||||
|
||||
/* gpmc */
|
||||
static struct omap_hwmod_class_sysconfig gpmc_sysc = {
|
||||
.rev_offs = 0x0,
|
||||
.sysc_offs = 0x10,
|
||||
.syss_offs = 0x14,
|
||||
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
|
||||
.name = "gpmc",
|
||||
.sysc = &gpmc_sysc,
|
||||
};
|
||||
|
||||
struct omap_hwmod am33xx_gpmc_hwmod = {
|
||||
.name = "gpmc",
|
||||
.class = &am33xx_gpmc_hwmod_class,
|
||||
.clkdm_name = "l3s_clkdm",
|
||||
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
|
||||
.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
|
||||
.main_clk = "l3s_gclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static void omap_hwmod_am33xx_clkctrl(void)
|
||||
{
|
||||
CLKCTRL(am33xx_smartreflex0_hwmod,
|
||||
AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_smartreflex1_hwmod,
|
||||
AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
|
||||
}
|
||||
|
||||
void omap_hwmod_am33xx_reg(void)
|
||||
@@ -275,12 +241,10 @@ static void omap_hwmod_am43xx_clkctrl(void)
|
||||
AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_smartreflex1_hwmod,
|
||||
AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
|
||||
}
|
||||
|
||||
|
||||
@@ -1,294 +0,0 @@
|
||||
/*
|
||||
* omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
|
||||
*
|
||||
* Copyright (C) {2012} Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* This file is automatically generated from the AM33XX hardware databases.
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "omap_hwmod.h"
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
#include "control.h"
|
||||
#include "cm33xx.h"
|
||||
#include "prm33xx.h"
|
||||
#include "prm-regbits-33xx.h"
|
||||
#include "omap_hwmod_33xx_43xx_common_data.h"
|
||||
|
||||
/*
|
||||
* IP blocks
|
||||
*/
|
||||
|
||||
/* emif */
|
||||
static struct omap_hwmod am33xx_emif_hwmod = {
|
||||
.name = "emif",
|
||||
.class = &am33xx_emif_hwmod_class,
|
||||
.clkdm_name = "l3_clkdm",
|
||||
.flags = HWMOD_INIT_NO_IDLE,
|
||||
.main_clk = "dpll_ddr_m2_div2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_hs */
|
||||
static struct omap_hwmod am33xx_l4_hs_hwmod = {
|
||||
.name = "l4_hs",
|
||||
.class = &am33xx_l4_hwmod_class,
|
||||
.clkdm_name = "l4hs_clkdm",
|
||||
.flags = HWMOD_INIT_NO_IDLE,
|
||||
.main_clk = "l4hs_gclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
|
||||
{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
|
||||
};
|
||||
|
||||
/* wkup_m3 */
|
||||
static struct omap_hwmod am33xx_wkup_m3_hwmod = {
|
||||
.name = "wkup_m3",
|
||||
.class = &am33xx_wkup_m3_hwmod_class,
|
||||
.clkdm_name = "l4_wkup_aon_clkdm",
|
||||
/* Keep hardreset asserted */
|
||||
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
|
||||
.main_clk = "dpll_core_m4_div2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
|
||||
.rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
|
||||
.rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.rst_lines = am33xx_wkup_m3_resets,
|
||||
.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Modules omap_hwmod structures
|
||||
*
|
||||
* The following IPs are excluded for the moment because:
|
||||
* - They do not need an explicit SW control using omap_hwmod API.
|
||||
* - They still need to be validated with the driver
|
||||
* properly adapted to omap_hwmod / omap_device
|
||||
*
|
||||
* - cEFUSE (doesn't fall under any ocp_if)
|
||||
* - clkdiv32k
|
||||
* - ocp watch point
|
||||
*/
|
||||
#if 0
|
||||
/*
|
||||
* 'cefuse' class
|
||||
*/
|
||||
static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
|
||||
.name = "cefuse",
|
||||
};
|
||||
|
||||
static struct omap_hwmod am33xx_cefuse_hwmod = {
|
||||
.name = "cefuse",
|
||||
.class = &am33xx_cefuse_hwmod_class,
|
||||
.clkdm_name = "l4_cefuse_clkdm",
|
||||
.main_clk = "cefuse_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'clkdiv32k' class
|
||||
*/
|
||||
static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
|
||||
.name = "clkdiv32k",
|
||||
};
|
||||
|
||||
static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
|
||||
.name = "clkdiv32k",
|
||||
.class = &am33xx_clkdiv32k_hwmod_class,
|
||||
.clkdm_name = "clk_24mhz_clkdm",
|
||||
.main_clk = "clkdiv32k_ick",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* ocpwp */
|
||||
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
|
||||
.name = "ocpwp",
|
||||
};
|
||||
|
||||
static struct omap_hwmod am33xx_ocpwp_hwmod = {
|
||||
.name = "ocpwp",
|
||||
.class = &am33xx_ocpwp_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
.main_clk = "l4ls_gclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 'debugss' class
|
||||
* debug sub system
|
||||
*/
|
||||
static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
|
||||
{ .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
|
||||
{ .role = "dbg_clka", .clk = "dbg_clka_ck" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
|
||||
.name = "debugss",
|
||||
};
|
||||
|
||||
static struct omap_hwmod am33xx_debugss_hwmod = {
|
||||
.name = "debugss",
|
||||
.class = &am33xx_debugss_hwmod_class,
|
||||
.clkdm_name = "l3_aon_clkdm",
|
||||
.main_clk = "trace_clk_div_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.opt_clks = debugss_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
|
||||
};
|
||||
|
||||
static struct omap_hwmod am33xx_control_hwmod = {
|
||||
.name = "control",
|
||||
.class = &am33xx_control_hwmod_class,
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.flags = HWMOD_INIT_NO_IDLE,
|
||||
.main_clk = "dpll_core_m4_div2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Interfaces
|
||||
*/
|
||||
|
||||
/* l3 main -> emif */
|
||||
static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_emif_hwmod,
|
||||
.clk = "dpll_core_m4_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3 main -> l4 hs */
|
||||
static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_l4_hs_hwmod,
|
||||
.clk = "l3s_gclk",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* wkup m3 -> l4 wkup */
|
||||
static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
|
||||
.master = &am33xx_wkup_m3_hwmod,
|
||||
.slave = &am33xx_l4_wkup_hwmod,
|
||||
.clk = "dpll_core_m4_div2_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4 wkup -> wkup m3 */
|
||||
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
|
||||
.master = &am33xx_l4_wkup_hwmod,
|
||||
.slave = &am33xx_wkup_m3_hwmod,
|
||||
.clk = "dpll_core_m4_div2_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main -> debugss */
|
||||
static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
.slave = &am33xx_debugss_hwmod,
|
||||
.clk = "dpll_core_m4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l4 wkup -> smartreflex0 */
|
||||
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
|
||||
.master = &am33xx_l4_wkup_hwmod,
|
||||
.slave = &am33xx_smartreflex0_hwmod,
|
||||
.clk = "dpll_core_m4_div2_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l4 wkup -> smartreflex1 */
|
||||
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
|
||||
.master = &am33xx_l4_wkup_hwmod,
|
||||
.slave = &am33xx_smartreflex1_hwmod,
|
||||
.clk = "dpll_core_m4_div2_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l4 wkup -> control */
|
||||
static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
|
||||
.master = &am33xx_l4_wkup_hwmod,
|
||||
.slave = &am33xx_control_hwmod,
|
||||
.clk = "dpll_core_m4_div2_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&am33xx_l3_main__emif,
|
||||
&am33xx_mpu__l3_main,
|
||||
&am33xx_mpu__prcm,
|
||||
&am33xx_l3_s__l4_ls,
|
||||
&am33xx_l3_s__l4_wkup,
|
||||
&am33xx_l3_main__l4_hs,
|
||||
&am33xx_l3_main__l3_s,
|
||||
&am33xx_l3_main__l3_instr,
|
||||
&am33xx_l3_s__l3_main,
|
||||
&am33xx_wkup_m3__l4_wkup,
|
||||
&am33xx_l3_main__debugss,
|
||||
&am33xx_l4_wkup__wkup_m3,
|
||||
&am33xx_l4_wkup__control,
|
||||
&am33xx_l4_wkup__smartreflex0,
|
||||
&am33xx_l4_wkup__smartreflex1,
|
||||
&am33xx_l3_s__gpmc,
|
||||
&am33xx_l3_main__ocmc,
|
||||
NULL,
|
||||
};
|
||||
|
||||
int __init am33xx_hwmod_init(void)
|
||||
{
|
||||
omap_hwmod_am33xx_reg();
|
||||
omap_hwmod_init();
|
||||
return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
|
||||
}
|
||||
@@ -150,7 +150,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&am43xx_l4_wkup__control,
|
||||
&am43xx_l4_wkup__smartreflex0,
|
||||
&am43xx_l4_wkup__smartreflex1,
|
||||
&am33xx_l3_s__gpmc,
|
||||
&am33xx_l3_main__ocmc,
|
||||
NULL,
|
||||
};
|
||||
|
||||
@@ -94,6 +94,7 @@ static void __init hsmmc2_internal_input_clk(void)
|
||||
omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_HWMOD
|
||||
static struct iommu_platform_data omap3_iommu_pdata = {
|
||||
.reset_name = "mmu",
|
||||
.assert_reset = omap_device_assert_hardreset,
|
||||
@@ -106,6 +107,7 @@ static struct iommu_platform_data omap3_iommu_isp_pdata = {
|
||||
.device_enable = omap_device_enable,
|
||||
.device_idle = omap_device_idle,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int omap3_sbc_t3730_twl_callback(struct device *dev,
|
||||
unsigned gpio,
|
||||
@@ -272,7 +274,7 @@ static void __init omap3_pandora_legacy_init(void)
|
||||
}
|
||||
#endif /* CONFIG_ARCH_OMAP3 */
|
||||
|
||||
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
|
||||
#if defined(CONFIG_SOC_AM43XX)
|
||||
static struct wkup_m3_platform_data wkup_m3_data = {
|
||||
.reset_name = "wkup_m3",
|
||||
.assert_reset = omap_device_assert_hardreset,
|
||||
@@ -370,6 +372,7 @@ static void ti_sysc_clkdm_allow_idle(struct device *dev,
|
||||
clkdm_allow_idle(cookie->clkdm);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_HWMOD
|
||||
static int ti_sysc_enable_module(struct device *dev,
|
||||
const struct ti_sysc_cookie *cookie)
|
||||
{
|
||||
@@ -396,6 +399,7 @@ static int ti_sysc_shutdown_module(struct device *dev,
|
||||
|
||||
return omap_hwmod_shutdown(cookie->data);
|
||||
}
|
||||
#endif /* CONFIG_OMAP_HWMOD */
|
||||
|
||||
static bool ti_sysc_soc_type_gp(void)
|
||||
{
|
||||
@@ -410,10 +414,12 @@ static struct ti_sysc_platform_data ti_sysc_pdata = {
|
||||
.init_clockdomain = ti_sysc_clkdm_init,
|
||||
.clkdm_deny_idle = ti_sysc_clkdm_deny_idle,
|
||||
.clkdm_allow_idle = ti_sysc_clkdm_allow_idle,
|
||||
#ifdef CONFIG_OMAP_HWMOD
|
||||
.init_module = omap_hwmod_init_module,
|
||||
.enable_module = ti_sysc_enable_module,
|
||||
.idle_module = ti_sysc_idle_module,
|
||||
.shutdown_module = ti_sysc_shutdown_module,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct pcs_pdata pcs_pdata;
|
||||
@@ -501,10 +507,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
|
||||
OF_DEV_AUXDATA("ti,omap3-mcbsp", 0x49024000, "49024000.mcbsp", &mcbsp_pdata),
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_AM33XX
|
||||
OF_DEV_AUXDATA("ti,am3352-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
|
||||
&wkup_m3_data),
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_AM43XX
|
||||
OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
|
||||
&wkup_m3_data),
|
||||
|
||||
Reference in New Issue
Block a user