dt-bindings: crypto: Convert hisilicon,hip0{6,7}-sec to DT schema
Convert the HiSilicon HIP06/7 Security Accelerator binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/hisilicon,hip06-sec.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Hisilicon hip06/hip07 Security Accelerator
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maintainers:
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- Jonathan Cameron <Jonathan.Cameron@huawei.com>
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properties:
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compatible:
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enum:
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- hisilicon,hip06-sec
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- hisilicon,hip07-sec
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reg:
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items:
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- description: Registers for backend processing engines
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- description: Registers for common functionality
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- description: Registers for queue 0
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- description: Registers for queue 1
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- description: Registers for queue 2
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- description: Registers for queue 3
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- description: Registers for queue 4
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- description: Registers for queue 5
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- description: Registers for queue 6
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- description: Registers for queue 7
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- description: Registers for queue 8
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- description: Registers for queue 9
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- description: Registers for queue 10
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- description: Registers for queue 11
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- description: Registers for queue 12
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- description: Registers for queue 13
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- description: Registers for queue 14
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- description: Registers for queue 15
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interrupts:
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items:
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- description: SEC unit error queue interrupt
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- description: Completion interrupt for queue 0
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- description: Error interrupt for queue 0
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- description: Completion interrupt for queue 1
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- description: Error interrupt for queue 1
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- description: Completion interrupt for queue 2
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- description: Error interrupt for queue 2
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- description: Completion interrupt for queue 3
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- description: Error interrupt for queue 3
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- description: Completion interrupt for queue 4
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- description: Error interrupt for queue 4
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- description: Completion interrupt for queue 5
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- description: Error interrupt for queue 5
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- description: Completion interrupt for queue 6
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- description: Error interrupt for queue 6
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- description: Completion interrupt for queue 7
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- description: Error interrupt for queue 7
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- description: Completion interrupt for queue 8
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- description: Error interrupt for queue 8
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- description: Completion interrupt for queue 9
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- description: Error interrupt for queue 9
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- description: Completion interrupt for queue 10
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- description: Error interrupt for queue 10
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- description: Completion interrupt for queue 11
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- description: Error interrupt for queue 11
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- description: Completion interrupt for queue 12
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- description: Error interrupt for queue 12
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- description: Completion interrupt for queue 13
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- description: Error interrupt for queue 13
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- description: Completion interrupt for queue 14
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- description: Error interrupt for queue 14
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- description: Completion interrupt for queue 15
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- description: Error interrupt for queue 15
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dma-coherent: true
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iommus:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- dma-coherent
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additionalProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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crypto@400d2000000 {
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compatible = "hisilicon,hip07-sec";
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reg = <0x400 0xd0000000 0x0 0x10000
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0x400 0xd2000000 0x0 0x10000
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0x400 0xd2010000 0x0 0x10000
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0x400 0xd2020000 0x0 0x10000
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0x400 0xd2030000 0x0 0x10000
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0x400 0xd2040000 0x0 0x10000
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0x400 0xd2050000 0x0 0x10000
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0x400 0xd2060000 0x0 0x10000
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0x400 0xd2070000 0x0 0x10000
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0x400 0xd2080000 0x0 0x10000
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0x400 0xd2090000 0x0 0x10000
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0x400 0xd20a0000 0x0 0x10000
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0x400 0xd20b0000 0x0 0x10000
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0x400 0xd20c0000 0x0 0x10000
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0x400 0xd20d0000 0x0 0x10000
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0x400 0xd20e0000 0x0 0x10000
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0x400 0xd20f0000 0x0 0x10000
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0x400 0xd2100000 0x0 0x10000>;
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interrupts = <576 4>,
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<577 1>, <578 4>,
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<579 1>, <580 4>,
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<581 1>, <582 4>,
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<583 1>, <584 4>,
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<585 1>, <586 4>,
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<587 1>, <588 4>,
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<589 1>, <590 4>,
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<591 1>, <592 4>,
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<593 1>, <594 4>,
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<595 1>, <596 4>,
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<597 1>, <598 4>,
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<599 1>, <600 4>,
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<601 1>, <602 4>,
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<603 1>, <604 4>,
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<605 1>, <606 4>,
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<607 1>, <608 4>;
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dma-coherent;
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iommus = <&p1_smmu_alg_a 0x600>;
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};
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};
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@@ -1,67 +0,0 @@
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* Hisilicon hip07 Security Accelerator (SEC)
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Required properties:
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- compatible: Must contain one of
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- "hisilicon,hip06-sec"
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- "hisilicon,hip07-sec"
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- reg: Memory addresses and lengths of the memory regions through which
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this device is controlled.
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Region 0 has registers to control the backend processing engines.
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Region 1 has registers for functionality common to all queues.
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Regions 2-18 have registers for the 16 individual queues which are isolated
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both in hardware and within the driver.
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- interrupts: Interrupt specifiers.
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Refer to interrupt-controller/interrupts.txt for generic interrupt client node
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bindings.
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Interrupt 0 is for the SEC unit error queue.
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Interrupt 2N + 1 is the completion interrupt for queue N.
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Interrupt 2N + 2 is the error interrupt for queue N.
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- dma-coherent: The driver assumes coherent dma is possible.
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Optional properties:
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- iommus: The SEC units are behind smmu-v3 iommus.
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Refer to iommu/arm,smmu-v3.txt for more information.
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Example:
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p1_sec_a: crypto@400d2000000 {
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compatible = "hisilicon,hip07-sec";
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reg = <0x400 0xd0000000 0x0 0x10000
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0x400 0xd2000000 0x0 0x10000
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0x400 0xd2010000 0x0 0x10000
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0x400 0xd2020000 0x0 0x10000
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0x400 0xd2030000 0x0 0x10000
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0x400 0xd2040000 0x0 0x10000
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0x400 0xd2050000 0x0 0x10000
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0x400 0xd2060000 0x0 0x10000
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0x400 0xd2070000 0x0 0x10000
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0x400 0xd2080000 0x0 0x10000
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0x400 0xd2090000 0x0 0x10000
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0x400 0xd20a0000 0x0 0x10000
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0x400 0xd20b0000 0x0 0x10000
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0x400 0xd20c0000 0x0 0x10000
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0x400 0xd20d0000 0x0 0x10000
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0x400 0xd20e0000 0x0 0x10000
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0x400 0xd20f0000 0x0 0x10000
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0x400 0xd2100000 0x0 0x10000>;
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interrupt-parent = <&p1_mbigen_sec_a>;
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iommus = <&p1_smmu_alg_a 0x600>;
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dma-coherent;
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interrupts = <576 4>,
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<577 1>, <578 4>,
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<579 1>, <580 4>,
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<581 1>, <582 4>,
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<583 1>, <584 4>,
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<585 1>, <586 4>,
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<587 1>, <588 4>,
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<589 1>, <590 4>,
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<591 1>, <592 4>,
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<593 1>, <594 4>,
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<595 1>, <596 4>,
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<597 1>, <598 4>,
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<599 1>, <600 4>,
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<601 1>, <602 4>,
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<603 1>, <604 4>,
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<605 1>, <606 4>,
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<607 1>, <608 4>;
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};
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