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Merge b44f2fd879 ("Merge tag 'drm-next-2022-08-03' of git://anongit.freedesktop.org/drm/drm") into android-mainline

Browse Source 
Steps on the way to 6.0-rc1

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I26fe75543def53ba915195bd856bf5257e024387
This commit is contained in:
Greg Kroah-Hartman
2022-08-11 14:43:59 +02:00
parent cf914356cc b44f2fd879
commit 0148b24eab
1873 changed files with 575957 additions and 36613 deletions
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CREDITS
+4
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@@ -3495,6 +3495,10 @@ D: wd33c93 SCSI driver (linux-m68k)
S: San Jose, California
S: USA
N: Joonyoung Shim
E: y0922.shim@samsung.com
D: Samsung Exynos DRM drivers
N: Robert Siemer
E: Robert.Siemer@gmx.de
P: 2048/C99A4289 2F DC 17 2E 56 62 01 C8 3D F2 AC 09 F2 E5 DD EE
Documentation/admin-guide/media/vimc.dot
+4
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@@ -5,9 +5,13 @@ digraph board {
n00000001 [label="{{} | Sensor A\n/dev/v4l-subdev0 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green]
n00000001:port0 -> n00000005:port0 [style=bold]
n00000001:port0 -> n0000000b [style=bold]
n00000001 -> n00000002
n00000002 [label="{{} | Lens A\n/dev/v4l-subdev5 | {<port0>}}", shape=Mrecord, style=filled, fillcolor=green]
n00000003 [label="{{} | Sensor B\n/dev/v4l-subdev1 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green]
n00000003:port0 -> n00000008:port0 [style=bold]
n00000003:port0 -> n0000000f [style=bold]
n00000003 -> n00000004
n00000004 [label="{{} | Lens B\n/dev/v4l-subdev6 | {<port0>}}", shape=Mrecord, style=filled, fillcolor=green]
n00000005 [label="{{<port0> 0} | Debayer A\n/dev/v4l-subdev2 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
n00000005:port1 -> n00000015:port0
n00000008 [label="{{<port0> 0} | Debayer B\n/dev/v4l-subdev3 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
Documentation/admin-guide/media/vimc.rst
+19
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@@ -53,6 +53,25 @@ vimc-sensor:
* 1 Pad source
vimc-lens:
Ancillary lens for a sensor. Supports auto focus control. Linked to
a vimc-sensor using an ancillary link. The lens supports FOCUS_ABSOLUTE
control.
.. code-block:: bash
media-ctl -p
...
- entity 28: Lens A (0 pad, 0 link)
type V4L2 subdev subtype Lens flags 0
device node name /dev/v4l-subdev6
- entity 29: Lens B (0 pad, 0 link)
type V4L2 subdev subtype Lens flags 0
device node name /dev/v4l-subdev7
v4l2-ctl -d /dev/v4l-subdev7 -C focus_absolute
focus_absolute: 0
vimc-debayer:
Transforms images in bayer format into a non-bayer format.
Exposes:
Documentation/admin-guide/media/vivid.rst
+14
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@@ -714,6 +714,20 @@ The Test Pattern Controls are all specific to video capture.
does the same for the EAV (End of Active Video) code.
- Insert Video Guard Band
adds 4 columns of pixels with the HDMI Video Guard Band code at the
left hand side of the image. This only works with 3 or 4 byte RGB pixel
formats. The RGB pixel value 0xab/0x55/0xab turns out to be equivalent
to the HDMI Video Guard Band code that precedes each active video line
(see section 5.2.2.1 in the HDMI 1.3 Specification). To test if a video
receiver has correct HDMI Video Guard Band processing, enable this
control and then move the image to the left hand side of the screen.
That will result in video lines that start with multiple pixels that
have the same value as the Video Guard Band that precedes them.
Receivers that will just keep skipping Video Guard Band values will
now fail and either loose sync or these video lines will shift.
Capture Feature Selection Controls
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
+18 -1
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@@ -94,7 +94,22 @@ properties:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Video port for MIPI DSI input.
MIPI DSI/DPI input.
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
type: object
additionalProperties: false
properties:
remote-endpoint: true
bus-type:
enum: [7]
default: 1
data-lanes: true
port@1:
$ref: /schemas/graph.yaml#/properties/port
@@ -143,6 +158,8 @@ examples:
reg = <0>;
anx7625_in: endpoint {
remote-endpoint = <&mipi_dsi>;
bus-type = <7>;
data-lanes = <0 1 2 3>;
};
};
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
+173
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@@ -0,0 +1,173 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qm/qxp LVDS Display Bridge
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
The CSR module, as a system controller, contains the LDB's configuration
registers.
For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
format and can map the input to VESA or JEIDA standards. The two channels
cannot be used simultaneously, that is to say, the user should pick one of
them to use. Two LDB channels from two LDB instances can work together in
LDB split mode to support a dual link LVDS display. The channel indexes
have to be different. Channel0 outputs odd pixels and channel1 outputs
even pixels.
For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
input color format. The two channels can be used simultaneously, either
in dual mode or split mode. In dual mode, the two channels output identical
data. In split mode, channel0 outputs odd pixels and channel1 outputs even
pixels.
A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in
i.MX6qdl/sx SoCs, i.e., it is essentially based on them. To keep the naming
consistency, this binding calls it LDB.
properties:
compatible:
enum:
- fsl,imx8qm-ldb
- fsl,imx8qxp-ldb
"#address-cells":
const: 1
"#size-cells":
const: 0
clocks:
items:
- description: pixel clock
- description: bypass clock
clock-names:
items:
- const: pixel
- const: bypass
power-domains:
maxItems: 1
fsl,companion-ldb:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
A phandle which points to companion LDB which is used in LDB split mode.
patternProperties:
"^channel@[0-1]$":
type: object
description: Represents a channel of LDB.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
reg:
description: The channel index.
enum: [ 0, 1 ]
phys:
description: A phandle to the phy module representing the LVDS PHY.
maxItems: 1
phy-names:
const: lvds_phy
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input port of the channel.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output port of the channel.
required:
- "#address-cells"
- "#size-cells"
- reg
- phys
- phy-names
additionalProperties: false
required:
- compatible
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
- power-domains
- channel@0
- channel@1
allOf:
- if:
properties:
compatible:
contains:
const: fsl,imx8qm-ldb
then:
properties:
fsl,companion-ldb: false
additionalProperties: false
examples:
- |
#include <dt-bindings/firmware/imx/rsrc.h>
ldb {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8qxp-ldb";
clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
clock-names = "pixel", "bypass";
power-domains = <&pd IMX_SC_R_LVDS_0>;
channel@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phys = <&mipi_lvds_0_phy>;
phy-names = "lvds_phy";
port@0 {
reg = <0>;
mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
};
};
};
channel@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phys = <&mipi_lvds_0_phy>;
phy-names = "lvds_phy";
port@0 {
reg = <0>;
mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
};
};
};
};
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
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@@ -0,0 +1,144 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qm/qxp Pixel Combiner
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
single display controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
either one screen, two screens, or virtual screens. The pixel combiner is
also responsible for generating some of the control signals for the pixel link
output channel.
properties:
compatible:
enum:
- fsl,imx8qm-pixel-combiner
- fsl,imx8qxp-pixel-combiner
"#address-cells":
const: 1
"#size-cells":
const: 0
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: apb
power-domains:
maxItems: 1
patternProperties:
"^channel@[0-1]$":
type: object
description: Represents a display stream of pixel combiner.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
reg:
description: The display stream index.
enum: [ 0, 1 ]
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input endpoint of the display stream.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output endpoint of the display stream.
required:
- "#address-cells"
- "#size-cells"
- reg
- port@0
- port@1
additionalProperties: false
required:
- compatible
- "#address-cells"
- "#size-cells"
- reg
- clocks
- clock-names
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
pixel-combiner@56020000 {
compatible = "fsl,imx8qxp-pixel-combiner";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x56020000 0x10000>;
clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
clock-names = "apb";
power-domains = <&pd IMX_SC_R_DC_0>;
channel@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
port@0 {
reg = <0>;
dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;
};
};
port@1 {
reg = <1>;
dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;
};
};
};
channel@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
port@0 {
reg = <0>;
dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;
};
};
port@1 {
reg = <1>;
dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;
};
};
};
};
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
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@@ -0,0 +1,144 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qm/qxp Display Pixel Link
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
asynchronous linkage between pixel sources(display controller or
camera module) and pixel consumers(imaging or displays).
It consists of two distinct functions, a pixel transfer function and a
control interface. Multiple pixel channels can exist per one control channel.
This binding documentation is only for pixel links whose pixel sources are
display controllers.
The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
firmware.
properties:
compatible:
enum:
- fsl,imx8qm-dc-pixel-link
- fsl,imx8qxp-dc-pixel-link
fsl,dc-id:
$ref: /schemas/types.yaml#/definitions/uint8
description: |
u8 value representing the display controller index that the pixel link
connects to.
fsl,dc-stream-id:
$ref: /schemas/types.yaml#/definitions/uint8
description: |
u8 value representing the display controller stream index that the pixel
link connects to.
enum: [0, 1]
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: The pixel link input port node from upstream video source.
patternProperties:
"^port@[1-4]$":
$ref: /schemas/graph.yaml#/properties/port
description: The pixel link output port node to downstream bridge.
required:
- port@0
- port@1
- port@2
- port@3
- port@4
allOf:
- if:
properties:
compatible:
contains:
const: fsl,imx8qxp-dc-pixel-link
then:
properties:
fsl,dc-id:
const: 0
- if:
properties:
compatible:
contains:
const: fsl,imx8qm-dc-pixel-link
then:
properties:
fsl,dc-id:
enum: [0, 1]
required:
- compatible
- fsl,dc-id
- fsl,dc-stream-id
- ports
additionalProperties: false
examples:
- |
dc0-pixel-link0 {
compatible = "fsl,imx8qxp-dc-pixel-link";
fsl,dc-id = /bits/ 8 <0>;
fsl,dc-stream-id = /bits/ 8 <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* from dc0 pixel combiner channel0 */
port@0 {
reg = <0>;
dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
};
};
/* to PXL2DPIs in MIPI/LVDS combo subsystems */
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
};
dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
};
};
/* unused */
port@2 {
reg = <2>;
};
/* unused */
port@3 {
reg = <3>;
};
/* to imaging subsystem */
port@4 {
reg = <4>;
};
};
};
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
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@@ -0,0 +1,108 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
interfaces the pixel link 36-bit data output and the DSI controller’s
MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
used in LVDS mode, to remap the pixel color codings between those modules.
This module is purely combinatorial.
The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
The CSR module, as a system controller, contains the PXL2DPI's configuration
register.
properties:
compatible:
const: fsl,imx8qxp-pxl2dpi
fsl,sc-resource:
$ref: /schemas/types.yaml#/definitions/uint32
description: The SCU resource ID associated with this PXL2DPI instance.
power-domains:
maxItems: 1
fsl,companion-pxl2dpi:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
A phandle which points to companion PXL2DPI which is used by downstream
LVDS Display Bridge(LDB) in split mode.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: The PXL2DPI input port node from pixel link.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: The PXL2DPI output port node to downstream bridge.
required:
- port@0
- port@1
required:
- compatible
- fsl,sc-resource
- power-domains
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/firmware/imx/rsrc.h>
pxl2dpi {
compatible = "fsl,imx8qxp-pxl2dpi";
fsl,sc-resource = <IMX_SC_R_MIPI_0>;
power-domains = <&pd IMX_SC_R_MIPI_0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
reg = <0>;
remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
};
mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
reg = <1>;
remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
};
mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
};
};
};
};
Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
+15 -1
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@@ -24,6 +24,15 @@ properties:
clock-names:
const: ldb
reg:
minItems: 2
maxItems: 2
reg-names:
items:
- const: ldb
- const: lvds
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -56,10 +65,15 @@ examples:
#include <dt-bindings/clock/imx8mp-clock.h>
blk-ctrl {
bridge {
#address-cells = <1>;
#size-cells = <1>;
bridge@5c {
compatible = "fsl,imx8mp-ldb";
clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
clock-names = "ldb";
reg = <0x5c 0x4>, <0x128 0x4>;
reg-names = "ldb", "lvds";
ports {
#address-cells = <1>;
Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
-1
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@@ -55,7 +55,6 @@ examples:
compatible = "ingenic,jz4780-dw-hdmi";
reg = <0x10180000 0x8000>;
reg-io-width = <4>;
ddc-i2c-bus = <&i2c4>;
interrupt-parent = <&intc>;
interrupts = <3>;
clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml
+117
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@@ -0,0 +1,117 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ti,dlpc3433.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI DLPC3433 MIPI DSI to DMD bridge
maintainers:
- Jagan Teki <jagan@amarulasolutions.com>
- Christopher Vollo <chris@renewoutreach.org>
description: |
TI DLPC3433 is a MIPI DSI based display controller bridge
for processing high resolution DMD based projectors.
It has a flexible configuration of MIPI DSI and DPI signal
input that produces a DMD output in RGB565, RGB666, RGB888
formats.
It supports upto 720p resolution with 60 and 120 Hz refresh
rates.
properties:
compatible:
const: ti,dlpc3433
reg:
enum:
- 0x1b
- 0x1d
enable-gpios:
description: PROJ_ON pin, chip powers up PROJ_ON is high.
vcc_intf-supply:
description: A 1.8V/3.3V supply that power the Host I/O.
vcc_flsh-supply:
description: A 1.8V/3.3V supply that power the Flash I/O.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Video port for MIPI DSI input.
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
description: array of physical DSI data lane indexes.
minItems: 1
items:
- const: 1
- const: 2
- const: 3
- const: 4
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Video port for DMD output.
required:
- port@0
- port@1
required:
- compatible
- reg
- enable-gpios
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c1 {
#address-cells = <1>;
#size-cells = <0>;
bridge@1b {
compatible = "ti,dlpc3433";
reg = <0x1b>;
enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in_dsi: endpoint {
remote-endpoint = <&dsi_out_bridge>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
bridge_out_panel: endpoint {
remote-endpoint = <&panel_out_bridge>;
};
};
};
};
};
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
+1
View File
@@ -20,6 +20,7 @@ properties:
- fsl,imx23-lcdif
- fsl,imx28-lcdif
- fsl,imx6sx-lcdif
- fsl,imx8mp-lcdif
- items:
- enum:
- fsl,imx6sl-lcdif
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+6 -5
View File
@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: mediatek DPI Controller Device Tree Bindings
title: MediaTek DPI and DP_INTF Controller
maintainers:
- CK Hu <ck.hu@mediatek.com>
- Jitao shi <jitao.shi@mediatek.com>
description: |
The Mediatek DPI function block is a sink of the display subsystem and
provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
output bus.
The MediaTek DPI and DP_INTF function blocks are a sink of the display
subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
parallel output bus.
properties:
compatible:
@@ -24,6 +24,7 @@ properties:
- mediatek,mt8183-dpi
- mediatek,mt8186-dpi
- mediatek,mt8192-dpi
- mediatek,mt8195-dp-intf
reg:
maxItems: 1
@@ -55,7 +56,7 @@ properties:
$ref: /schemas/graph.yaml#/properties/port
description:
Output port node. This port should be connected to the input port of an
attached HDMI or LVDS encoder chip.
attached HDMI, LVDS or DisplayPort encoder chip.
required:
- compatible
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
-62
View File
@@ -1,62 +0,0 @@
Mediatek DSI Device
===================
The Mediatek DSI function block is a sink of the display subsystem and can
drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- clock-names: must contain "engine", "digital", and "hs"
- phys: phandle link to the MIPI D-PHY controller.
- phy-names: must contain "dphy"
- port: Output port node with endpoint definitions as described in
Documentation/devicetree/bindings/graph.txt. This port should be connected
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
Optional properties:
- resets: list of phandle + reset specifier pair, as described in [1].
[1] Documentation/devicetree/bindings/reset/reset.txt
MIPI TX Configuration Module
============================
See phy/mediatek,dsi-phy.yaml
Example:
mipi_tx0: mipi-dphy@10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
clocks = <&clk26m>;
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
drive-strength-microamp = <4600>;
nvmem-cells= <&mipi_tx_calibration>;
nvmem-cell-names = "calibration-data";
};
dsi0: dsi@1401b000 {
compatible = "mediatek,mt8173-dsi";
reg = <0 0x1401b000 0 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
port {
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
+116
View File
@@ -0,0 +1,116 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek DSI Controller Device Tree Bindings
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
- Jitao Shi <jitao.shi@mediatek.com>
- Xinlei Lee <xinlei.lee@mediatek.com>
description: |
The MediaTek DSI function block is a sink of the display subsystem and can
drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
channel output.
allOf:
- $ref: /schemas/display/dsi-controller.yaml#
properties:
compatible:
enum:
- mediatek,mt2701-dsi
- mediatek,mt7623-dsi
- mediatek,mt8167-dsi
- mediatek,mt8173-dsi
- mediatek,mt8183-dsi
- mediatek,mt8186-dsi
reg:
maxItems: 1
interrupts:
maxItems: 1
power-domains:
maxItems: 1
clocks:
items:
- description: Engine Clock
- description: Digital Clock
- description: HS Clock
clock-names:
items:
- const: engine
- const: digital
- const: hs
resets:
maxItems: 1
phys:
maxItems: 1
phy-names:
items:
- const: dphy
port:
$ref: /schemas/graph.yaml#/properties/port
description:
Output port node. This port should be connected to the input
port of an attached DSI panel or DSI-to-eDP encoder chip.
required:
- compatible
- reg
- interrupts
- power-domains
- clocks
- clock-names
- phys
- phy-names
- port
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt8183-resets.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
dsi0: dsi@14014000 {
compatible = "mediatek,mt8183-dsi";
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DSI0_MM>,
<&mmsys CLK_MM_DSI0_IF>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
port {
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
...
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
+88
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@@ -0,0 +1,88 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MDP RDMA
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
description:
The MediaTek MDP RDMA stands for Read Direct Memory Access.
It provides real time data to the back-end panel driver, such as DSI,
DPI and DP_INTF.
It contains one line buffer to store the sufficient pixel data.
RDMA device node must be siblings to the central MMSYS_CONFIG node.
For a description of the MMSYS_CONFIG binding, see
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
properties:
compatible:
const: mediatek,mt8195-vdo1-rdma
reg:
maxItems: 1
interrupts:
maxItems: 1
power-domains:
maxItems: 1
clocks:
items:
- description: RDMA Clock
iommus:
maxItems: 1
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
such as gce node, subsys id, offset and register size. The subsys id that is
mapping to the register of display function blocks is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
maxItems: 1
required:
- compatible
- reg
- power-domains
- clocks
- iommus
- mediatek,gce-client-reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
rdma@1c104000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c104000 0 0x1000>;
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
};
};
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+7 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: MSM Display Port Controller
maintainers:
- Kuogee Hsieh <khsieh@codeaurora.org>
- Kuogee Hsieh <quic_khsieh@quicinc.com>
description: |
Device tree bindings for DisplayPort host controller for MSM targets
@@ -76,6 +76,9 @@ properties:
"#sound-dai-cells":
const: 0
vdda-0p9-supply: true
vdda-1p2-supply: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
@@ -137,6 +140,9 @@ examples:
power-domains = <&rpmhpd SC7180_CX>;
vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
Documentation/devicetree/bindings/display/msm/hdmi.txt
-99
View File
@@ -1,99 +0,0 @@
Qualcomm adreno/snapdragon hdmi output
Required properties:
- compatible: one of the following
* "qcom,hdmi-tx-8996"
* "qcom,hdmi-tx-8994"
* "qcom,hdmi-tx-8084"
* "qcom,hdmi-tx-8974"
* "qcom,hdmi-tx-8660"
* "qcom,hdmi-tx-8960"
- reg: Physical base address and length of the controller's registers
- reg-names: "core_physical"
- interrupts: The interrupt signal from the hdmi block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
See ../clocks/clock-bindings.txt for details.
- core-vdda-supply: phandle to supply regulator
- hdmi-mux-supply: phandle to mux regulator
- phys: the phandle for the HDMI PHY device
- phy-names: the name of the corresponding PHY device
Optional properties:
- hpd-gpios: hpd pin
- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin
- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin
- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin
- power-domains: reference to the power domain(s), if available.
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)
- pinctrl-1: the "sleep" pinctrl state
HDMI PHY:
Required properties:
- compatible: Could be the following
* "qcom,hdmi-phy-8660"
* "qcom,hdmi-phy-8960"
* "qcom,hdmi-phy-8974"
* "qcom,hdmi-phy-8084"
* "qcom,hdmi-phy-8996"
- #phy-cells: Number of cells in a PHY specifier; Should be 0.
- reg: Physical base address and length of the registers of the PHY sub blocks.
- reg-names: The names of register regions. The following regions are required:
* "hdmi_phy"
* "hdmi_pll"
For HDMI PHY on msm8996, these additional register regions are required:
* "hdmi_tx_l0"
* "hdmi_tx_l1"
* "hdmi_tx_l3"
* "hdmi_tx_l4"
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- core-vdda-supply: phandle to vdda regulator device node
Example:
/ {
...
hdmi: hdmi@4a00000 {
compatible = "qcom,hdmi-tx-8960";
reg-names = "core_physical";
reg = <0x04a00000 0x2f0>;
interrupts = <GIC_SPI 79 0>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names =
"core",
"master_iface",
"slave_iface";
clocks =
<&mmcc HDMI_APP_CLK>,
<&mmcc HDMI_M_AHB_CLK>,
<&mmcc HDMI_S_AHB_CLK>;
qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
core-vdda-supply = <&pm8921_hdmi_mvs>;
hdmi-mux-supply = <&ext_3p3v>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
phys = <&hdmi_phy>;
phy-names = "hdmi_phy";
};
hdmi_phy: phy@4a00400 {
compatible = "qcom,hdmi-phy-8960";
reg-names = "hdmi_phy",
"hdmi_pll";
reg = <0x4a00400 0x60>,
<0x4a00500 0x100>;
#phy-cells = <0>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names = "slave_iface";
clocks = <&mmcc HDMI_S_AHB_CLK>;
core-vdda-supply = <&pm8921_hdmi_mvs>;
};
};
Documentation/devicetree/bindings/display/msm/hdmi.yaml
+232
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@@ -0,0 +1,232 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Adreno/Snapdragon HDMI output
maintainers:
- Rob Clark <robdclark@gmail.com>
properties:
compatible:
enum:
- qcom,hdmi-tx-8084
- qcom,hdmi-tx-8660
- qcom,hdmi-tx-8960
- qcom,hdmi-tx-8974
- qcom,hdmi-tx-8994
- qcom,hdmi-tx-8996
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
reg:
minItems: 1
maxItems: 3
reg-names:
minItems: 1
items:
- const: core_physical
- const: qfprom_physical
- const: hdcp_physical
interrupts:
maxItems: 1
phys:
maxItems: 1
phy-names:
enum:
- hdmi_phy
- hdmi-phy
deprecated: true
core-vdda-supply:
description: phandle to VDDA supply regulator
hdmi-mux-supply:
description: phandle to mux regulator
deprecated: true
core-vcc-supply:
description: phandle to VCC supply regulator
hpd-gpios:
maxItems: 1
description: hpd pin
qcom,hdmi-tx-mux-en-gpios:
maxItems: 1
deprecated: true
description: HDMI mux enable pin
qcom,hdmi-tx-mux-sel-gpios:
maxItems: 1
deprecated: true
description: HDMI mux select pin
qcom,hdmi-tx-mux-lpm-gpios:
maxItems: 1
deprecated: true
description: HDMI mux lpm pin
'#sound-dai-cells':
const: 1
ports:
type: object
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
description: |
Input endpoints of the controller.
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
description: |
Output endpoints of the controller.
required:
- port@0
required:
- compatible
- clocks
- clock-names
- reg
- reg-names
- interrupts
- phys
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,hdmi-tx-8960
- qcom,hdmi-tx-8660
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: core
- const: master_iface
- const: slave_iface
core-vcc-supplies: false
- if:
properties:
compatible:
contains:
enum:
- qcom,hdmi-tx-8974
- qcom,hdmi-tx-8084
- qcom,hdmi-tx-8994
- qcom,hdmi-tx-8996
then:
properties:
clocks:
minItems: 5
clock-names:
items:
- const: mdp_core
- const: iface
- const: core
- const: alt_iface
- const: extp
hdmi-mux-supplies: false
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
hdmi: hdmi@4a00000 {
compatible = "qcom,hdmi-tx-8960";
reg-names = "core_physical";
reg = <0x04a00000 0x2f0>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core",
"master_iface",
"slave_iface";
clocks = <&clk 61>,
<&clk 72>,
<&clk 98>;
hpd-gpios = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
core-vdda-supply = <&pm8921_hdmi_mvs>;
hdmi-mux-supply = <&ext_3p3v>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
phys = <&hdmi_phy>;
};
- |
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
hdmi@9a0000 {
compatible = "qcom,hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
<0x00070000 0x6158>,
<0x009e0000 0xfff>;
reg-names = "core_physical",
"qfprom_physical",
"hdcp_physical";
interrupt-parent = <&mdss>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_HDMI_CLK>,
<&mmcc MDSS_HDMI_AHB_CLK>,
<&mmcc MDSS_EXTPCLK_CLK>;
clock-names = "mdp_core",
"iface",
"core",
"alt_iface",
"extp";
phys = <&hdmi_phy>;
#sound-dai-cells = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
core-vdda-supply = <&vreg_l12a_1p8>;
core-vcc-supply = <&vreg_s4a_1p8>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&mdp5_intf3_out>;
};
};
};
};
...
Documentation/devicetree/bindings/display/panel/ebbg,ft8719.yaml
+74
View File
@@ -0,0 +1,74 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/ebbg,ft8719.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: EBBG FT8719 MIPI-DSI LCD panel
maintainers:
- Joel Selvaraj <jo@jsfamily.in>
description: |
The FT8719 panel from EBBG is a FHD+ LCD display panel with a resolution
of 1080x2246. It is a video mode DSI panel. The backlight is managed
through the QCOM WLED driver.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: ebbg,ft8719
reg:
maxItems: 1
description: DSI virtual channel of the peripheral
vddio-supply:
description: power IC supply regulator
vddpos-supply:
description: positive boost supply regulator
vddneg-supply:
description: negative boost supply regulator
required:
- compatible
- reg
- vddio-supply
- vddpos-supply
- vddneg-supply
- reset-gpios
- port
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "ebbg,ft8719";
reg = <0>;
vddio-supply = <&vreg_l14a_1p88>;
vddpos-supply = <&lab>;
vddneg-supply = <&ibb>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
backlight = <&pmi8998_wled>;
port {
ebbg_ft8719_in_0: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml
-1
View File
@@ -35,7 +35,6 @@ required:
- reg
- avdd-supply
- dvdd-supply
- reset-gpios
additionalProperties: false
Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
+2
View File
@@ -46,6 +46,7 @@ properties:
reg: true
port: true
backlight: true
required:
- compatible
@@ -73,6 +74,7 @@ examples:
vddpos-supply = <&lab>;
vddneg-supply = <&ibb>;
backlight = <&pmi8998_wled>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
port {
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
+8
View File
@@ -35,6 +35,8 @@ properties:
- ampire,am-480272h3tmqw-t01h
# Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel
- ampire,am800480r3tmqwa1h
# Ampire AM-800600P5TMQW-TB8H 8.0" SVGA TFT LCD panel
- ampire,am800600p5tmqw-tb8h
# AU Optronics Corporation 10.1" WSVGA TFT LCD panel
- auo,b101aw03
# AU Optronics Corporation 10.1" WSVGA TFT LCD panel
@@ -107,6 +109,8 @@ properties:
- chunghwa,claa101wb03
# DataImage, Inc. 4.3" WQVGA (480x272) TFT LCD panel with 24-bit parallel interface.
- dataimage,fg040346dsswbg04
# DataImage, Inc. 10.1" WXGA (1280×800) TFT LCD panel
- dataimage,fg1001l0dsswmg01
# DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface.
- dataimage,scf0700c48ggu18
# DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel
@@ -137,6 +141,8 @@ properties:
# Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
- edt,etm0700g0dh6
- edt,etm0700g0edh6
# Emerging Display Technology Corp. LVDS WSVGA TFT Display with capacitive touch
- edt,etml0700y5dha
# Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with
# capacitive touch
- edt,etmv570g2dhu
@@ -158,6 +164,8 @@ properties:
- hannstar,hsd070pww1
# HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel
- hannstar,hsd100pxn1
# HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel
- hannstar,hsd101pww2
# Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel
- hit,tx23d38vm0caa
# InfoVision Optoelectronics M133NWF4 R0 13.3" FHD (1920x1080) TFT LCD panel
Documentation/devicetree/bindings/display/panel/sharp,lq101r1sx01.yaml
+6 -1
View File
@@ -30,7 +30,12 @@ allOf:
properties:
compatible:
const: sharp,lq101r1sx01
oneOf:
- items:
- const: sharp,lq101r1sx03
- const: sharp,lq101r1sx01
- items:
- const: sharp,lq101r1sx01
reg: true
power-supply: true
Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml
-1
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@@ -8,7 +8,6 @@ title: Samsung Exynos SoC HDMI DDC
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi.yaml
-1
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@@ -8,7 +8,6 @@ title: Samsung Exynos SoC HDMI
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
Documentation/devicetree/bindings/display/samsung/samsung,exynos-mixer.yaml
-1
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@@ -8,7 +8,6 @@ title: Samsung Exynos SoC Mixer
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-decon.yaml
-1
View File
@@ -8,7 +8,6 @@ title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-mic.yaml
-1
View File
@@ -8,7 +8,6 @@ title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml
-1
View File
@@ -8,7 +8,6 @@ title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml
-1
View File
@@ -8,7 +8,6 @@ title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
-41
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@@ -1,41 +0,0 @@
NVIDIA Tegra MIPI pad calibration controller
Required properties:
- compatible: "nvidia,tegra<chip>-mipi"
- reg: Physical base address and length of the controller's registers.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- mipi-cal
- #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
that need to be calibrated for a given device.
User nodes need to contain an nvidia,mipi-calibrate property that has a
phandle to refer to the calibration controller node and a bitmask of the pads
that need to be calibrated.
Example:
mipi: mipi@700e3000 {
compatible = "nvidia,tegra114-mipi";
reg = <0x700e3000 0x100>;
clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
clock-names = "mipi-cal";
#nvidia,mipi-calibrate-cells = <1>;
};
...
host1x@50000000 {
...
dsi@54300000 {
...
nvidia,mipi-calibrate = <&mipi 0x060>;
...
};
...
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
+74
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@@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra MIPI pad calibration controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^mipi@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra114-mipi
- nvidia,tegra210-mipi
- nvidia,tegra186-mipi
reg:
maxItems: 1
clocks:
items:
- description: module clock
clock-names:
items:
- const: mipi-cal
power-domains:
maxItems: 1
"#nvidia,mipi-calibrate-cells":
description: The number of cells in a MIPI calibration specifier.
Should be 1. The single cell specifies a bitmask of the pads that
need to be calibrated for a given device.
$ref: "/schemas/types.yaml#/definitions/uint32"
const: 1
additionalProperties: false
required:
- compatible
- reg
- clocks
- "#nvidia,mipi-calibrate-cells"
examples:
- |
#include <dt-bindings/clock/tegra114-car.h>
mipi@700e3000 {
compatible = "nvidia,tegra114-mipi";
reg = <0x700e3000 0x100>;
clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
clock-names = "mipi-cal";
#nvidia,mipi-calibrate-cells = <1>;
};
dsia: dsi@54300000 {
compatible = "nvidia,tegra114-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA114_CLK_DSIA>,
<&tegra_car TEGRA114_CLK_DSIALP>,
<&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
clock-names = "dsi", "lp", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
+152
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@@ -0,0 +1,152 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra DisplayPort AUX Interface
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
pins which can be assigned to either the DPAUX channel or to an I2C
controller.
When configured for DisplayPort AUX operation, the DPAUX controller
can also be used to communicate with a DisplayPort device using the
AUX channel.
properties:
$nodename:
pattern: "^dpaux@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra124-dpaux
- nvidia,tegra210-dpaux
- nvidia,tegra186-dpaux
- nvidia,tegra194-dpaux
- items:
- const: nvidia,tegra132-dpaux
- const: nvidia,tegra124-dpaux
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: clock input for the DPAUX hardware
- description: reference clock
clock-names:
items:
- const: dpaux
- const: parent
resets:
items:
- description: module reset
reset-names:
items:
- const: dpaux
power-domains:
maxItems: 1
i2c-bus:
description: Subnode where I2C slave devices are listed. This
subnode must be always present. If there are no I2C slave
devices, an empty node should be added. See ../../i2c/i2c.yaml
for more information.
type: object
aux-bus:
$ref: /schemas/display/dp-aux-bus.yaml#
vdd-supply:
description: phandle of a supply that powers the DisplayPort
link
patternProperties:
"^pinmux-[a-z0-9]+$":
description:
Since only three configurations are possible, only three child
nodes are needed to describe the pin mux'ing options for the
DPAUX pads. Furthermore, given that the pad functions are only
applicable to a single set of pads, the child nodes only need
to describe the pad group the functions are being applied to
rather than the individual pads.
type: object
properties:
groups:
const: dpaux-io
function:
enum:
- aux
- i2c
- off
additionalProperties: false
required:
- groups
- function
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
dpaux: dpaux@545c0000 {
compatible = "nvidia,tegra210-dpaux";
reg = <0x545c0000 0x00040000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
<&tegra_car TEGRA210_CLK_PLL_DP>;
clock-names = "dpaux", "parent";
resets = <&tegra_car 181>;
reset-names = "dpaux";
power-domains = <&pd_sor>;
status = "disabled";
state_dpaux_aux: pinmux-aux {
groups = "dpaux-io";
function = "aux";
};
state_dpaux_i2c: pinmux-i2c {
groups = "dpaux-io";
function = "i2c";
};
state_dpaux_off: pinmux-off {
groups = "dpaux-io";
function = "off";
};
i2c-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
+197
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@@ -0,0 +1,197 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra SOR Output Encoder
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
and DP outputs.
properties:
$nodename:
pattern: "^sor@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra124-sor
- nvidia,tegra210-sor
- nvidia,tegra210-sor1
- nvidia,tegra186-sor
- nvidia,tegra186-sor1
- nvidia,tegra194-sor
- items:
- const: nvidia,tegra132-sor
- const: nvidia,tegra124-sor
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 5
maxItems: 6
clock-names:
minItems: 5
maxItems: 6
resets:
items:
- description: module reset
reset-names:
items:
- const: sor
power-domains:
maxItems: 1
avdd-io-hdmi-dp-supply:
description: I/O supply for HDMI/DP
vdd-hdmi-dp-pll-supply:
description: PLL supply for HDMI/DP
hdmi-supply:
description: +5.0V HDMI connector supply, required for HDMI
# Tegra186 and later
nvidia,interface:
description: index of the SOR interface
$ref: "/schemas/types.yaml#/definitions/uint32"
nvidia,ddc-i2c-bus:
description: phandle of an I2C controller used for DDC EDID
probing
$ref: "/schemas/types.yaml#/definitions/phandle"
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
maxItems: 1
nvidia,edid:
description: supplies a binary EDID blob
$ref: "/schemas/types.yaml#/definitions/uint8-array"
nvidia,panel:
description: phandle of a display panel, required for eDP
$ref: "/schemas/types.yaml#/definitions/phandle"
nvidia,xbar-cfg:
description: 5 cells containing the crossbar configuration.
Each lane of the SOR, identified by the cell's index, is
mapped via the crossbar to the pad specified by the cell's
value.
$ref: "/schemas/types.yaml#/definitions/uint32-array"
# optional when driving an eDP output
nvidia,dpaux:
description: phandle to a DispayPort AUX interface
$ref: "/schemas/types.yaml#/definitions/phandle"
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra186-sor
- nvidia,tegra194-sor
then:
properties:
clocks:
items:
- description: clock input for the SOR hardware
- description: SOR output clock
- description: input for the pixel clock
- description: reference clock for the SOR clock
- description: safe reference clock for the SOR clock
during power up
- description: SOR pad output clock
clock-names:
items:
- const: sor
- enum:
- source # deprecated
- out
- const: parent
- const: dp
- const: safe
- const: pad
else:
properties:
clocks:
items:
- description: clock input for the SOR hardware
- description: SOR output clock
- description: input for the pixel clock
- description: reference clock for the SOR clock
- description: safe reference clock for the SOR clock
during power up
clock-names:
items:
- const: sor
- enum:
- source # deprecated
- out
- const: parent
- const: dp
- const: safe
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- avdd-io-hdmi-dp-supply
- vdd-hdmi-dp-pll-supply
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
sor0: sor@54540000 {
compatible = "nvidia,tegra210-sor";
reg = <0x54540000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR0_OUT>,
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_DP>,
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
clock-names = "sor", "out", "parent", "dp", "safe";
resets = <&tegra_car 182>;
reset-names = "sor";
pinctrl-0 = <&state_dpaux_aux>;
pinctrl-1 = <&state_dpaux_i2c>;
pinctrl-2 = <&state_dpaux_off>;
pinctrl-names = "aux", "i2c", "off";
power-domains = <&pd_sor>;
avdd-io-hdmi-dp-supply = <&avdd_1v05>;
vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
hdmi-supply = <&vdd_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>;
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
+72
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@@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Video Image Composer
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^vic@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra124-vic
- nvidia,tegra210-vic
- nvidia,tegra186-vic
- nvidia,tegra194-vic
- nvidia,tegra234-vic
- items:
- const: nvidia,tegra132-vic
- const: nvidia,tegra124-vic
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: clock input for the VIC hardware
clock-names:
items:
- const: vic
resets:
items:
- description: module reset
reset-names:
items:
- const: vic
power-domains:
maxItems: 1
iommus:
maxItems: 1
interconnects:
description: Description of the interconnect paths for the VIC;
see ../interconnect/interconnect.txt for details.
items:
- description: memory read client for VIC
- description: memory write client for VIC
interconnect-names:
items:
- const: dma-mem # read
- const: write
dma-coherent: true
additionalProperties: false
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
+85
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@@ -0,0 +1,85 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 (and later) Display Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^display@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra186-dc
- nvidia,tegra194-dc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: display controller pixel clock
clock-names:
items:
- const: dc
resets:
items:
- description: display controller reset
reset-names:
items:
- const: dc
power-domains:
maxItems: 1
iommus:
maxItems: 1
interconnects:
description: Description of the interconnect paths for the
display controller; see ../interconnect/interconnect.txt
for details.
interconnect-names:
items:
- const: dma-mem # read-0
- const: read-1
nvidia,outputs:
description: A list of phandles of outputs that this display
controller can drive.
$ref: "/schemas/types.yaml#/definitions/phandle-array"
nvidia,head:
description: The number of the display controller head. This
is used to setup the various types of output to receive
video data from the given head.
$ref: "/schemas/types.yaml#/definitions/uint32"
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- power-domains
- nvidia,outputs
- nvidia,head
# see nvidia,tegra186-display.yaml for examples
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
+310
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@@ -0,0 +1,310 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 (and later) Display Hub
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^display-hub@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra186-display
- nvidia,tegra194-display
'#address-cells':
const: 1
'#size-cells':
const: 1
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
maxItems: 3
resets:
items:
- description: display hub reset
- description: window group 0 reset
- description: window group 1 reset
- description: window group 2 reset
- description: window group 3 reset
- description: window group 4 reset
- description: window group 5 reset
reset-names:
items:
- const: misc
- const: wgrp0
- const: wgrp1
- const: wgrp2
- const: wgrp3
- const: wgrp4
- const: wgrp5
power-domains:
maxItems: 1
ranges:
maxItems: 1
patternProperties:
"^display@[0-9a-f]+$":
type: object
allOf:
- if:
properties:
compatible:
contains:
const: nvidia,tegra186-display
then:
properties:
clocks:
items:
- description: display core clock
- description: display stream compression clock
- description: display hub clock
clock-names:
items:
- const: disp
- const: dsc
- const: hub
else:
properties:
clocks:
items:
- description: display core clock
- description: display hub clock
clock-names:
items:
- const: disp
- const: hub
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
- "#address-cells"
- "#size-cells"
- ranges
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
display-hub@15200000 {
compatible = "nvidia,tegra186-display";
reg = <0x15200000 0x00040000>;
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
"wgrp3", "wgrp4", "wgrp5";
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
<&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
<&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
clock-names = "disp", "dsc", "hub";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x15200000 0x15200000 0x40000>;
display@15200000 {
compatible = "nvidia,tegra186-dc";
reg = <0x15200000 0x10000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
clock-names = "dc";
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
nvidia,head = <0>;
};
display@15210000 {
compatible = "nvidia,tegra186-dc";
reg = <0x15210000 0x10000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
clock-names = "dc";
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
nvidia,head = <1>;
};
display@15220000 {
compatible = "nvidia,tegra186-dc";
reg = <0x15220000 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
clock-names = "dc";
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1>;
nvidia,head = <2>;
};
};
- |
#include <dt-bindings/clock/tegra194-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra194-mc.h>
#include <dt-bindings/power/tegra194-powergate.h>
#include <dt-bindings/reset/tegra194-reset.h>
display-hub@15200000 {
compatible = "nvidia,tegra194-display";
reg = <0x15200000 0x00040000>;
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
"wgrp3", "wgrp4", "wgrp5";
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
<&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
clock-names = "disp", "hub";
status = "disabled";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x15200000 0x15200000 0x40000>;
display@15200000 {
compatible = "nvidia,tegra194-dc";
reg = <0x15200000 0x10000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
clock-names = "dc";
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <0>;
};
display@15210000 {
compatible = "nvidia,tegra194-dc";
reg = <0x15210000 0x10000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
clock-names = "dc";
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <1>;
};
display@15220000 {
compatible = "nvidia,tegra194-dc";
reg = <0x15220000 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
clock-names = "dc";
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <2>;
};
display@15230000 {
compatible = "nvidia,tegra194-dc";
reg = <0x15230000 0x10000>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
clock-names = "dc";
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <3>;
};
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dsi-padctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra MIPI DSI pad controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^padctl@[0-9a-f]+$"
compatible:
const: nvidia,tegra186-dsi-padctl
reg:
maxItems: 1
resets:
items:
- description: module reset
reset-names:
items:
- const: dsi
allOf:
- $ref: "/schemas/reset/reset.yaml"
additionalProperties: false
examples:
- |
#include <dt-bindings/reset/tegra186-reset.h>
padctl@15880000 {
compatible = "nvidia,tegra186-dsi-padctl";
reg = <0x15880000 0x10000>;
resets = <&bpmp TEGRA186_RESET_DSI>;
reset-names = "dsi";
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Display Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^dc@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra20-dc
- nvidia,tegra30-dc
- nvidia,tegra114-dc
- nvidia,tegra124-dc
- nvidia,tegra210-dc
- items:
- const: nvidia,tegra124-dc
- const: nvidia,tegra132-dc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description: display controller pixel clock
- description: parent clock # optional
clock-names:
minItems: 1
items:
- const: dc
- const: parent # optional
resets:
items:
- description: module reset
reset-names:
items:
- const: dc
interconnect-names: true
interconnects: true
iommus:
maxItems: 1
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
power-domains:
items:
- description: phandle to the core power domain
memory-region: true
nvidia,head:
$ref: /schemas/types.yaml#/definitions/uint32
description: The number of the display controller head. This is used to setup the various
types of output to receive video data from the given head.
nvidia,outputs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: A list of phandles of outputs that this display controller can drive.
rgb:
type: object
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-dc
- nvidia,tegra30-dc
- nvidia,tegra114-dc
then:
properties:
interconnects:
items:
- description: window A memory client
- description: window B memory client
- description: window B memory client (vertical filter)
- description: window C memory client
- description: cursor memory client
interconnect-names:
items:
- const: wina
- const: winb
- const: winb-vfilter
- const: winc
- const: cursor
rgb:
description: Each display controller node has a child node, named "rgb", that represents
the RGB output associated with the controller.
type: object
properties:
nvidia,ddc-i2c-bus:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle of an I2C controller used for DDC EDID probing
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
maxItems: 1
nvidia,edid:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: supplies a binary EDID blob
nvidia,panel:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle of a display panel
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra124-dc
then:
properties:
interconnects:
minItems: 4
items:
- description: window A memory client
- description: window B memory client
- description: window C memory client
- description: cursor memory client
- description: window D memory client
- description: window T memory client
interconnect-names:
minItems: 4
items:
- const: wina
- const: winb
- const: winc
- const: cursor
- const: wind
- const: wint
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
dc@54200000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_DISP1>;
clock-names = "dc";
resets = <&tegra_car 27>;
reset-names = "dc";
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Display Serial Interface
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra20-dsi
- nvidia,tegra30-dsi
- nvidia,tegra114-dsi
- nvidia,tegra124-dsi
- nvidia,tegra210-dsi
- nvidia,tegra186-dsi
- items:
- const: nvidia,tegra132-dsi
- const: nvidia,tegra124-dsi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
maxItems: 3
resets:
items:
- description: module reset
reset-names:
items:
- const: dsi
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
power-domains:
maxItems: 1
avdd-dsi-csi-supply:
description: phandle of a supply that powers the DSI controller
nvidia,mipi-calibrate:
description: Should contain a phandle and a specifier specifying
which pads are used by this DSI output and need to be
calibrated. See nvidia,tegra114-mipi.yaml for details.
$ref: "/schemas/types.yaml#/definitions/phandle-array"
nvidia,ddc-i2c-bus:
description: phandle of an I2C controller used for DDC EDID
probing
$ref: "/schemas/types.yaml#/definitions/phandle"
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
maxItems: 1
nvidia,edid:
description: supplies a binary EDID blob
$ref: "/schemas/types.yaml#/definitions/uint8-array"
nvidia,panel:
description: phandle of a display panel
$ref: "/schemas/types.yaml#/definitions/phandle"
nvidia,ganged-mode:
description: contains a phandle to a second DSI controller to
gang up with in order to support up to 8 data lanes
$ref: "/schemas/types.yaml#/definitions/phandle"
allOf:
- $ref: "../dsi-controller.yaml#"
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-dsi
- nvidia,tegra30-dsi
then:
properties:
clocks:
items:
- description: DSI module clock
- description: input for the pixel clock
clock-names:
items:
- const: dsi
- const: parent
else:
properties:
clocks:
items:
- description: DSI module clock
- description: low-power module clock
- description: input for the pixel clock
clock-names:
items:
- const: dsi
- const: lp
- const: parent
- if:
properties:
compatible:
contains:
const: nvidia,tegra186-dsi
then:
required:
- interrupts
unevaluatedProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
dsi@15300000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x15300000 0x10000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DSI>,
<&bpmp TEGRA186_CLK_DSIA_LP>,
<&bpmp TEGRA186_CLK_PLLD>;
clock-names = "dsi", "lp", "parent";
resets = <&bpmp TEGRA186_RESET_DSI>;
reset-names = "dsi";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Encoder Pre-Processor
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^epp@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-epp
- nvidia,tegra30-epp
- nvidia,tegra114-epp
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
items:
- description: module reset
reset-names:
items:
- const: epp
iommus:
maxItems: 1
interconnects:
maxItems: 4
interconnect-names:
maxItems: 4
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
power-domains:
items:
- description: phandle to the core power domain
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
epp@540c0000 {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA 2D graphics engine
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^gr2d@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-gr2d
- nvidia,tegra30-gr2d
- nvidia,tegra114-gr2d
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
resets:
items:
- description: module reset
- description: memory client hotflush reset
reset-names:
items:
- const: 2d
- const: mc
iommus:
maxItems: 1
interconnects:
maxItems: 4
interconnect-names:
maxItems: 4
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
power-domains:
items:
- description: phandle to the HEG or core power domain
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra20-mc.h>
gr2d@54140000 {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
reset-names = "2d", "mc";
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA 3D graphics engine
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^gr3d@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-gr3d
- nvidia,tegra30-gr3d
- nvidia,tegra114-gr3d
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
resets:
minItems: 2
maxItems: 4
reset-names:
minItems: 2
maxItems: 4
iommus:
minItems: 1
maxItems: 2
interconnects:
minItems: 4
maxItems: 10
interconnect-names:
minItems: 4
maxItems: 10
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
power-domains:
minItems: 1
maxItems: 2
power-domain-names:
minItems: 2
maxItems: 2
allOf:
- if:
properties:
compatible:
contains:
const: nvidia,tegra20-gr2d
then:
properties:
clocks:
items:
- description: module clock
clock-names:
items:
- const: 3d
resets:
items:
- description: module reset
- description: memory client hotflush reset
reset-names:
items:
- const: 3d
- const: mc
iommus:
maxItems: 1
interconnects:
minItems: 4
maxItems: 4
interconnect-names:
minItems: 4
maxItems: 4
power-domains:
items:
- description: phandle to the TD power domain
- if:
properties:
compatible:
contains:
const: nvidia,tegra30-gr3d
then:
properties:
clocks:
items:
- description: primary module clock
- description: secondary module clock
clock-names:
items:
- const: 3d
- const: 3d2
resets:
items:
- description: primary module reset
- description: secondary module reset
- description: primary memory client hotflush reset
- description: secondary memory client hotflush reset
reset-names:
items:
- const: 3d
- const: 3d2
- const: mc
- const: mc2
iommus:
minItems: 2
maxItems: 2
interconnects:
minItems: 8
maxItems: 8
interconnect-names:
minItems: 8
maxItems: 8
power-domains:
items:
- description: phandle to the TD power domain
- description: phandle to the TD2 power domain
power-domain-names:
items:
- const: 3d0
- const: 3d1
dependencies:
power-domains: [ power-domain-names ]
- if:
properties:
compatible:
contains:
const: nvidia,tegra114-gr2d
then:
properties:
clocks:
items:
- description: module clock
clock-names:
items:
- const: 3d
resets:
items:
- description: module reset
- description: memory client hotflush reset
reset-names:
items:
- const: 3d
- const: mc
iommus:
maxItems: 1
interconnects:
minItems: 10
maxItems: 10
interconnect-names:
minItems: 10
maxItems: 10
power-domains:
items:
- description: phandle to the TD power domain
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/memory/tegra20-mc.h>
gr3d@54180000 {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
reset-names = "3d", "mc";
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra HDMI Output Encoder
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^hdmi@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra20-hdmi
- nvidia,tegra30-hdmi
- nvidia,tegra114-hdmi
- nvidia,tegra124-hdmi
- items:
- const: nvidia,tegra132-hdmi
- const: nvidia,tegra124-hdmi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
- description: parent clock
clock-names:
items:
- const: hdmi
- const: parent
resets:
items:
- description: module reset
reset-names:
items:
- const: hdmi
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
power-domains:
items:
- description: phandle to the core power domain
hdmi-supply:
description: supply for the +5V HDMI connector pin
vdd-supply:
description: regulator for supply voltage
pll-supply:
description: regulator for PLL
nvidia,ddc-i2c-bus:
description: phandle of an I2C controller used for DDC EDID
probing
$ref: "/schemas/types.yaml#/definitions/phandle"
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
maxItems: 1
nvidia,edid:
description: supplies a binary EDID blob
$ref: "/schemas/types.yaml#/definitions/uint8-array"
nvidia,panel:
description: phandle of a display panel
$ref: "/schemas/types.yaml#/definitions/phandle"
"#sound-dai-cells":
const: 0
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- pll-supply
- vdd-supply
- nvidia,ddc-i2c-bus
- nvidia,hpd-gpio
examples:
- |
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/tegra-gpio.h>
hdmi@54280000 {
compatible = "nvidia,tegra124-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_HDMI>,
<&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
hdmi-supply = <&vdd_5v0_hdmi>;
pll-supply = <&vdd_hdmi_pll>;
vdd-supply = <&vdd_3v3_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
-675
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@@ -1,675 +0,0 @@
NVIDIA Tegra host1x
Required properties:
- compatible: "nvidia,tegra<chip>-host1x"
- reg: Physical base address and length of the controller's registers.
For pre-Tegra186, one entry describing the whole register area.
For Tegra186, one entry for each entry in reg-names:
"vm" - VM region assigned to Linux
"hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
- interrupts: The interrupt outputs from the controller.
- #address-cells: The number of cells used to represent physical base addresses
in the host1x address space. Should be 1.
- #size-cells: The number of cells used to represent the size of an address
range in the host1x address space. Should be 1.
- ranges: The mapping of the host1x address space to the CPU address space.
- clocks: Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- host1x
- mc
Optional properties:
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- power-domains: Phandle to HEG or core power domain.
For each opp entry in 'operating-points-v2' table of host1x and its modules:
- opp-supported-hw: One bitfield indicating:
On Tegra20: SoC process ID mask
On Tegra30+: SoC speedo ID mask
A bitwise AND is performed against the value and if any bit
matches, the OPP gets enabled.
Each host1x client module having to perform DMA through the Memory Controller
should have the interconnect endpoints set to the Memory Client and External
Memory respectively.
The host1x top-level node defines a number of children, each representing one
of the following host1x client modules:
- mpe: video encoder
Required properties:
- compatible: "nvidia,tegra<chip>-mpe"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- mpe
Optional properties:
- interconnects: Must contain entry for the MPE memory clients.
- interconnect-names: Must include name of the interconnect path for each
interconnect entry. Consult TRM documentation for information about
available memory clients, see MEMORY CONTROLLER section.
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- power-domains: Phandle to MPE power domain.
- vi: video input
Required properties:
- compatible: "nvidia,tegra<chip>-vi"
- reg: Physical base address and length of the controller registers.
- interrupts: The interrupt outputs from the controller.
- clocks: clocks: Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- Tegra20/Tegra30/Tegra114/Tegra124:
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- vi
- Tegra210:
- power-domains: Must include venc powergate node as vi is in VE partition.
ports (optional node)
vi can have optional ports node and max 6 ports are supported. Each port
should have single 'endpoint' child node. All port nodes are grouped under
ports node. Please refer to the bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt
csi (required node)
Tegra210 has CSI part of VI sharing same host interface and register space.
So, VI device node should have CSI child node.
- csi: mipi csi interface to vi
Required properties:
- compatible: "nvidia,tegra210-csi"
- reg: Physical base address offset to parent and length of the controller
registers.
- clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
See ../clocks/clock-bindings.txt for details.
- power-domains: Must include sor powergate node as csicil is in
SOR partition.
channel (optional nodes)
Maximum 6 channels are supported with each csi brick as either x4 or x2
based on hw connectivity to sensor.
Required properties:
- reg: csi port number. Valid port numbers are 0 through 5.
- nvidia,mipi-calibrate: Should contain a phandle and a specifier
specifying which pads are used by this CSI port and need to be
calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
Each channel node must contain 2 port nodes which can be grouped
under 'ports' node and each port should have a single child 'endpoint'
node.
ports node
Please refer to the bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt
ports node must contain below 2 port nodes.
port@0 with single child 'endpoint' node always a sink.
port@1 with single child 'endpoint' node always a source.
port@0 (required node)
Required properties:
- reg: 0
endpoint (required node)
Required properties:
- data-lanes: an array of data lane from 1 to 8. Valid array
lengths are 1/2/4/8.
- remote-endpoint: phandle to sensor 'endpoint' node.
port@1 (required node)
Required properties:
- reg: 1
endpoint (required node)
Required properties:
- remote-endpoint: phandle to vi port 'endpoint' node.
Optional properties:
- interconnects: Must contain entry for the VI memory clients.
- interconnect-names: Must include name of the interconnect path for each
interconnect entry. Consult TRM documentation for information about
available memory clients, see MEMORY CONTROLLER section.
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- power-domains: Phandle to VENC power domain.
- epp: encoder pre-processor
Required properties:
- compatible: "nvidia,tegra<chip>-epp"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- epp
Optional properties:
- interconnects: Must contain entry for the EPP memory clients.
- interconnect-names: Must include name of the interconnect path for each
interconnect entry. Consult TRM documentation for information about
available memory clients, see MEMORY CONTROLLER section.
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- power-domains: Phandle to HEG or core power domain.
- isp: image signal processor
Required properties:
- compatible: "nvidia,tegra<chip>-isp"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- isp
Optional properties:
- interconnects: Must contain entry for the ISP memory clients.
- interconnect-names: Must include name of the interconnect path for each
interconnect entry. Consult TRM documentation for information about
available memory clients, see MEMORY CONTROLLER section.
- power-domains: Phandle to VENC or core power domain.
- gr2d: 2D graphics engine
Required properties:
- compatible: "nvidia,tegra<chip>-gr2d"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- 2d
- mc
Optional properties:
- interconnects: Must contain entry for the GR2D memory clients.
- interconnect-names: Must include name of the interconnect path for each
interconnect entry. Consult TRM documentation for information about
available memory clients, see MEMORY CONTROLLER section.
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- power-domains: Phandle to HEG or core power domain.
- gr3d: 3D graphics engine
Required properties:
- compatible: "nvidia,tegra<chip>-gr3d"
- reg: Physical base address and length of the controller's registers.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
(This property may be omitted if the only clock in the list is "3d")
- 3d
This MUST be the first entry.
- 3d2 (Only required on SoCs with two 3D clocks)
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- 3d
- 3d2 (Only required on SoCs with two 3D clocks)
- mc
- mc2 (Only required on SoCs with two 3D clocks)
Optional properties:
- interconnects: Must contain entry for the GR3D memory clients.
- interconnect-names: Must include name of the interconnect path for each
interconnect entry. Consult TRM documentation for information about
available memory clients, see MEMORY CONTROLLER section.
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- power-domains: Phandles to 3D or core power domain.
- dc: display controller
Required properties:
- compatible: "nvidia,tegra<chip>-dc"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- dc
This MUST be the first entry.
- parent
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- dc
- nvidia,head: The number of the display controller head. This is used to
setup the various types of output to receive video data from the given
head.
Each display controller node has a child node, named "rgb", that represents
the RGB output associated with the controller. It can take the following
optional properties:
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- nvidia,edid: supplies a binary EDID blob
- nvidia,panel: phandle of a display panel
- interconnects: Must contain entry for the DC memory clients.
- interconnect-names: Must include name of the interconnect path for each
interconnect entry. Consult TRM documentation for information about
available memory clients, see MEMORY CONTROLLER section.
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- power-domains: Phandle to core power domain.
- hdmi: High Definition Multimedia Interface
Required properties:
- compatible: "nvidia,tegra<chip>-hdmi"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- hdmi-supply: supply for the +5V HDMI connector pin
- vdd-supply: regulator for supply voltage
- pll-supply: regulator for PLL
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- hdmi
This MUST be the first entry.
- parent
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- hdmi
Optional properties:
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- nvidia,edid: supplies a binary EDID blob
- nvidia,panel: phandle of a display panel
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- tvo: TV encoder output
Required properties:
- compatible: "nvidia,tegra<chip>-tvo"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
Optional properties:
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- power-domains: Phandle to core power domain.
- dsi: display serial interface
Required properties:
- compatible: "nvidia,tegra<chip>-dsi"
- reg: Physical base address and length of the controller's registers.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- dsi
This MUST be the first entry.
- lp
- parent
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- dsi
- avdd-dsi-supply: phandle of a supply that powers the DSI controller
- nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
which pads are used by this DSI output and need to be calibrated. See also
../display/tegra/nvidia,tegra114-mipi.txt.
Optional properties:
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- nvidia,edid: supplies a binary EDID blob
- nvidia,panel: phandle of a display panel
- nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
up with in order to support up to 8 data lanes
- operating-points-v2: See ../bindings/opp/opp.txt for details.
- sor: serial output resource
Required properties:
- compatible: Should be:
- "nvidia,tegra124-sor": for Tegra124 and Tegra132
- "nvidia,tegra132-sor": for Tegra132
- "nvidia,tegra210-sor": for Tegra210
- "nvidia,tegra210-sor1": for Tegra210
- "nvidia,tegra186-sor": for Tegra186
- "nvidia,tegra186-sor1": for Tegra186
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- sor: clock input for the SOR hardware
- out: SOR output clock
- parent: input for the pixel clock
- dp: reference clock for the SOR clock
- safe: safe reference for the SOR clock during power up
For Tegra186 and later:
- pad: SOR pad output clock (on Tegra186 and later)
Obsolete:
- source: source clock for the SOR clock (obsolete, use "out" instead)
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- sor
Required properties on Tegra186 and later:
- nvidia,interface: index of the SOR interface
Optional properties:
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- nvidia,edid: supplies a binary EDID blob
- nvidia,panel: phandle of a display panel
- nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
of the SOR, identified by the cell's index, is mapped via the crossbar to
the pad specified by the cell's value.
Optional properties when driving an eDP output:
- nvidia,dpaux: phandle to a DispayPort AUX interface
- dpaux: DisplayPort AUX interface
- compatible : Should contain one of the following:
- "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
- "nvidia,tegra210-dpaux": for Tegra210
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- dpaux: clock input for the DPAUX hardware
- parent: reference clock
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- dpaux
- vdd-supply: phandle of a supply that powers the DisplayPort link
- i2c-bus: Subnode where I2C slave devices are listed. This subnode
must be always present. If there are no I2C slave devices, an empty
node should be added. See ../../i2c/i2c.txt for more information.
See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
regarding the DPAUX pad controller bindings.
- vic: Video Image Compositor
- compatible : "nvidia,tegra<chip>-vic"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- vic: clock input for the VIC hardware
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- vic
Optional properties:
- interconnects: Must contain entry for the VIC memory clients.
- interconnect-names: Must include name of the interconnect path for each
interconnect entry. Consult TRM documentation for information about
available memory clients, see MEMORY CONTROLLER section.
Example:
/ {
...
host1x {
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
interrupts = <0 65 0x04 /* mpcore syncpt */
0 67 0x04>; /* mpcore general */
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
resets = <&tegra_car 28>;
reset-names = "host1x";
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x54000000 0x54000000 0x04000000>;
mpe {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <0 68 0x04>;
clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
};
vi@54080000 {
compatible = "nvidia,tegra210-vi";
reg = <0x0 0x54080000 0x0 0x700>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
operating-points-v2 = <&dvfs_opp_table>;
clocks = <&tegra_car TEGRA210_CLK_VI>;
power-domains = <&pd_venc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x54080000 0x2000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
imx219_vi_in0: endpoint {
remote-endpoint = <&imx219_csi_out0>;
};
};
};
csi@838 {
compatible = "nvidia,tegra210-csi";
reg = <0x838 0x1300>;
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>;
assigned-clock-rates = <102000000>,
<102000000>,
<102000000>,
<972000000>;
clocks = <&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
power-domains = <&pd_sor>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
nvidia,mipi-calibrate = <&mipi 0x001>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
imx219_csi_in0: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&imx219_out0>;
};
};
port@1 {
reg = <1>;
imx219_csi_out0: endpoint {
remote-endpoint = <&imx219_vi_in0>;
};
};
};
};
};
};
epp {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <0 70 0x04>;
clocks = <&tegra_car TEGRA20_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
};
isp {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
interrupts = <0 71 0x04>;
clocks = <&tegra_car TEGRA20_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
};
gr2d {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <0 72 0x04>;
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
};
gr3d {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>;
reset-names = "3d";
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
};
dc@54200000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <0 73 0x04>;
clocks = <&tegra_car TEGRA20_CLK_DISP1>,
<&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
<&mc TEGRA20_MC_DISPLAY0B &emc>,
<&mc TEGRA20_MC_DISPLAY0C &emc>,
<&mc TEGRA20_MC_DISPLAYHC &emc>;
interconnect-names = "wina",
"winb",
"winc",
"cursor";
rgb {
status = "disabled";
};
};
dc@54240000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54240000 0x00040000>;
interrupts = <0 74 0x04>;
clocks = <&tegra_car TEGRA20_CLK_DISP2>,
<&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
<&mc TEGRA20_MC_DISPLAY0BB &emc>,
<&mc TEGRA20_MC_DISPLAY0CB &emc>,
<&mc TEGRA20_MC_DISPLAYHCB &emc>;
interconnect-names = "wina",
"winb",
"winc",
"cursor";
rgb {
status = "disabled";
};
};
hdmi {
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <0 75 0x04>;
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
status = "disabled";
operating-points-v2 = <&dvfs_opp_table>;
};
tvo {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <0 76 0x04>;
clocks = <&tegra_car TEGRA20_CLK_TVO>;
status = "disabled";
operating-points-v2 = <&dvfs_opp_table>;
};
dsi {
compatible = "nvidia,tegra20-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_DSI>,
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
status = "disabled";
operating-points-v2 = <&dvfs_opp_table>;
};
};
...
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra host1x controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: The host1x top-level node defines a number of children, each
representing one of the host1x client modules defined in this binding.
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra20-host1x
- nvidia,tegra30-host1x
- nvidia,tegra114-host1x
- nvidia,tegra124-host1x
- nvidia,tegra210-host1x
- nvidia,tegra186-host1x
- nvidia,tegra194-host1x
- nvidia,tegra234-host1x
- items:
- const: nvidia,tegra132-host1x
- const: nvidia,tegra124-host1x
reg:
minItems: 1
maxItems: 3
reg-names:
minItems: 1
maxItems: 3
interrupts:
minItems: 1
maxItems: 9
interrupt-names:
minItems: 1
maxItems: 9
'#address-cells':
description: The number of cells used to represent physical base addresses
in the host1x address space.
enum: [1, 2]
'#size-cells':
description: The number of cells used to represent the size of an address
range in the host1x address space.
enum: [1, 2]
ranges:
maxItems: 1
clocks:
description: Must contain one entry, for the module clock. See
../clocks/clock-bindings.txt for details.
clock-names:
items:
- const: host1x
resets:
minItems: 1 # MC reset is optional on Tegra186 and later
items:
- description: module reset
- description: memory client hotflush reset
reset-names:
minItems: 1 # MC reset is optional on Tegra186 and later
items:
- const: host1x
- const: mc
iommus:
maxItems: 1
interconnects:
items:
- description: memory read client for host1x
interconnect-names:
items:
- const: dma-mem # read
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
power-domains:
items:
- description: phandle to the HEG or core power domain
required:
- compatible
- interrupts
- interrupt-names
- '#address-cells'
- '#size-cells'
- ranges
- reg
- clocks
- clock-names
unevaluatedProperties:
type: object
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-host1x
- nvidia,tegra30-host1x
- nvidia,tegra114-host1x
- nvidia,tegra124-host1x
- nvidia,tegra210-host1x
then:
properties:
interrupts:
items:
- description: host1x syncpoint interrupt
- description: host1x general interrupt
interrupt-names:
items:
- const: syncpt
- const: host1x
required:
- resets
- reset-names
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra186-host1x
- nvidia,tegra194-host1x
then:
properties:
reg-names:
items:
- const: hypervisor
- const: vm
reg:
items:
- description: region used by the hypervisor
- description: region assigned to the virtual machine
resets:
maxItems: 1
reset-names:
maxItems: 1
interrupts:
items:
- description: host1x syncpoint interrupt
- description: host1x general interrupt
interrupt-names:
items:
- const: syncpt
- const: host1x
iommu-map:
description: Specification of stream IDs available for memory context device
use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
usable stream IDs.
required:
- reg-names
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra234-host1x
then:
properties:
reg-names:
items:
- const: common
- const: hypervisor
- const: vm
reg:
items:
- description: region used by host1x server
- description: region used by the hypervisor
- description: region assigned to the virtual machine
interrupts:
items:
- description: host1x syncpoint interrupt 0
- description: host1x syncpoint interrupt 1
- description: host1x syncpoint interrupt 2
- description: host1x syncpoint interrupt 3
- description: host1x syncpoint interrupt 4
- description: host1x syncpoint interrupt 5
- description: host1x syncpoint interrupt 6
- description: host1x syncpoint interrupt 7
- description: host1x general interrupt
interrupt-names:
items:
- const: syncpt0
- const: syncpt1
- const: syncpt2
- const: syncpt3
- const: syncpt4
- const: syncpt5
- const: syncpt6
- const: syncpt7
- const: host1x
iommu-map:
description: Specification of stream IDs available for memory context device
use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
usable stream IDs.
required:
- reg-names
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra20-mc.h>
host1x@50000000 {
compatible = "nvidia,tegra20-host1x";
reg = <0x50000000 0x00024000>;
interrupts = <0 65 0x04>, /* mpcore syncpt */
<0 67 0x04>; /* mpcore general */
interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
reset-names = "host1x", "mc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x54000000 0x54000000 0x04000000>;
mpe@54040000 {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <0 68 0x04>;
clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
};
vi@54080000 {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
interrupts = <0 69 0x04>;
clocks = <&tegra_car TEGRA20_CLK_VI>;
resets = <&tegra_car 100>;
reset-names = "vi";
};
epp@540c0000 {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <0 70 0x04>;
clocks = <&tegra_car TEGRA20_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
};
isp@54100000 {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
interrupts = <0 71 0x04>;
clocks = <&tegra_car TEGRA20_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
};
gr2d@54140000 {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <0 72 0x04>;
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
reset-names = "2d", "mc";
};
gr3d@54180000 {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
reset-names = "3d", "mc";
};
dc@54200000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <0 73 0x04>;
clocks = <&tegra_car TEGRA20_CLK_DISP1>;
clock-names = "dc";
resets = <&tegra_car 27>;
reset-names = "dc";
rgb {
};
};
dc@54240000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54240000 0x00040000>;
interrupts = <0 74 0x04>;
clocks = <&tegra_car TEGRA20_CLK_DISP2>;
clock-names = "dc";
resets = <&tegra_car 26>;
reset-names = "dc";
rgb {
};
};
hdmi@54280000 {
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <0 75 0x04>;
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
hdmi-supply = <&vdd_5v0_hdmi>;
pll-supply = <&vdd_hdmi_pll>;
vdd-supply = <&vdd_3v3_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
};
tvo@542c0000 {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <0 76 0x04>;
clocks = <&tegra_car TEGRA20_CLK_TVO>;
};
dsi@54300000 {
compatible = "nvidia,tegra20-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_DSI>,
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
};
};
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra210-mc.h>
host1x@50000000 {
compatible = "nvidia,tegra210-host1x";
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x54000000 0x54000000 0x01000000>;
iommus = <&mc TEGRA_SWGROUP_HC>;
vi@54080000 {
compatible = "nvidia,tegra210-vi";
reg = <0x54080000 0x00000700>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
clocks = <&tegra_car TEGRA210_CLK_VI>;
power-domains = <&pd_venc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x54080000 0x2000>;
csi@838 {
compatible = "nvidia,tegra210-csi";
reg = <0x838 0x1300>;
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>;
assigned-clock-rates = <102000000>,
<102000000>,
<102000000>,
<972000000>;
clocks = <&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
power-domains = <&pd_sor>;
};
};
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra ISP processor
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
enum:
- nvidia,tegra20-isp
- nvidia,tegra30-isp
- nvidia,tegra210-isp
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
resets:
items:
- description: module reset
reset-names:
items:
- const: isp
iommus:
maxItems: 1
interconnects:
items:
- description: memory write client
interconnect-names:
items:
- const: dma-mem # write
power-domains:
items:
- description: phandle to the VENC or core power domain
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
isp@54100000 {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Video Encoder
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^mpe@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-mpe
- nvidia,tegra30-mpe
- nvidia,tegra114-mpe
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
resets:
items:
- description: module reset
reset-names:
items:
- const: mpe
iommus:
maxItems: 1
interconnects:
minItems: 6
maxItems: 6
interconnect-names:
minItems: 6
maxItems: 6
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
power-domains:
items:
- description: phandle to the MPE power domain
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mpe@54040000 {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
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@@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra TV Encoder Output
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^tvo@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-tvo
- nvidia,tegra30-tvo
- nvidia,tegra114-tvo
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
power-domains:
items:
- description: phandle to the core power domain
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
tvo@542c0000 {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_TVO>;
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Video Input controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^vi@[0-9a-f]+$"
compatible:
oneOf:
- const: nvidia,tegra20-vi
- const: nvidia,tegra30-vi
- const: nvidia,tegra114-vi
- const: nvidia,tegra124-vi
- items:
- const: nvidia,tegra132-vi
- const: nvidia,tegra124-vi
- const: nvidia,tegra210-vi
- const: nvidia,tegra186-vi
- const: nvidia,tegra194-vi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
items:
- description: module reset
reset-names:
items:
- const: vi
iommus:
maxItems: 1
interconnects:
minItems: 4
maxItems: 5
interconnect-names:
minItems: 4
maxItems: 5
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
power-domains:
items:
- description: phandle to the VENC power domain
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges:
maxItems: 1
avdd-dsi-csi-supply:
description: DSI/CSI power supply. Must supply 1.2 V.
patternProperties:
"^csi@[0-9a-f]+$":
type: object
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-vi
- nvidia,tegra30-vi
- nvidia,tegra114-vi
- nvidia,tegra124-vi
then:
required:
- resets
- reset-names
else:
required:
- power-domains
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
vi@54080000 {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_VI>;
resets = <&tegra_car 100>;
reset-names = "vi";
};
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
vi@54080000 {
compatible = "nvidia,tegra210-vi";
reg = <0x54080000 0x00000700>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
clocks = <&tegra_car TEGRA210_CLK_VI>;
power-domains = <&pd_venc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x54080000 0x2000>;
csi@838 {
compatible = "nvidia,tegra210-csi";
reg = <0x838 0x1300>;
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>;
assigned-clock-rates = <102000000>,
<102000000>,
<102000000>,
<972000000>;
clocks = <&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
power-domains = <&pd_sor>;
};
};
Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra CSI controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^csi@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra210-csi
reg:
maxItems: 1
clocks:
items:
- description: module clock
- description: A/B lanes clock
- description: C/D lanes clock
- description: E lane clock
- description: test pattern generator clock
clock-names:
items:
- const: csi
- const: cilab
- const: cilcd
- const: cile
- const: csi_tpg
power-domains:
maxItems: 1
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
# see nvidia,tegra20-vi.yaml for an example
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+15 -10
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@@ -14,16 +14,21 @@ properties:
pattern: '^gpu@[a-f0-9]+$'
compatible:
items:
- enum:
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
oneOf:
- items:
- enum:
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
- items:
- enum:
- mediatek,mt8192-mali
- const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
reg:
maxItems: 1
Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
+1
View File
@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- brcm,2711-v3d
- brcm,7268-v3d
- brcm,7278-v3d
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
+43 -13
View File
@@ -42,6 +42,7 @@ properties:
port:
$ref: /schemas/graph.yaml#/$defs/port-base
description: Parallel input port, connect to a parallel sensor
properties:
endpoint:
@@ -59,7 +60,24 @@ properties:
required:
- bus-width
additionalProperties: false
unevaluatedProperties: false
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: "#/properties/port"
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: MIPI CSI-2 bridge input port
anyOf:
- required:
- port@0
- required:
- port@1
required:
- compatible
@@ -69,6 +87,12 @@ required:
- clock-names
- resets
oneOf:
- required:
- ports
- required:
- port
additionalProperties: false
examples:
@@ -89,19 +113,25 @@ examples:
"ram";
resets = <&ccu RST_BUS_CSI>;
port {
/* Parallel bus endpoint */
csi1_ep: endpoint {
remote-endpoint = <&adv7611_ep>;
bus-width = <16>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/*
* If hsync-active/vsync-active are missing,
* embedded BT.656 sync is used.
*/
hsync-active = <0>; /* Active low */
vsync-active = <0>; /* Active low */
pclk-sample = <1>; /* Rising */
port@0 {
reg = <0>;
/* Parallel bus endpoint */
csi1_ep: endpoint {
remote-endpoint = <&adv7611_ep>;
bus-width = <16>;
/*
* If hsync-active/vsync-active are missing,
* embedded BT.656 sync is used.
*/
hsync-active = <0>; /* Active low */
vsync-active = <0>; /* Active low */
pclk-sample = <1>; /* Rising */
};
};
};
};
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
+137
View File
@@ -0,0 +1,137 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A31 MIPI CSI-2 Device Tree Bindings
maintainers:
- Paul Kocialkowski <paul.kocialkowski@bootlin.com>
properties:
compatible:
oneOf:
- const: allwinner,sun6i-a31-mipi-csi2
- items:
- const: allwinner,sun8i-v3s-mipi-csi2
- const: allwinner,sun6i-a31-mipi-csi2
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
clock-names:
items:
- const: bus
- const: mod
phys:
maxItems: 1
description: MIPI D-PHY
phy-names:
items:
- const: dphy
resets:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
description: Input port, connect to a MIPI CSI-2 sensor
properties:
reg:
const: 0
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
unevaluatedProperties: false
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output port, connect to a CSI controller
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- phys
- phy-names
- resets
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
mipi_csi2: csi@1cb1000 {
compatible = "allwinner,sun8i-v3s-mipi-csi2",
"allwinner,sun6i-a31-mipi-csi2";
reg = <0x01cb1000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
<&ccu CLK_CSI1_SCLK>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_CSI>;
phys = <&dphy>;
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_in: port@0 {
reg = <0>;
mipi_csi2_in_ov5648: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&ov5648_out_mipi_csi2>;
};
};
mipi_csi2_out: port@1 {
reg = <1>;
mipi_csi2_out_csi0: endpoint {
remote-endpoint = <&csi0_in_mipi_csi2>;
};
};
};
};
...
Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
+125
View File
@@ -0,0 +1,125 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A83T MIPI CSI-2 Device Tree Bindings
maintainers:
- Paul Kocialkowski <paul.kocialkowski@bootlin.com>
properties:
compatible:
const: allwinner,sun8i-a83t-mipi-csi2
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
- description: MIPI-specific Clock
- description: Misc CSI Clock
clock-names:
items:
- const: bus
- const: mod
- const: mipi
- const: misc
resets:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
description: Input port, connect to a MIPI CSI-2 sensor
properties:
reg:
const: 0
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
unevaluatedProperties: false
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output port, connect to a CSI controller
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
mipi_csi2: csi@1cb1000 {
compatible = "allwinner,sun8i-a83t-mipi-csi2";
reg = <0x01cb1000 0x1000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
<&ccu CLK_CSI_SCLK>,
<&ccu CLK_MIPI_CSI>,
<&ccu CLK_CSI_MISC>;
clock-names = "bus", "mod", "mipi", "misc";
resets = <&ccu RST_BUS_CSI>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_in: port@0 {
reg = <0>;
mipi_csi2_in_ov8865: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&ov8865_out_mipi_csi2>;
};
};
mipi_csi2_out: port@1 {
reg = <1>;
mipi_csi2_out_csi: endpoint {
remote-endpoint = <&csi_in_mipi_csi2>;
};
};
};
};
...
Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt
-16
View File
@@ -1,16 +0,0 @@
Samsung S5P/Exynos SoC series JPEG codec
Required properties:
- compatible : should be one of:
"samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg",
"samsung,exynos3250-jpeg", "samsung,exynos5420-jpeg",
"samsung,exynos5433-jpeg";
- reg : address and length of the JPEG codec IP register set;
- interrupts : specifies the JPEG codec IP interrupt;
- clock-names : should contain:
- "jpeg" for the core gate clock,
- "sclk" for the special clock (optional).
- clocks : should contain the clock specifier and clock ID list
matching entries in the clock-names property; from
the common clock bindings.
Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml
+1
View File
@@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
- aptina,mt9p006
- aptina,mt9p031
- aptina,mt9p031m
Documentation/devicetree/bindings/media/i2c/onnn,ar0521.yaml
+112
View File
@@ -0,0 +1,112 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/onnn,ar0521.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ON Semiconductor AR0521 MIPI CSI-2 sensor
maintainers:
- Krzysztof Hałasa <khalasa@piap.pl>
description: |-
The AR0521 is a raw CMOS image sensor with MIPI CSI-2 and
I2C-compatible control interface.
properties:
compatible:
const: onnn,ar0521
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: extclk
vaa-supply:
description:
Definition of the regulator used as analog (2.7 V) voltage supply.
vdd-supply:
description:
Definition of the regulator used as digital core (1.2 V) voltage supply.
vdd_io-supply:
description:
Definition of the regulator used as digital I/O (1.8 V) voltage supply.
reset-gpios:
description: reset GPIO, usually active low
maxItems: 1
port:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: |
Video output port.
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
bus-type:
const: 4
data-lanes:
anyOf:
- items:
- const: 1
- items:
- const: 1
- const: 2
- items:
- const: 1
- const: 2
- const: 3
- const: 4
required:
- compatible
- reg
- clocks
- clock-names
- vaa-supply
- vdd-supply
- vdd_io-supply
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
ar0521: camera-sensor@36 {
compatible = "onnn,ar0521";
reg = <0x36>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi_camera>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "extclk";
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
vaa-supply = <&reg_2p7v>;
vdd-supply = <&reg_1p2v>;
vdd_io-supply = <&reg_1p8v>;
port {
mipi_camera_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
Documentation/devicetree/bindings/media/i2c/ovti,ov5693.yaml
+124
View File
@@ -0,0 +1,124 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2022 Amarulasolutions
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/ovti,ov5693.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Omnivision OV5693 CMOS Sensor
maintainers:
- Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
description: |
The Omnivision OV5693 is a high performance, 1/4-inch, 5 megapixel, CMOS
image sensor that delivers 2592x1944 at 30fps. It provides full-frame,
sub-sampled, and windowed 10-bit MIPI images in various formats via the
Serial Camera Control Bus (SCCB) interface.
OV5693 is controlled via I2C and two-wire Serial Camera Control Bus (SCCB).
The sensor output is available via CSI-2 serial data output (up to 2-lane).
allOf:
- $ref: /schemas/media/video-interface-devices.yaml#
properties:
compatible:
const: ovti,ov5693
reg:
maxItems: 1
clocks:
description:
System input clock (aka XVCLK). From 6 to 27 MHz.
maxItems: 1
dovdd-supply:
description:
Digital I/O voltage supply, 1.8V.
avdd-supply:
description:
Analog voltage supply, 2.8V.
dvdd-supply:
description:
Digital core voltage supply, 1.2V.
reset-gpios:
description:
The phandle and specifier for the GPIO that controls sensor reset.
This corresponds to the hardware pin XSHUTDN which is physically
active low.
maxItems: 1
port:
description: MIPI CSI-2 transmitter port
$ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
link-frequencies: true
data-lanes:
minItems: 1
maxItems: 2
required:
- data-lanes
- link-frequencies
required:
- compatible
- reg
- clocks
- port
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/px30-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
ov5693: camera@36 {
compatible = "ovti,ov5693";
reg = <0x36>;
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cif_clkout_m0>;
clocks = <&cru SCLK_CIF_OUT>;
assigned-clocks = <&cru SCLK_CIF_OUT>;
assigned-clock-rates = <19200000>;
avdd-supply = <&vcc_1v8>;
dvdd-supply = <&vcc_1v2>;
dovdd-supply = <&vcc_2v8>;
rotation = <90>;
orientation = <0>;
port {
ucam_out: endpoint {
remote-endpoint = <&mipi_in_ucam>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <450000000>;
};
};
};
};
...
Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+36 -16
View File
@@ -17,20 +17,20 @@ description: |
About the Decoder Hardware Block Diagram, please check below:
+---------------------------------+------------------------------------+
| | |
| input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
| || | || |
+------------||-------------------+---------------------||-------------+
lat workqueue | core workqueue <parent>
-------------||-----------------------------------------||------------------
|| || <child>
\/ <----------------HW index-------------->\/
+------------------------------------------------------+
| enable/disable |
| clk power irq iommu |
| (lat/lat soc/core0/core1) |
+------------------------------------------------------+
+------------------------------------------------+-------------------------------------+
| | |
| input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
| || || | || |
+------------||-------------||-------------------+---------------------||--------------+
|| lat || | core workqueue <parent>
-------------||-------------||-------------------|---------------------||---------------
||<------------||----------------HW index---------------->|| <child>
\/ \/ \/
+-------------------------------------------------------------+
| enable/disable |
| clk power irq iommu |
| (lat/lat soc/core0/core1) |
+-------------------------------------------------------------+
As above, there are parent and child devices, child mean each hardware. The child device
controls the information of each hardware independent which include clk/power/irq.
@@ -45,11 +45,19 @@ description: |
For the smi common may not the same for each hardware, can't combine all hardware in one node,
or leading to iommu fault when access dram data.
Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
clock when lat start to work, don't have interrupt.
mt8195: lat soc HW + lat HW + core HW
mt8192: lat HW + core HW
properties:
compatible:
enum:
- mediatek,mt8192-vcodec-dec
- mediatek,mt8186-vcodec-dec
- mediatek,mt8195-vcodec-dec
reg:
maxItems: 1
@@ -87,7 +95,9 @@ patternProperties:
properties:
compatible:
const: mediatek,mtk-vcodec-lat
enum:
- mediatek,mtk-vcodec-lat
- mediatek,mtk-vcodec-lat-soc
reg:
maxItems: 1
@@ -125,7 +135,6 @@ patternProperties:
required:
- compatible
- reg
- interrupts
- iommus
- clocks
- clock-names
@@ -196,6 +205,17 @@ required:
- dma-ranges
- ranges
if:
properties:
compatible:
contains:
enum:
- mediatek,mtk-vcodec-lat
then:
required:
- interrupts
additionalProperties: false
examples:
Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
+6
View File
@@ -18,6 +18,7 @@ properties:
- enum:
- mediatek,mt2701-jpgenc
- mediatek,mt8183-jpgenc
- mediatek,mt8186-jpgenc
- const: mediatek,mtk-jpgenc
reg:
maxItems: 1
@@ -42,6 +43,11 @@ properties:
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
required:
- compatible
- reg
Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
+8 -3
View File
@@ -22,9 +22,14 @@ description: |-
properties:
compatible:
enum:
- fsl,imx7-mipi-csi2
- fsl,imx8mm-mipi-csi2
oneOf:
- enum:
- fsl,imx7-mipi-csi2
- fsl,imx8mm-mipi-csi2
- items:
- enum:
- fsl,imx8mp-mipi-csi2
- const: fsl,imx8mm-mipi-csi2
reg:
maxItems: 1
Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml
+7
View File
@@ -84,6 +84,13 @@ properties:
- const: vfe0
- const: vfe1
interconnects:
maxItems: 1
interconnect-names:
items:
- const: vfe-mem
iommus:
maxItems: 4
Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
+69
View File
@@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/rockchip,rk3568-vepu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Hantro G1 VPU encoders implemented on Rockchip SoCs
maintainers:
- Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
description:
Hantro G1 video encode-only accelerators present on Rockchip SoCs.
properties:
compatible:
enum:
- rockchip,rk3568-vepu
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: aclk
- const: hclk
power-domains:
maxItems: 1
iommus:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/rk3568-power.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
vepu: video-codec@fdee0000 {
compatible = "rockchip,rk3568-vepu";
reg = <0x0 0xfdee0000 0x0 0x800>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
clock-names = "aclk", "hclk";
iommus = <&vepu_mmu>;
power-domains = <&power RK3568_PD_RGA>;
};
};
Documentation/devicetree/bindings/media/rockchip-isp1.yaml
+21 -2
View File
@@ -84,8 +84,27 @@ properties:
minItems: 1
maxItems: 4
required:
- port@0
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: connection point for input on the parallel interface
properties:
bus-type:
enum: [5, 6]
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
required:
- bus-type
anyOf:
- required:
- port@0
- required:
- port@1
required:
- compatible
Documentation/devicetree/bindings/media/samsung,s5pv210-jpeg.yaml
+123
View File
@@ -0,0 +1,123 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/samsung,s5pv210-jpeg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S5PV210 and Exynos SoC JPEG codec
maintainers:
- Jacek Anaszewski <jacek.anaszewski@gmail.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Andrzej Pietrasiewicz <andrzejtp2010@gmail.com>
properties:
compatible:
enum:
- samsung,s5pv210-jpeg
- samsung,exynos3250-jpeg
- samsung,exynos4210-jpeg
- samsung,exynos4212-jpeg
- samsung,exynos5420-jpeg
- samsung,exynos5433-jpeg
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
interrupts:
maxItems: 1
iommus:
maxItems: 1
power-domains:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- interrupts
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,s5pv210-jpeg
- samsung,exynos4210-jpeg
- samsung,exynos4212-jpeg
- samsung,exynos5420-jpeg
then:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: jpeg
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos3250-jpeg
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: jpeg
- const: sclk
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5433-jpeg
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: pclk
- const: aclk
- const: aclk_xiu
- const: sclk
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
codec@15020000 {
compatible = "samsung,exynos5433-jpeg";
reg = <0x15020000 0x10000>;
interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
clocks = <&cmu_mscl CLK_PCLK_JPEG>,
<&cmu_mscl CLK_ACLK_JPEG>,
<&cmu_mscl CLK_ACLK_XIU_MSCLX>,
<&cmu_mscl CLK_SCLK_JPEG>;
iommus = <&sysmmu_jpeg>;
power-domains = <&pd_mscl>;
};
Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
+192
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@@ -0,0 +1,192 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
As a system controller, the Freescale i.MX8qm/qxp Control and Status
Registers(CSR) module represents a set of miscellaneous registers of a
specific subsystem. It may provide control and/or status report interfaces
to a mix of standalone hardware devices within that subsystem. One typical
use-case is for some other nodes to acquire a reference to the syscon node
by phandle, and the other typical use-case is that the operating system
should consider all subnodes of the CSR module as separate child devices.
properties:
$nodename:
pattern: "^syscon@[0-9a-f]+$"
compatible:
items:
- enum:
- fsl,imx8qxp-mipi-lvds-csr
- fsl,imx8qm-lvds-csr
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: ipg
patternProperties:
"^(ldb|phy|pxl2dpi)$":
type: object
description: The possible child devices of the CSR module.
required:
- compatible
- reg
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
const: fsl,imx8qxp-mipi-lvds-csr
then:
required:
- pxl2dpi
- ldb
- if:
properties:
compatible:
contains:
const: fsl,imx8qm-lvds-csr
then:
required:
- phy
- ldb
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
mipi_lvds_0_csr: syscon@56221000 {
compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
reg = <0x56221000 0x1000>;
clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
clock-names = "ipg";
mipi_lvds_0_pxl2dpi: pxl2dpi {
compatible = "fsl,imx8qxp-pxl2dpi";
fsl,sc-resource = <IMX_SC_R_MIPI_0>;
power-domains = <&pd IMX_SC_R_MIPI_0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
reg = <0>;
remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
};
mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
reg = <1>;
remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
};
mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
};
};
};
};
mipi_lvds_0_ldb: ldb {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8qxp-ldb";
clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
clock-names = "pixel", "bypass";
power-domains = <&pd IMX_SC_R_LVDS_0>;
channel@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phys = <&mipi_lvds_0_phy>;
phy-names = "lvds_phy";
port@0 {
reg = <0>;
mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
};
};
port@1 {
reg = <1>;
/* ... */
};
};
channel@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phys = <&mipi_lvds_0_phy>;
phy-names = "lvds_phy";
port@0 {
reg = <0>;
mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
};
};
port@1 {
reg = <1>;
/* ... */
};
};
};
};
mipi_lvds_0_phy: phy@56228300 {
compatible = "fsl,imx8qxp-mipi-dphy";
reg = <0x56228300 0x100>;
clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
clock-names = "phy_ref";
#phy-cells = <0>;
fsl,syscon = <&mipi_lvds_0_csr>;
power-domains = <&pd IMX_SC_R_MIPI_0>;
};
Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml
+104
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@@ -0,0 +1,104 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Adreno/Snapdragon HDMI phy
maintainers:
- Rob Clark <robdclark@gmail.com>
properties:
compatible:
enum:
- qcom,hdmi-phy-8660
- qcom,hdmi-phy-8960
- qcom,hdmi-phy-8974
- qcom,hdmi-phy-8084
reg:
maxItems: 2
reg-names:
items:
- const: hdmi_phy
- const: hdmi_pll
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
power-domains:
maxItems: 1
core-vdda-supply:
description: phandle to VDDA supply regulator
vddio-supply:
description: phandle to VDD I/O supply regulator
'#phy-cells':
const: 0
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,hdmi-phy-8660
- qcom,hdmi-phy-8960
then:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: slave_iface
vddio-supply: false
- if:
properties:
compatible:
contains:
enum:
- qcom,hdmi-phy-8084
- qcom,hdmi-phy-8974
then:
properties:
clocks:
maxItems: 2
clock-names:
items:
- const: iface
- const: alt_iface
required:
- compatible
- clocks
- reg
- reg-names
- '#phy-cells'
additionalProperties: false
examples:
- |
hdmi_phy: phy@4a00400 {
compatible = "qcom,hdmi-phy-8960";
reg-names = "hdmi_phy",
"hdmi_pll";
reg = <0x4a00400 0x60>,
<0x4a00500 0x100>;
#phy-cells = <0>;
power-domains = <&mmcc 1>;
clock-names = "slave_iface";
clocks = <&clk 21>;
core-vdda-supply = <&pm8921_hdmi_mvs>;
};
Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml
+85
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@@ -0,0 +1,85 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Adreno/Snapdragon QMP HDMI phy
maintainers:
- Rob Clark <robdclark@gmail.com>
properties:
compatible:
enum:
- qcom,hdmi-phy-8996
reg:
maxItems: 6
reg-names:
items:
- const: hdmi_pll
- const: hdmi_tx_l0
- const: hdmi_tx_l1
- const: hdmi_tx_l2
- const: hdmi_tx_l3
- const: hdmi_phy
clocks:
maxItems: 2
clock-names:
items:
- const: iface
- const: ref
power-domains:
maxItems: 1
vcca-supply:
description: phandle to VCCA supply regulator
vddio-supply:
description: phandle to VDD I/O supply regulator
'#phy-cells':
const: 0
required:
- compatible
- clocks
- clock-names
- reg
- reg-names
- '#phy-cells'
additionalProperties: false
examples:
- |
hdmi-phy@9a0600 {
compatible = "qcom,hdmi-phy-8996";
reg = <0x009a0600 0x1c4>,
<0x009a0a00 0x124>,
<0x009a0c00 0x124>,
<0x009a0e00 0x124>,
<0x009a1000 0x124>,
<0x009a1200 0x0c8>;
reg-names = "hdmi_pll",
"hdmi_tx_l0",
"hdmi_tx_l1",
"hdmi_tx_l2",
"hdmi_tx_l3",
"hdmi_phy";
clocks = <&mmcc 116>,
<&gcc 214>;
clock-names = "iface",
"ref";
#phy-cells = <0>;
vddio-supply = <&vreg_l12a_1p8>;
vcca-supply = <&vreg_l28a_0p925>;
};
Documentation/devicetree/bindings/phy/samsung,exynos-hdmi-phy.yaml
-1
View File
@@ -8,7 +8,6 @@ title: Samsung Exynos SoC HDMI PHY
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
-59
View File
@@ -1,59 +0,0 @@
Device tree binding for NVIDIA Tegra DPAUX pad controller
========================================================
The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins
which can be assigned to either the DPAUX channel or to an I2C
controller.
This document defines the device-specific binding for the DPAUX pad
controller. Refer to pinctrl-bindings.txt in this directory for generic
information about pin controller device tree bindings. Please refer to
the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more
details on the DPAUX binding.
Pin muxing:
-----------
Child nodes contain the pinmux configurations following the conventions
from the pinctrl-bindings.txt document.
Since only three configurations are possible, only three child nodes are
needed to describe the pin mux'ing options for the DPAUX pads.
Furthermore, given that the pad functions are only applicable to a
single set of pads, the child nodes only need to describe the pad group
the functions are being applied to rather than the individual pads.
Required properties:
- groups: Must be "dpaux-io"
- function: Must be either "aux", "i2c" or "off".
Example:
--------
dpaux@545c0000 {
...
state_dpaux_aux: pinmux-aux {
groups = "dpaux-io";
function = "aux";
};
state_dpaux_i2c: pinmux-i2c {
groups = "dpaux-io";
function = "i2c";
};
state_dpaux_off: pinmux-off {
groups = "dpaux-io";
function = "off";
};
};
...
i2c@7000d100 {
...
pinctrl-0 = <&state_dpaux_i2c>;
pinctrl-1 = <&state_dpaux_off>;
pinctrl-names = "default", "idle";
};
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
View File
@@ -350,6 +350,8 @@ patternProperties:
description: Embedded Artists AB
"^ebang,.*":
description: Zhejiang Ebang Communication Co., Ltd
"^ebbg,.*":
description: EBBG
"^ebs-systart,.*":
description: EBS-SYSTART GmbH
"^ebv,.*":
Documentation/driver-api/aperture.rst
+13
View File
@@ -0,0 +1,13 @@
.. SPDX-License-Identifier: GPL-2.0
Managing Ownership of the Framebuffer Aperture
==============================================
.. kernel-doc:: drivers/video/aperture.c
:doc: overview
.. kernel-doc:: include/linux/aperture.h
:internal:
.. kernel-doc:: drivers/video/aperture.c
:export:
Documentation/driver-api/index.rst
+1
View File
@@ -27,6 +27,7 @@ available subsections can be seen below.
component
message-based
infiniband
aperture
frame-buffer
regulator
reset
Documentation/driver-api/media/mc-core.rst
+3 -2
View File
@@ -186,8 +186,9 @@ is required and the graph structure can be freed normally.
Helper functions can be used to find a link between two given pads, or a pad
connected to another pad through an enabled link
:c:func:`media_entity_find_link()` and
:c:func:`media_entity_remote_pad()`.
(:c:func:`media_entity_find_link()`, :c:func:`media_pad_remote_pad_first()`,
:c:func:`media_entity_remote_source_pad_unique()` and
:c:func:`media_pad_remote_pad_unique()`).
Use count and power handling
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Documentation/driver-api/media/v4l2-subdev.rst
+6
View File
@@ -243,6 +243,12 @@ notifier callback is called. After all subdevices have been located the
.complete() callback is called. When a subdevice is removed from the
system the .unbind() method is called. All three callbacks are optional.
Drivers can store any type of custom data in their driver-specific
:c:type:`v4l2_async_subdev` wrapper. If any of that data requires special
handling when the structure is freed, drivers must implement the ``.destroy()``
notifier callback. The framework will call it right before freeing the
:c:type:`v4l2_async_subdev`.
Calling subdev operations
~~~~~~~~~~~~~~~~~~~~~~~~~
Documentation/gpu/amdgpu/amdgpu-glossary.rst
+1 -1
View File
@@ -75,7 +75,7 @@ we have a dedicated glossary for Display Core at
PSP
Platform Security Processor
RCL
RLC
RunList Controller
SDMA
Documentation/gpu/amdgpu/thermal.rst
+41
View File
@@ -63,3 +63,44 @@ gpu_metrics
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
:doc: gpu_metrics
GFXOFF
======
GFXOFF is a feature found in most recent GPUs that saves power at runtime. The
card's RLC (RunList Controller) firmware powers off the gfx engine
dynamically when there is no workload on gfx or compute pipes. GFXOFF is on by
default on supported GPUs.
Userspace can interact with GFXOFF through a debugfs interface:
``amdgpu_gfxoff``
-----------------
Use it to enable/disable GFXOFF, and to check if it's current enabled/disabled::
$ xxd -l1 -p /sys/kernel/debug/dri/0/amdgpu_gfxoff
01
- Write 0 to disable it, and 1 to enable it.
- Read 0 means it's disabled, 1 it's enabled.
If it's enabled, that means that the GPU is free to enter into GFXOFF mode as
needed. Disabled means that it will never enter GFXOFF mode.
``amdgpu_gfxoff_status``
------------------------
Read it to check current GFXOFF's status of a GPU::
$ xxd -l1 -p /sys/kernel/debug/dri/0/amdgpu_gfxoff_status
02
- 0: GPU is in GFXOFF state, the gfx engine is powered down.
- 1: Transition out of GFXOFF state
- 2: Not in GFXOFF state
- 3: Transition into GFXOFF state
If GFXOFF is enabled, the value will be transitioning around [0, 3], always
getting into 0 when possible. When it's disabled, it's always at 2. Returns
``-EINVAL`` if it's not supported.
Documentation/gpu/drm-internals.rst
+32
View File
@@ -207,6 +207,38 @@ Utilities
:internal:
Unit testing
============
KUnit
-----
KUnit (Kernel unit testing framework) provides a common framework for unit tests
within the Linux kernel.
This section covers the specifics for the DRM subsystem. For general information
about KUnit, please refer to Documentation/dev-tools/kunit/start.rst.
How to run the tests?
~~~~~~~~~~~~~~~~~~~~~
In order to facilitate running the test suite, a configuration file is present
in ``drivers/gpu/drm/tests/.kunitconfig``. It can be used by ``kunit.py`` as
follows:
.. code-block:: bash
$ ./tools/testing/kunit/kunit.py run --kunitconfig=drivers/gpu/drm/tests \
--kconfig_add CONFIG_VIRTIO_UML=y \
--kconfig_add CONFIG_UML_PCI_OVER_VIRTIO=y
.. note::
The configuration included in ``.kunitconfig`` should be as generic as
possible.
``CONFIG_VIRTIO_UML`` and ``CONFIG_UML_PCI_OVER_VIRTIO`` are not
included in it because they are only required for User Mode Linux.
Legacy Support Code
===================
Documentation/gpu/drm-usage-stats.rst
+21
View File
@@ -105,6 +105,27 @@ object belong to this client, in the respective memory region.
Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB'
indicating kibi- or mebi-bytes.
- drm-cycles-<str> <uint>
Engine identifier string must be the same as the one specified in the
drm-engine-<str> tag and shall contain the number of busy cycles for the given
engine.
Values are not required to be constantly monotonic if it makes the driver
implementation easier, but are required to catch up with the previously reported
larger value within a reasonable period. Upon observing a value lower than what
was previously read, userspace is expected to stay with that larger previous
value until a monotonic update is seen.
- drm-maxfreq-<str> <uint> [Hz|MHz|KHz]
Engine identifier string must be the same as the one specified in the
drm-engine-<str> tag and shall contain the maximum frequency for the given
engine. Taken together with drm-cycles-<str>, this can be used to calculate
percentage utilization of the engine, whereas drm-engine-<str> only reflects
time active without considering what frequency the engine is operating as a
percentage of it's maximum frequency.
===============================
Driver specific implementations
===============================
Documentation/gpu/i915.rst
+12
View File
@@ -246,6 +246,18 @@ Display State Buffer
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
:internal:
GT Programming
==============
Multicast/Replicated (MCR) Registers
------------------------------------
.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
:doc: GT Multicast/Replicated (MCR) Register Support
.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
:internal:
Memory Management and Command Submission
========================================
Documentation/gpu/rfc/i915_small_bar.h
+189
View File
@@ -0,0 +1,189 @@
/**
* struct __drm_i915_memory_region_info - Describes one region as known to the
* driver.
*
* Note this is using both struct drm_i915_query_item and struct drm_i915_query.
* For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
* at &drm_i915_query_item.query_id.
*/
struct __drm_i915_memory_region_info {
/** @region: The class:instance pair encoding */
struct drm_i915_gem_memory_class_instance region;
/** @rsvd0: MBZ */
__u32 rsvd0;
/**
* @probed_size: Memory probed by the driver
*
* Note that it should not be possible to ever encounter a zero value
* here, also note that no current region type will ever return -1 here.
* Although for future region types, this might be a possibility. The
* same applies to the other size fields.
*/
__u64 probed_size;
/**
* @unallocated_size: Estimate of memory remaining
*
* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting.
* Without this (or if this is an older kernel) the value here will
* always equal the @probed_size. Note this is only currently tracked
* for I915_MEMORY_CLASS_DEVICE regions (for other types the value here
* will always equal the @probed_size).
*/
__u64 unallocated_size;
union {
/** @rsvd1: MBZ */
__u64 rsvd1[8];
struct {
/**
* @probed_cpu_visible_size: Memory probed by the driver
* that is CPU accessible.
*
* This will be always be <= @probed_size, and the
* remainder (if there is any) will not be CPU
* accessible.
*
* On systems without small BAR, the @probed_size will
* always equal the @probed_cpu_visible_size, since all
* of it will be CPU accessible.
*
* Note this is only tracked for
* I915_MEMORY_CLASS_DEVICE regions (for other types the
* value here will always equal the @probed_size).
*
* Note that if the value returned here is zero, then
* this must be an old kernel which lacks the relevant
* small-bar uAPI support (including
* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on
* such systems we should never actually end up with a
* small BAR configuration, assuming we are able to load
* the kernel module. Hence it should be safe to treat
* this the same as when @probed_cpu_visible_size ==
* @probed_size.
*/
__u64 probed_cpu_visible_size;
/**
* @unallocated_cpu_visible_size: Estimate of CPU
* visible memory remaining
*
* Note this is only tracked for
* I915_MEMORY_CLASS_DEVICE regions (for other types the
* value here will always equal the
* @probed_cpu_visible_size).
*
* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
* accounting. Without this the value here will always
* equal the @probed_cpu_visible_size. Note this is only
* currently tracked for I915_MEMORY_CLASS_DEVICE
* regions (for other types the value here will also
* always equal the @probed_cpu_visible_size).
*
* If this is an older kernel the value here will be
* zero, see also @probed_cpu_visible_size.
*/
__u64 unallocated_cpu_visible_size;
};
};
};
/**
* struct __drm_i915_gem_create_ext - Existing gem_create behaviour, with added
* extension support using struct i915_user_extension.
*
* Note that new buffer flags should be added here, at least for the stuff that
* is immutable. Previously we would have two ioctls, one to create the object
* with gem_create, and another to apply various parameters, however this
* creates some ambiguity for the params which are considered immutable. Also in
* general we're phasing out the various SET/GET ioctls.
*/
struct __drm_i915_gem_create_ext {
/**
* @size: Requested size for the object.
*
* The (page-aligned) allocated size for the object will be returned.
*
* Note that for some devices we have might have further minimum
* page-size restrictions (larger than 4K), like for device local-memory.
* However in general the final size here should always reflect any
* rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
* extension to place the object in device local-memory. The kernel will
* always select the largest minimum page-size for the set of possible
* placements as the value to use when rounding up the @size.
*/
__u64 size;
/**
* @handle: Returned handle for the object.
*
* Object handles are nonzero.
*/
__u32 handle;
/**
* @flags: Optional flags.
*
* Supported values:
*
* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that
* the object will need to be accessed via the CPU.
*
* Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only
* strictly required on configurations where some subset of the device
* memory is directly visible/mappable through the CPU (which we also
* call small BAR), like on some DG2+ systems. Note that this is quite
* undesirable, but due to various factors like the client CPU, BIOS etc
* it's something we can expect to see in the wild. See
* &__drm_i915_memory_region_info.probed_cpu_visible_size for how to
* determine if this system applies.
*
* Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to
* ensure the kernel can always spill the allocation to system memory,
* if the object can't be allocated in the mappable part of
* I915_MEMORY_CLASS_DEVICE.
*
* Also note that since the kernel only supports flat-CCS on objects
* that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore
* don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with
* flat-CCS.
*
* Without this hint, the kernel will assume that non-mappable
* I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the
* kernel can still migrate the object to the mappable part, as a last
* resort, if userspace ever CPU faults this object, but this might be
* expensive, and so ideally should be avoided.
*
* On older kernels which lack the relevant small-bar uAPI support (see
* also &__drm_i915_memory_region_info.probed_cpu_visible_size),
* usage of the flag will result in an error, but it should NEVER be
* possible to end up with a small BAR configuration, assuming we can
* also successfully load the i915 kernel module. In such cases the
* entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as
* such there are zero restrictions on where the object can be placed.
*/
#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)
__u32 flags;
/**
* @extensions: The chain of extensions to apply to this object.
*
* This will be useful in the future when we need to support several
* different extensions, and we need to apply more than one when
* creating the object. See struct i915_user_extension.
*
* If we don't supply any extensions then we get the same old gem_create
* behaviour.
*
* For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
* struct drm_i915_gem_create_ext_memory_regions.
*
* For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
* struct drm_i915_gem_create_ext_protected_content.
*/
#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
__u64 extensions;
};
Documentation/gpu/rfc/i915_small_bar.rst
+47
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==========================
I915 Small BAR RFC Section
==========================
Starting from DG2 we will have resizable BAR support for device local-memory(i.e
I915_MEMORY_CLASS_DEVICE), but in some cases the final BAR size might still be
smaller than the total probed_size. In such cases, only some subset of
I915_MEMORY_CLASS_DEVICE will be CPU accessible(for example the first 256M),
while the remainder is only accessible via the GPU.
I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS flag
----------------------------------------------
New gem_create_ext flag to tell the kernel that a BO will require CPU access.
This becomes important when placing an object in I915_MEMORY_CLASS_DEVICE, where
underneath the device has a small BAR, meaning only some portion of it is CPU
accessible. Without this flag the kernel will assume that CPU access is not
required, and prioritize using the non-CPU visible portion of
I915_MEMORY_CLASS_DEVICE.
.. kernel-doc:: Documentation/gpu/rfc/i915_small_bar.h
:functions: __drm_i915_gem_create_ext
probed_cpu_visible_size attribute
---------------------------------
New struct__drm_i915_memory_region attribute which returns the total size of the
CPU accessible portion, for the particular region. This should only be
applicable for I915_MEMORY_CLASS_DEVICE. We also report the
unallocated_cpu_visible_size, alongside the unallocated_size.
Vulkan will need this as part of creating a separate VkMemoryHeap with the
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT set, to represent the CPU visible portion,
where the total size of the heap needs to be known. It also wants to be able to
give a rough estimate of how memory can potentially be allocated.
.. kernel-doc:: Documentation/gpu/rfc/i915_small_bar.h
:functions: __drm_i915_memory_region_info
Error Capture restrictions
--------------------------
With error capture we have two new restrictions:
1) Error capture is best effort on small BAR systems; if the pages are not
CPU accessible, at the time of capture, then the kernel is free to skip
trying to capture them.
2) On discrete and newer integrated platforms we now reject error capture
on recoverable contexts. In the future the kernel may want to blit during
error capture, when for example something is not currently CPU accessible.
Documentation/gpu/rfc/i915_vm_bind.h
+291
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@@ -0,0 +1,291 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
/**
* DOC: I915_PARAM_VM_BIND_VERSION
*
* VM_BIND feature version supported.
* See typedef drm_i915_getparam_t param.
*
* Specifies the VM_BIND feature version supported.
* The following versions of VM_BIND have been defined:
*
* 0: No VM_BIND support.
*
* 1: In VM_UNBIND calls, the UMD must specify the exact mappings created
* previously with VM_BIND, the ioctl will not support unbinding multiple
* mappings or splitting them. Similarly, VM_BIND calls will not replace
* any existing mappings.
*
* 2: The restrictions on unbinding partial or multiple mappings is
* lifted, Similarly, binding will replace any mappings in the given range.
*
* See struct drm_i915_gem_vm_bind and struct drm_i915_gem_vm_unbind.
*/
#define I915_PARAM_VM_BIND_VERSION 57
/**
* DOC: I915_VM_CREATE_FLAGS_USE_VM_BIND
*
* Flag to opt-in for VM_BIND mode of binding during VM creation.
* See struct drm_i915_gem_vm_control flags.
*
* The older execbuf2 ioctl will not support VM_BIND mode of operation.
* For VM_BIND mode, we have new execbuf3 ioctl which will not accept any
* execlist (See struct drm_i915_gem_execbuffer3 for more details).
*/
#define I915_VM_CREATE_FLAGS_USE_VM_BIND (1 << 0)
/* VM_BIND related ioctls */
#define DRM_I915_GEM_VM_BIND 0x3d
#define DRM_I915_GEM_VM_UNBIND 0x3e
#define DRM_I915_GEM_EXECBUFFER3 0x3f
#define DRM_IOCTL_I915_GEM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_BIND, struct drm_i915_gem_vm_bind)
#define DRM_IOCTL_I915_GEM_VM_UNBIND DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_UNBIND, struct drm_i915_gem_vm_bind)
#define DRM_IOCTL_I915_GEM_EXECBUFFER3 DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER3, struct drm_i915_gem_execbuffer3)
/**
* struct drm_i915_gem_timeline_fence - An input or output timeline fence.
*
* The operation will wait for input fence to signal.
*
* The returned output fence will be signaled after the completion of the
* operation.
*/
struct drm_i915_gem_timeline_fence {
/** @handle: User's handle for a drm_syncobj to wait on or signal. */
__u32 handle;
/**
* @flags: Supported flags are:
*
* I915_TIMELINE_FENCE_WAIT:
* Wait for the input fence before the operation.
*
* I915_TIMELINE_FENCE_SIGNAL:
* Return operation completion fence as output.
*/
__u32 flags;
#define I915_TIMELINE_FENCE_WAIT (1 << 0)
#define I915_TIMELINE_FENCE_SIGNAL (1 << 1)
#define __I915_TIMELINE_FENCE_UNKNOWN_FLAGS (-(I915_TIMELINE_FENCE_SIGNAL << 1))
/**
* @value: A point in the timeline.
* Value must be 0 for a binary drm_syncobj. A Value of 0 for a
* timeline drm_syncobj is invalid as it turns a drm_syncobj into a
* binary one.
*/
__u64 value;
};
/**
* struct drm_i915_gem_vm_bind - VA to object mapping to bind.
*
* This structure is passed to VM_BIND ioctl and specifies the mapping of GPU
* virtual address (VA) range to the section of an object that should be bound
* in the device page table of the specified address space (VM).
* The VA range specified must be unique (ie., not currently bound) and can
* be mapped to whole object or a section of the object (partial binding).
* Multiple VA mappings can be created to the same section of the object
* (aliasing).
*
* The @start, @offset and @length must be 4K page aligned. However the DG2
* and XEHPSDV has 64K page size for device local memory and has compact page
* table. On those platforms, for binding device local-memory objects, the
* @start, @offset and @length must be 64K aligned. Also, UMDs should not mix
* the local memory 64K page and the system memory 4K page bindings in the same
* 2M range.
*
* Error code -EINVAL will be returned if @start, @offset and @length are not
* properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code
* -ENOSPC will be returned if the VA range specified can't be reserved.
*
* VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently
* are not ordered. Furthermore, parts of the VM_BIND operation can be done
* asynchronously, if valid @fence is specified.
*/
struct drm_i915_gem_vm_bind {
/** @vm_id: VM (address space) id to bind */
__u32 vm_id;
/** @handle: Object handle */
__u32 handle;
/** @start: Virtual Address start to bind */
__u64 start;
/** @offset: Offset in object to bind */
__u64 offset;
/** @length: Length of mapping to bind */
__u64 length;
/**
* @flags: Supported flags are:
*
* I915_GEM_VM_BIND_CAPTURE:
* Capture this mapping in the dump upon GPU error.
*
* Note that @fence carries its own flags.
*/
__u64 flags;
#define I915_GEM_VM_BIND_CAPTURE (1 << 0)
/**
* @fence: Timeline fence for bind completion signaling.
*
* Timeline fence is of format struct drm_i915_gem_timeline_fence.
*
* It is an out fence, hence using I915_TIMELINE_FENCE_WAIT flag
* is invalid, and an error will be returned.
*
* If I915_TIMELINE_FENCE_SIGNAL flag is not set, then out fence
* is not requested and binding is completed synchronously.
*/
struct drm_i915_gem_timeline_fence fence;
/**
* @extensions: Zero-terminated chain of extensions.
*
* For future extensions. See struct i915_user_extension.
*/
__u64 extensions;
};
/**
* struct drm_i915_gem_vm_unbind - VA to object mapping to unbind.
*
* This structure is passed to VM_UNBIND ioctl and specifies the GPU virtual
* address (VA) range that should be unbound from the device page table of the
* specified address space (VM). VM_UNBIND will force unbind the specified
* range from device page table without waiting for any GPU job to complete.
* It is UMDs responsibility to ensure the mapping is no longer in use before
* calling VM_UNBIND.
*
* If the specified mapping is not found, the ioctl will simply return without
* any error.
*
* VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently
* are not ordered. Furthermore, parts of the VM_UNBIND operation can be done
* asynchronously, if valid @fence is specified.
*/
struct drm_i915_gem_vm_unbind {
/** @vm_id: VM (address space) id to bind */
__u32 vm_id;
/** @rsvd: Reserved, MBZ */
__u32 rsvd;
/** @start: Virtual Address start to unbind */
__u64 start;
/** @length: Length of mapping to unbind */
__u64 length;
/**
* @flags: Currently reserved, MBZ.
*
* Note that @fence carries its own flags.
*/
__u64 flags;
/**
* @fence: Timeline fence for unbind completion signaling.
*
* Timeline fence is of format struct drm_i915_gem_timeline_fence.
*
* It is an out fence, hence using I915_TIMELINE_FENCE_WAIT flag
* is invalid, and an error will be returned.
*
* If I915_TIMELINE_FENCE_SIGNAL flag is not set, then out fence
* is not requested and unbinding is completed synchronously.
*/
struct drm_i915_gem_timeline_fence fence;
/**
* @extensions: Zero-terminated chain of extensions.
*
* For future extensions. See struct i915_user_extension.
*/
__u64 extensions;
};
/**
* struct drm_i915_gem_execbuffer3 - Structure for DRM_I915_GEM_EXECBUFFER3
* ioctl.
*
* DRM_I915_GEM_EXECBUFFER3 ioctl only works in VM_BIND mode and VM_BIND mode
* only works with this ioctl for submission.
* See I915_VM_CREATE_FLAGS_USE_VM_BIND.
*/
struct drm_i915_gem_execbuffer3 {
/**
* @ctx_id: Context id
*
* Only contexts with user engine map are allowed.
*/
__u32 ctx_id;
/**
* @engine_idx: Engine index
*
* An index in the user engine map of the context specified by @ctx_id.
*/
__u32 engine_idx;
/**
* @batch_address: Batch gpu virtual address/es.
*
* For normal submission, it is the gpu virtual address of the batch
* buffer. For parallel submission, it is a pointer to an array of
* batch buffer gpu virtual addresses with array size equal to the
* number of (parallel) engines involved in that submission (See
* struct i915_context_engines_parallel_submit).
*/
__u64 batch_address;
/** @flags: Currently reserved, MBZ */
__u64 flags;
/** @rsvd1: Reserved, MBZ */
__u32 rsvd1;
/** @fence_count: Number of fences in @timeline_fences array. */
__u32 fence_count;
/**
* @timeline_fences: Pointer to an array of timeline fences.
*
* Timeline fences are of format struct drm_i915_gem_timeline_fence.
*/
__u64 timeline_fences;
/** @rsvd2: Reserved, MBZ */
__u64 rsvd2;
/**
* @extensions: Zero-terminated chain of extensions.
*
* For future extensions. See struct i915_user_extension.
*/
__u64 extensions;
};
/**
* struct drm_i915_gem_create_ext_vm_private - Extension to make the object
* private to the specified VM.
*
* See struct drm_i915_gem_create_ext.
*/
struct drm_i915_gem_create_ext_vm_private {
#define I915_GEM_CREATE_EXT_VM_PRIVATE 2
/** @base: Extension link. See struct i915_user_extension. */
struct i915_user_extension base;
/** @vm_id: Id of the VM to which the object is private */
__u32 vm_id;
};
Documentation/gpu/rfc/i915_vm_bind.rst
+245
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@@ -0,0 +1,245 @@
==========================================
I915 VM_BIND feature design and use cases
==========================================
VM_BIND feature
================
DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM buffer
objects (BOs) or sections of a BOs at specified GPU virtual addresses on a
specified address space (VM). These mappings (also referred to as persistent
mappings) will be persistent across multiple GPU submissions (execbuf calls)
issued by the UMD, without user having to provide a list of all required
mappings during each submission (as required by older execbuf mode).
The VM_BIND/UNBIND calls allow UMDs to request a timeline out fence for
signaling the completion of bind/unbind operation.
VM_BIND feature is advertised to user via I915_PARAM_VM_BIND_VERSION.
User has to opt-in for VM_BIND mode of binding for an address space (VM)
during VM creation time via I915_VM_CREATE_FLAGS_USE_VM_BIND extension.
VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently are
not ordered. Furthermore, parts of the VM_BIND/UNBIND operations can be done
asynchronously, when valid out fence is specified.
VM_BIND features include:
* Multiple Virtual Address (VA) mappings can map to the same physical pages
of an object (aliasing).
* VA mapping can map to a partial section of the BO (partial binding).
* Support capture of persistent mappings in the dump upon GPU error.
* Support for userptr gem objects (no special uapi is required for this).
TLB flush consideration
------------------------
The i915 driver flushes the TLB for each submission and when an object's
pages are released. The VM_BIND/UNBIND operation will not do any additional
TLB flush. Any VM_BIND mapping added will be in the working set for subsequent
submissions on that VM and will not be in the working set for currently running
batches (which would require additional TLB flushes, which is not supported).
Execbuf ioctl in VM_BIND mode
-------------------------------
A VM in VM_BIND mode will not support older execbuf mode of binding.
The execbuf ioctl handling in VM_BIND mode differs significantly from the
older execbuf2 ioctl (See struct drm_i915_gem_execbuffer2).
Hence, a new execbuf3 ioctl has been added to support VM_BIND mode. (See
struct drm_i915_gem_execbuffer3). The execbuf3 ioctl will not accept any
execlist. Hence, no support for implicit sync. It is expected that the below
work will be able to support requirements of object dependency setting in all
use cases:
"dma-buf: Add an API for exporting sync files"
(https://lwn.net/Articles/859290/)
The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
works with execbuf3 ioctl for submission. All BOs mapped on that VM (through
VM_BIND call) at the time of execbuf3 call are deemed required for that
submission.
The execbuf3 ioctl directly specifies the batch addresses instead of as
object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
support many of the older features like in/out/submit fences, fence array,
default gem context and many more (See struct drm_i915_gem_execbuffer3).
In VM_BIND mode, VA allocation is completely managed by the user instead of
the i915 driver. Hence all VA assignment, eviction are not applicable in
VM_BIND mode. Also, for determining object activeness, VM_BIND mode will not
be using the i915_vma active reference tracking. It will instead use dma-resv
object for that (See `VM_BIND dma_resv usage`_).
So, a lot of existing code supporting execbuf2 ioctl, like relocations, VA
evictions, vma lookup table, implicit sync, vma active reference tracking etc.,
are not applicable for execbuf3 ioctl. Hence, all execbuf3 specific handling
should be in a separate file and only functionalities common to these ioctls
can be the shared code where possible.
VM_PRIVATE objects
-------------------
By default, BOs can be mapped on multiple VMs and can also be dma-buf
exported. Hence these BOs are referred to as Shared BOs.
During each execbuf submission, the request fence must be added to the
dma-resv fence list of all shared BOs mapped on the VM.
VM_BIND feature introduces an optimization where user can create BO which
is private to a specified VM via I915_GEM_CREATE_EXT_VM_PRIVATE flag during
BO creation. Unlike Shared BOs, these VM private BOs can only be mapped on
the VM they are private to and can't be dma-buf exported.
All private BOs of a VM share the dma-resv object. Hence during each execbuf
submission, they need only one dma-resv fence list updated. Thus, the fast
path (where required mappings are already bound) submission latency is O(1)
w.r.t the number of VM private BOs.
VM_BIND locking hirarchy
-------------------------
The locking design here supports the older (execlist based) execbuf mode, the
newer VM_BIND mode, the VM_BIND mode with GPU page faults and possible future
system allocator support (See `Shared Virtual Memory (SVM) support`_).
The older execbuf mode and the newer VM_BIND mode without page faults manages
residency of backing storage using dma_fence. The VM_BIND mode with page faults
and the system allocator support do not use any dma_fence at all.
VM_BIND locking order is as below.
1) Lock-A: A vm_bind mutex will protect vm_bind lists. This lock is taken in
vm_bind/vm_unbind ioctl calls, in the execbuf path and while releasing the
mapping.
In future, when GPU page faults are supported, we can potentially use a
rwsem instead, so that multiple page fault handlers can take the read side
lock to lookup the mapping and hence can run in parallel.
The older execbuf mode of binding do not need this lock.
2) Lock-B: The object's dma-resv lock will protect i915_vma state and needs to
be held while binding/unbinding a vma in the async worker and while updating
dma-resv fence list of an object. Note that private BOs of a VM will all
share a dma-resv object.
The future system allocator support will use the HMM prescribed locking
instead.
3) Lock-C: Spinlock/s to protect some of the VM's lists like the list of
invalidated vmas (due to eviction and userptr invalidation) etc.
When GPU page faults are supported, the execbuf path do not take any of these
locks. There we will simply smash the new batch buffer address into the ring and
then tell the scheduler run that. The lock taking only happens from the page
fault handler, where we take lock-A in read mode, whichever lock-B we need to
find the backing storage (dma_resv lock for gem objects, and hmm/core mm for
system allocator) and some additional locks (lock-D) for taking care of page
table races. Page fault mode should not need to ever manipulate the vm lists,
so won't ever need lock-C.
VM_BIND LRU handling
---------------------
We need to ensure VM_BIND mapped objects are properly LRU tagged to avoid
performance degradation. We will also need support for bulk LRU movement of
VM_BIND objects to avoid additional latencies in execbuf path.
The page table pages are similar to VM_BIND mapped objects (See
`Evictable page table allocations`_) and are maintained per VM and needs to
be pinned in memory when VM is made active (ie., upon an execbuf call with
that VM). So, bulk LRU movement of page table pages is also needed.
VM_BIND dma_resv usage
-----------------------
Fences needs to be added to all VM_BIND mapped objects. During each execbuf
submission, they are added with DMA_RESV_USAGE_BOOKKEEP usage to prevent
over sync (See enum dma_resv_usage). One can override it with either
DMA_RESV_USAGE_READ or DMA_RESV_USAGE_WRITE usage during explicit object
dependency setting.
Note that DRM_I915_GEM_WAIT and DRM_I915_GEM_BUSY ioctls do not check for
DMA_RESV_USAGE_BOOKKEEP usage and hence should not be used for end of batch
check. Instead, the execbuf3 out fence should be used for end of batch check
(See struct drm_i915_gem_execbuffer3).
Also, in VM_BIND mode, use dma-resv apis for determining object activeness
(See dma_resv_test_signaled() and dma_resv_wait_timeout()) and do not use the
older i915_vma active reference tracking which is deprecated. This should be
easier to get it working with the current TTM backend.
Mesa use case
--------------
VM_BIND can potentially reduce the CPU overhead in Mesa (both Vulkan and Iris),
hence improving performance of CPU-bound applications. It also allows us to
implement Vulkan's Sparse Resources. With increasing GPU hardware performance,
reducing CPU overhead becomes more impactful.
Other VM_BIND use cases
========================
Long running Compute contexts
------------------------------
Usage of dma-fence expects that they complete in reasonable amount of time.
Compute on the other hand can be long running. Hence it is appropriate for
compute to use user/memory fence (See `User/Memory Fence`_) and dma-fence usage
must be limited to in-kernel consumption only.
Where GPU page faults are not available, kernel driver upon buffer invalidation
will initiate a suspend (preemption) of long running context, finish the
invalidation, revalidate the BO and then resume the compute context. This is
done by having a per-context preempt fence which is enabled when someone tries
to wait on it and triggers the context preemption.
User/Memory Fence
~~~~~~~~~~~~~~~~~~
User/Memory fence is a <address, value> pair. To signal the user fence, the
specified value will be written at the specified virtual address and wakeup the
waiting process. User fence can be signaled either by the GPU or kernel async
worker (like upon bind completion). User can wait on a user fence with a new
user fence wait ioctl.
Here is some prior work on this:
https://patchwork.freedesktop.org/patch/349417/
Low Latency Submission
~~~~~~~~~~~~~~~~~~~~~~~
Allows compute UMD to directly submit GPU jobs instead of through execbuf
ioctl. This is made possible by VM_BIND is not being synchronized against
execbuf. VM_BIND allows bind/unbind of mappings required for the directly
submitted jobs.
Debugger
---------
With debug event interface user space process (debugger) is able to keep track
of and act upon resources created by another process (debugged) and attached
to GPU via vm_bind interface.
GPU page faults
----------------
GPU page faults when supported (in future), will only be supported in the
VM_BIND mode. While both the older execbuf mode and the newer VM_BIND mode of
binding will require using dma-fence to ensure residency, the GPU page faults
mode when supported, will not use any dma-fence as residency is purely managed
by installing and removing/invalidating page table entries.
Page level hints settings
--------------------------
VM_BIND allows any hints setting per mapping instead of per BO. Possible hints
include placement and atomicity. Sub-BO level placement hint will be even more
relevant with upcoming GPU on-demand page fault support.
Page level Cache/CLOS settings
-------------------------------
VM_BIND allows cache/CLOS settings per mapping instead of per BO.
Evictable page table allocations
---------------------------------
Make pagetable allocations evictable and manage them similar to VM_BIND
mapped objects. Page table pages are similar to persistent mappings of a
VM (difference here are that the page table pages will not have an i915_vma
structure and after swapping pages back in, parent page link needs to be
updated).
Shared Virtual Memory (SVM) support
------------------------------------
VM_BIND interface can be used to map system memory directly (without gem BO
abstraction) using the HMM interface. SVM is only supported with GPU page
faults enabled.
VM_BIND UAPI
=============
.. kernel-doc:: Documentation/gpu/rfc/i915_vm_bind.h
Documentation/gpu/rfc/index.rst
+8
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@@ -23,3 +23,11 @@ host such documentation:
.. toctree::
i915_scheduler.rst
.. toctree::
i915_small_bar.rst
.. toctree::
i915_vm_bind.rst
Documentation/gpu/todo.rst
+11
View File
@@ -617,6 +617,17 @@ Contact: Javier Martinez Canillas <javierm@redhat.com>
Level: Intermediate
Convert Kernel Selftests (kselftest) to KUnit tests when appropriate
--------------------------------------------------------------------
Many of the `Kselftest <https://www.kernel.org/doc/html/latest/dev-tools/kselftest.html>`_
tests in DRM could be converted to Kunit tests instead, since that framework
is more suitable for unit testing.
Contact: Javier Martinez Canillas <javierm@redhat.com>
Level: Starter
Enable trinity for DRM
----------------------
Documentation/gpu/vkms.rst
-6
View File
@@ -102,12 +102,6 @@ Debugging:
- kms_plane: some test cases are failing due to timeout on capturing CRC;
- kms_flip: when running test cases in sequence, some successful individual
test cases are failing randomly; when individually, some successful test
cases display in the log the following error::
[drm:vkms_prepare_fb [vkms]] ERROR vmap failed: -4
Virtual hardware (vblank-less) mode:
- VKMS already has support for vblanks simulated via hrtimers, which can be
Documentation/userspace-api/media/drivers/hantro.rst
-19
View File
@@ -1,19 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0
Hantro video decoder driver
===========================
The Hantro video decoder driver implements the following driver-specific controls:
``V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP (integer)``
Specifies to Hantro HEVC video decoder driver the number of data (in bits) to
skip in the slice segment header.
If non-IDR, the bits to be skipped go from syntax element "pic_output_flag"
to before syntax element "slice_temporal_mvp_enabled_flag".
If IDR, the skipped bits are just "pic_output_flag"
(separate_colour_plane_flag is not supported).
.. note::
This control is not yet part of the public kernel API and
it is expected to change.
Documentation/userspace-api/media/drivers/index.rst
-1
View File
@@ -33,7 +33,6 @@ For more details see the file COPYING in the source distribution of Linux.
ccs
cx2341x-uapi
hantro
imx-uapi
max2175
meye-uapi
Documentation/userspace-api/media/v4l/control.rst
+2 -2
View File
@@ -461,10 +461,10 @@ Example: Changing controls
perror("VIDIOC_QUERYCTRL");
exit(EXIT_FAILURE);
} else {
printf("V4L2_CID_BRIGHTNESS is not supportedn");
printf("V4L2_CID_BRIGHTNESS is not supported\n");
}
} else if (queryctrl.flags & V4L2_CTRL_FLAG_DISABLED) {
printf("V4L2_CID_BRIGHTNESS is not supportedn");
printf("V4L2_CID_BRIGHTNESS is not supported\n");
} else {
memset(&control, 0, sizeof (control));
control.id = V4L2_CID_BRIGHTNESS;
Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst
+902
View File
@@ -2048,3 +2048,905 @@ This structure contains all loop filter related parameters. See sections
- 0x2
- When set, the bitstream contains additional syntax elements that
specify which mode and reference frame deltas are to be updated.
.. _v4l2-codec-stateless-hevc:
``V4L2_CID_STATELESS_HEVC_SPS (struct)``
Specifies the Sequence Parameter Set fields (as extracted from the
bitstream) for the associated HEVC slice data.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.3.2 "Sequence parameter set RBSP
semantics" of the specification.
.. c:type:: v4l2_ctrl_hevc_sps
.. raw:: latex
\small
.. tabularcolumns:: |p{1.2cm}|p{9.2cm}|p{6.9cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_sps
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``video_parameter_set_id``
- Specifies the value of the vps_video_parameter_set_id of the active VPS
as described in section "7.4.3.2.1 General sequence parameter set RBSP semantics"
of H.265 specifications.
* - __u8
- ``seq_parameter_set_id``
- Provides an identifier for the SPS for reference by other syntax elements
as described in section "7.4.3.2.1 General sequence parameter set RBSP semantics"
of H.265 specifications.
* - __u16
- ``pic_width_in_luma_samples``
- Specifies the width of each decoded picture in units of luma samples.
* - __u16
- ``pic_height_in_luma_samples``
- Specifies the height of each decoded picture in units of luma samples.
* - __u8
- ``bit_depth_luma_minus8``
- This value plus 8 specifies the bit depth of the samples of the luma array.
* - __u8
- ``bit_depth_chroma_minus8``
- This value plus 8 specifies the bit depth of the samples of the chroma arrays.
* - __u8
- ``log2_max_pic_order_cnt_lsb_minus4``
- Specifies the value of the variable MaxPicOrderCntLsb.
* - __u8
- ``sps_max_dec_pic_buffering_minus1``
- This value plus 1 specifies the maximum required size of the decoded picture buffer for
the coded video sequence (CVS).
* - __u8
- ``sps_max_num_reorder_pics``
- Indicates the maximum allowed number of pictures.
* - __u8
- ``sps_max_latency_increase_plus1``
- Used to signal MaxLatencyPictures, which indicates the maximum number of
pictures that can precede any picture in output order and follow that
picture in decoding order.
* - __u8
- ``log2_min_luma_coding_block_size_minus3``
- This value plus 3 specifies the minimum luma coding block size.
* - __u8
- ``log2_diff_max_min_luma_coding_block_size``
- Specifies the difference between the maximum and minimum luma coding block size.
* - __u8
- ``log2_min_luma_transform_block_size_minus2``
- This value plus 2 specifies the minimum luma transform block size.
* - __u8
- ``log2_diff_max_min_luma_transform_block_size``
- Specifies the difference between the maximum and minimum luma transform block size.
* - __u8
- ``max_transform_hierarchy_depth_inter``
- Specifies the maximum hierarchy depth for transform units of coding units coded
in inter prediction mode.
* - __u8
- ``max_transform_hierarchy_depth_intra``
- Specifies the maximum hierarchy depth for transform units of coding units coded in
intra prediction mode.
* - __u8
- ``pcm_sample_bit_depth_luma_minus1``
- This value plus 1 specifies the number of bits used to represent each of PCM sample values of the
luma component.
* - __u8
- ``pcm_sample_bit_depth_chroma_minus1``
- Specifies the number of bits used to represent each of PCM sample values of
the chroma components.
* - __u8
- ``log2_min_pcm_luma_coding_block_size_minus3``
- Plus 3 specifies the minimum size of coding blocks.
* - __u8
- ``log2_diff_max_min_pcm_luma_coding_block_size``
- Specifies the difference between the maximum and minimum size of coding blocks.
* - __u8
- ``num_short_term_ref_pic_sets``
- Specifies the number of st_ref_pic_set() syntax structures included in the SPS.
* - __u8
- ``num_long_term_ref_pics_sps``
- Specifies the number of candidate long-term reference pictures that are
specified in the SPS.
* - __u8
- ``chroma_format_idc``
- Specifies the chroma sampling.
* - __u8
- ``sps_max_sub_layers_minus1``
- This value plus 1 specifies the maximum number of temporal sub-layers.
* - __u64
- ``flags``
- See :ref:`Sequence Parameter Set Flags <hevc_sps_flags>`
.. raw:: latex
\normalsize
.. _hevc_sps_flags:
``Sequence Parameter Set Flags``
.. raw:: latex
\small
.. cssclass:: longtable
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE``
- 0x00000001
-
* - ``V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED``
- 0x00000002
-
* - ``V4L2_HEVC_SPS_FLAG_AMP_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET``
- 0x00000008
-
* - ``V4L2_HEVC_SPS_FLAG_PCM_ENABLED``
- 0x00000010
-
* - ``V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED``
- 0x00000020
-
* - ``V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT``
- 0x00000040
-
* - ``V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED``
- 0x00000080
-
* - ``V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED``
- 0x00000100
-
.. raw:: latex
\normalsize
``V4L2_CID_STATELESS_HEVC_PPS (struct)``
Specifies the Picture Parameter Set fields (as extracted from the
bitstream) for the associated HEVC slice data.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.3.3 "Picture parameter set RBSP
semantics" of the specification.
.. c:type:: v4l2_ctrl_hevc_pps
.. tabularcolumns:: |p{1.2cm}|p{8.6cm}|p{7.5cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_pps
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``pic_parameter_set_id``
- Identifies the PPS for reference by other syntax elements.
* - __u8
- ``num_extra_slice_header_bits``
- Specifies the number of extra slice header bits that are present
in the slice header RBSP for coded pictures referring to the PPS.
* - __u8
- ``num_ref_idx_l0_default_active_minus1``
- This value plus 1 specifies the inferred value of num_ref_idx_l0_active_minus1.
* - __u8
- ``num_ref_idx_l1_default_active_minus1``
- This value plus 1 specifies the inferred value of num_ref_idx_l1_active_minus1.
* - __s8
- ``init_qp_minus26``
- This value plus 26 specifies the initial value of SliceQp Y for each slice
referring to the PPS.
* - __u8
- ``diff_cu_qp_delta_depth``
- Specifies the difference between the luma coding tree block size
and the minimum luma coding block size of coding units that
convey cu_qp_delta_abs and cu_qp_delta_sign_flag.
* - __s8
- ``pps_cb_qp_offset``
- Specifies the offsets to the luma quantization parameter Cb.
* - __s8
- ``pps_cr_qp_offset``
- Specifies the offsets to the luma quantization parameter Cr.
* - __u8
- ``num_tile_columns_minus1``
- This value plus 1 specifies the number of tile columns partitioning the picture.
* - __u8
- ``num_tile_rows_minus1``
- This value plus 1 specifies the number of tile rows partitioning the picture.
* - __u8
- ``column_width_minus1[20]``
- This value plus 1 specifies the width of the i-th tile column in units of
coding tree blocks.
* - __u8
- ``row_height_minus1[22]``
- This value plus 1 specifies the height of the i-th tile row in units of coding
tree blocks.
* - __s8
- ``pps_beta_offset_div2``
- Specifies the default deblocking parameter offsets for beta divided by 2.
* - __s8
- ``pps_tc_offset_div2``
- Specifies the default deblocking parameter offsets for tC divided by 2.
* - __u8
- ``log2_parallel_merge_level_minus2``
- This value plus 2 specifies the value of the variable Log2ParMrgLevel.
* - __u8
- ``padding[4]``
- Applications and drivers must set this to zero.
* - __u64
- ``flags``
- See :ref:`Picture Parameter Set Flags <hevc_pps_flags>`
.. _hevc_pps_flags:
``Picture Parameter Set Flags``
.. raw:: latex
\small
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED``
- 0x00000001
-
* - ``V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT``
- 0x00000002
-
* - ``V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT``
- 0x00000008
-
* - ``V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED``
- 0x00000010
-
* - ``V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED``
- 0x00000020
-
* - ``V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED``
- 0x00000040
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT``
- 0x00000080
-
* - ``V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED``
- 0x00000100
-
* - ``V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED``
- 0x00000200
-
* - ``V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED``
- 0x00000400
-
* - ``V4L2_HEVC_PPS_FLAG_TILES_ENABLED``
- 0x00000800
-
* - ``V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED``
- 0x00001000
-
* - ``V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED``
- 0x00002000
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED``
- 0x00004000
-
* - ``V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED``
- 0x00008000
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER``
- 0x00010000
-
* - ``V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT``
- 0x00020000
-
* - ``V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT``
- 0x00040000
-
* - ``V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT``
- 0x00080000
- Specifies the presence of deblocking filter control syntax elements in
the PPS
* - ``V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING``
- 0x00100000
- Specifies that tile column boundaries and likewise tile row boundaries
are distributed uniformly across the picture
.. raw:: latex
\normalsize
``V4L2_CID_STATELESS_HEVC_SLICE_PARAMS (struct)``
Specifies various slice-specific parameters, especially from the NAL unit
header, general slice segment header and weighted prediction parameter
parts of the bitstream.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.7 "General slice segment header
semantics" of the specification.
This control is a dynamically sized 1-dimensional array,
V4L2_CTRL_FLAG_DYNAMIC_ARRAY flag must be set when using it.
.. c:type:: v4l2_ctrl_hevc_slice_params
.. raw:: latex
\scriptsize
.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_slice_params
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u32
- ``bit_size``
- Size (in bits) of the current slice data.
* - __u32
- ``data_byte_offset``
- Offset (in byte) to the video data in the current slice data.
* - __u32
- ``num_entry_point_offsets``
- Specifies the number of entry point offset syntax elements in the slice header.
When the driver supports it, the ``V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS``
must be set.
* - __u8
- ``nal_unit_type``
- Specifies the coding type of the slice (B, P or I).
* - __u8
- ``nuh_temporal_id_plus1``
- Minus 1 specifies a temporal identifier for the NAL unit.
* - __u8
- ``slice_type``
-
(V4L2_HEVC_SLICE_TYPE_I, V4L2_HEVC_SLICE_TYPE_P or
V4L2_HEVC_SLICE_TYPE_B).
* - __u8
- ``colour_plane_id``
- Specifies the colour plane associated with the current slice.
* - __s32
- ``slice_pic_order_cnt``
- Specifies the picture order count.
* - __u8
- ``num_ref_idx_l0_active_minus1``
- This value plus 1 specifies the maximum reference index for reference picture list 0
that may be used to decode the slice.
* - __u8
- ``num_ref_idx_l1_active_minus1``
- This value plus 1 specifies the maximum reference index for reference picture list 1
that may be used to decode the slice.
* - __u8
- ``collocated_ref_idx``
- Specifies the reference index of the collocated picture used for
temporal motion vector prediction.
* - __u8
- ``five_minus_max_num_merge_cand``
- Specifies the maximum number of merging motion vector prediction
candidates supported in the slice subtracted from 5.
* - __s8
- ``slice_qp_delta``
- Specifies the initial value of QpY to be used for the coding blocks in the slice.
* - __s8
- ``slice_cb_qp_offset``
- Specifies a difference to be added to the value of pps_cb_qp_offset.
* - __s8
- ``slice_cr_qp_offset``
- Specifies a difference to be added to the value of pps_cr_qp_offset.
* - __s8
- ``slice_act_y_qp_offset``
- Specifies the offset to the luma of quantization parameter qP derived in section 8.6.2
* - __s8
- ``slice_act_cb_qp_offset``
- Specifies the offset to the cb of quantization parameter qP derived in section 8.6.2
* - __s8
- ``slice_act_cr_qp_offset``
- Specifies the offset to the cr of quantization parameter qP derived in section 8.6.2
* - __s8
- ``slice_beta_offset_div2``
- Specifies the deblocking parameter offsets for beta divided by 2.
* - __s8
- ``slice_tc_offset_div2``
- Specifies the deblocking parameter offsets for tC divided by 2.
* - __u8
- ``pic_struct``
- Indicates whether a picture should be displayed as a frame or as one or more fields.
* - __u32
- ``slice_segment_addr``
- Specifies the address of the first coding tree block in the slice segment.
* - __u8
- ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The list of L0 reference elements as indices in the DPB.
* - __u8
- ``ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The list of L1 reference elements as indices in the DPB.
* - __u16
- ``short_term_ref_pic_set_size``
- Specifies the size, in bits, of the short-term reference picture set, described as st_ref_pic_set()
in the specification, included in the slice header or SPS (section 7.3.6.1).
* - __u16
- ``long_term_ref_pic_set_size``
- Specifies the size, in bits, of the long-term reference picture set include in the slice header
or SPS. It is the number of bits in the conditional block if(long_term_ref_pics_present_flag)
in section 7.3.6.1 of the specification.
* - __u8
- ``padding``
- Applications and drivers must set this to zero.
* - struct :c:type:`v4l2_hevc_pred_weight_table`
- ``pred_weight_table``
- The prediction weight coefficients for inter-picture prediction.
* - __u64
- ``flags``
- See :ref:`Slice Parameters Flags <hevc_slice_params_flags>`
.. raw:: latex
\normalsize
.. _hevc_slice_params_flags:
``Slice Parameters Flags``
.. raw:: latex
\scriptsize
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA``
- 0x00000001
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA``
- 0x00000002
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO``
- 0x00000008
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT``
- 0x00000010
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0``
- 0x00000020
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV``
- 0x00000040
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED``
- 0x00000080
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED``
- 0x00000100
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT``
- 0x00000200
-
.. raw:: latex
\normalsize
``V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS (integer)``
Specifies entry point offsets in bytes.
This control is a dynamically sized array. The number of entry point
offsets is reported by the ``elems`` field.
This bitstream parameter is defined according to :ref:`hevc`.
They are described in section 7.4.7.1 "General slice segment header
semantics" of the specification.
When multiple slices are submitted in a request, the length of
this array must be the sum of num_entry_point_offsets of all the
slices in the request.
``V4L2_CID_STATELESS_HEVC_SCALING_MATRIX (struct)``
Specifies the HEVC scaling matrix parameters used for the scaling process
for transform coefficients.
These matrix and parameters are defined according to :ref:`hevc`.
They are described in section 7.4.5 "Scaling list data semantics" of
the specification.
.. c:type:: v4l2_ctrl_hevc_scaling_matrix
.. raw:: latex
\scriptsize
.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``scaling_list_4x4[6][16]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_8x8[6][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_16x16[6][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_32x32[2][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_dc_coef_16x16[6]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_dc_coef_32x32[2]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
.. raw:: latex
\normalsize
.. c:type:: v4l2_hevc_dpb_entry
.. raw:: latex
\small
.. tabularcolumns:: |p{1.0cm}|p{4.2cm}|p{12.1cm}|
.. flat-table:: struct v4l2_hevc_dpb_entry
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u64
- ``timestamp``
- Timestamp of the V4L2 capture buffer to use as reference, used
with B-coded and P-coded frames. The timestamp refers to the
``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the
:c:func:`v4l2_timeval_to_ns()` function to convert the struct
:c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64.
* - __u8
- ``flags``
- Long term flag for the reference frame
(V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE). The flag is set as
described in the ITU HEVC specification chapter "8.3.2 Decoding
process for reference picture set".
* - __u8
- ``field_pic``
- Whether the reference is a field picture or a frame.
See :ref:`HEVC dpb field pic Flags <hevc_dpb_field_pic_flags>`
* - __s32
- ``pic_order_cnt_val``
- The picture order count of the current picture.
* - __u8
- ``padding[2]``
- Applications and drivers must set this to zero.
.. raw:: latex
\normalsize
.. _hevc_dpb_field_pic_flags:
``HEVC dpb field pic Flags``
.. raw:: latex
\scriptsize
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_SEI_PIC_STRUCT_FRAME``
- 0
- (progressive) Frame
* - ``V4L2_HEVC_SEI_PIC_STRUCT_TOP_FIELD``
- 1
- Top field
* - ``V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_FIELD``
- 2
- Bottom field
* - ``V4L2_HEVC_SEI_PIC_STRUCT_TOP_BOTTOM``
- 3
- Top field, bottom field, in that order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_TOP``
- 4
- Bottom field, top field, in that order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_TOP_BOTTOM_TOP``
- 5
- Top field, bottom field, top field repeated, in that order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_TOP_BOTTOM``
- 6
- Bottom field, top field, bottom field repeated, in that order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_FRAME_DOUBLING``
- 7
- Frame doubling
* - ``V4L2_HEVC_SEI_PIC_STRUCT_FRAME_TRIPLING``
- 8
- Frame tripling
* - ``V4L2_HEVC_SEI_PIC_STRUCT_TOP_PAIRED_PREVIOUS_BOTTOM``
- 9
- Top field paired with previous bottom field in output order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_PAIRED_PREVIOUS_TOP``
- 10
- Bottom field paired with previous top field in output order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_TOP_PAIRED_NEXT_BOTTOM``
- 11
- Top field paired with next bottom field in output order
* - ``V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_PAIRED_NEXT_TOP``
- 12
- Bottom field paired with next top field in output order
.. c:type:: v4l2_hevc_pred_weight_table
.. raw:: latex
\footnotesize
.. tabularcolumns:: |p{0.8cm}|p{10.6cm}|p{5.9cm}|
.. flat-table:: struct v4l2_hevc_pred_weight_table
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __s8
- ``delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The difference of the weighting factor applied to the luma
prediction value for list 0.
* - __s8
- ``luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The additive offset applied to the luma prediction value for list 0.
* - __s8
- ``delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
- The difference of the weighting factor applied to the chroma
prediction value for list 0.
* - __s8
- ``chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
- The difference of the additive offset applied to the chroma
prediction values for list 0.
* - __s8
- ``delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The difference of the weighting factor applied to the luma
prediction value for list 1.
* - __s8
- ``luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The additive offset applied to the luma prediction value for list 1.
* - __s8
- ``delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
- The difference of the weighting factor applied to the chroma
prediction value for list 1.
* - __s8
- ``chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
- The difference of the additive offset applied to the chroma
prediction values for list 1.
* - __u8
- ``luma_log2_weight_denom``
- The base 2 logarithm of the denominator for all luma weighting
factors.
* - __s8
- ``delta_chroma_log2_weight_denom``
- The difference of the base 2 logarithm of the denominator for
all chroma weighting factors.
* - __u8
- ``padding[6]``
- Applications and drivers must set this to zero.
.. raw:: latex
\normalsize
``V4L2_CID_STATELESS_HEVC_DECODE_MODE (enum)``
Specifies the decoding mode to use. Currently exposes slice-based and
frame-based decoding but new modes might be added later on.
This control is used as a modifier for V4L2_PIX_FMT_HEVC_SLICE
pixel format. Applications that support V4L2_PIX_FMT_HEVC_SLICE
are required to set this control in order to specify the decoding mode
that is expected for the buffer.
Drivers may expose a single or multiple decoding modes, depending
on what they can support.
.. c:type:: v4l2_stateless_hevc_decode_mode
.. raw:: latex
\small
.. tabularcolumns:: |p{9.4cm}|p{0.6cm}|p{7.3cm}|
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED``
- 0
- Decoding is done at the slice granularity.
The OUTPUT buffer must contain a single slice.
* - ``V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED``
- 1
- Decoding is done at the frame granularity.
The OUTPUT buffer must contain all slices needed to decode the
frame.
.. raw:: latex
\normalsize
``V4L2_CID_STATELESS_HEVC_START_CODE (enum)``
Specifies the HEVC slice start code expected for each slice.
This control is used as a modifier for V4L2_PIX_FMT_HEVC_SLICE
pixel format. Applications that support V4L2_PIX_FMT_HEVC_SLICE
are required to set this control in order to specify the start code
that is expected for the buffer.
Drivers may expose a single or multiple start codes, depending
on what they can support.
.. c:type:: v4l2_stateless_hevc_start_code
.. tabularcolumns:: |p{9.2cm}|p{0.6cm}|p{7.5cm}|
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_STATELESS_HEVC_START_CODE_NONE``
- 0
- Selecting this value specifies that HEVC slices are passed
to the driver without any start code. The bitstream data should be
according to :ref:`hevc` 7.3.1.1 General NAL unit syntax, hence
contains emulation prevention bytes when required.
* - ``V4L2_STATELESS_HEVC_START_CODE_ANNEX_B``
- 1
- Selecting this value specifies that HEVC slices are expected
to be prefixed by Annex B start codes. According to :ref:`hevc`
valid start codes can be 3-bytes 0x000001 or 4-bytes 0x00000001.
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID (integer)``
Specifies a priority identifier for the NAL unit, which will be applied to
the base layer. By default this value is set to 0 for the base layer,
and the next layer will have the priority ID assigned as 1, 2, 3 and so on.
The video encoder can't decide the priority id to be applied to a layer,
so this has to come from client.
This is applicable to H264 and valid Range is from 0 to 63.
Source Rec. ITU-T H.264 (06/2019); G.7.4.1.1, G.8.8.1.
``V4L2_CID_MPEG_VIDEO_LTR_COUNT (integer)``
Specifies the maximum number of Long Term Reference (LTR) frames at any
given time that the encoder can keep.
This is applicable to the H264 and HEVC encoders.
``V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX (integer)``
After setting this control the frame that will be queued next
will be marked as a Long Term Reference (LTR) frame
and given this LTR index which ranges from 0 to LTR_COUNT-1.
This is applicable to the H264 and HEVC encoders.
Source Rec. ITU-T H.264 (06/2019); Table 7.9
``V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES (bitmask)``
Specifies the Long Term Reference (LTR) frame(s) to be used for
encoding the next frame queued after setting this control.
This provides a bitmask which consists of bits [0, LTR_COUNT-1].
This is applicable to the H264 and HEVC encoders.
``V4L2_CID_STATELESS_HEVC_DECODE_PARAMS (struct)``
Specifies various decode parameters, especially the references picture order
count (POC) for all the lists (short, long, before, current, after) and the
number of entries for each of them.
These parameters are defined according to :ref:`hevc`.
They are described in section 8.3 "Slice decoding process" of the
specification.
.. c:type:: v4l2_ctrl_hevc_decode_params
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_decode_params
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __s32
- ``pic_order_cnt_val``
- PicOrderCntVal as described in section 8.3.1 "Decoding process
for picture order count" of the specification.
* - __u16
- ``short_term_ref_pic_set_size``
- Specifies the size, in bits, of the short-term reference picture set, of the first slice
described as st_ref_pic_set() in the specification, included in the slice header
or SPS (section 7.3.6.1).
* - __u16
- ``long_term_ref_pic_set_size``
- Specifies the size, in bits, of the long-term reference picture set, of the first slice
included in the slice header or SPS. It is the number of bits in the conditional block
if(long_term_ref_pics_present_flag) in section 7.3.6.1 of the specification.
* - __u8
- ``num_active_dpb_entries``
- The number of entries in ``dpb``.
* - __u8
- ``num_poc_st_curr_before``
- The number of reference pictures in the short-term set that come before
the current frame.
* - __u8
- ``num_poc_st_curr_after``
- The number of reference pictures in the short-term set that come after
the current frame.
* - __u8
- ``num_poc_lt_curr``
- The number of reference pictures in the long-term set.
* - __u8
- ``poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocStCurrBefore as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the short term before references in DPB array.
* - __u8
- ``poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocStCurrAfter as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the short term after references in DPB array.
* - __u8
- ``poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocLtCurr as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the long term references in DPB array.
* - struct :c:type:`v4l2_hevc_dpb_entry`
- ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The decoded picture buffer, for meta-data about reference frames.
* - __u64
- ``flags``
- See :ref:`Decode Parameters Flags <hevc_decode_params_flags>`
.. _hevc_decode_params_flags:
``Decode Parameters Flags``
.. cssclass:: longtable
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC``
- 0x00000001
-
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC``
- 0x00000002
-
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR``
- 0x00000004
-
Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
-780
View File
@@ -2658,783 +2658,3 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
Indicates whether to generate SPS and PPS at every IDR. Setting it to 0
disables generating SPS and PPS at every IDR. Setting it to one enables
generating SPS and PPS at every IDR.
.. _v4l2-mpeg-hevc:
``V4L2_CID_MPEG_VIDEO_HEVC_SPS (struct)``
Specifies the Sequence Parameter Set fields (as extracted from the
bitstream) for the associated HEVC slice data.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.3.2 "Sequence parameter set RBSP
semantics" of the specification.
.. c:type:: v4l2_ctrl_hevc_sps
.. raw:: latex
\small
.. tabularcolumns:: |p{1.2cm}|p{9.2cm}|p{6.9cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_sps
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u16
- ``pic_width_in_luma_samples``
-
* - __u16
- ``pic_height_in_luma_samples``
-
* - __u8
- ``bit_depth_luma_minus8``
-
* - __u8
- ``bit_depth_chroma_minus8``
-
* - __u8
- ``log2_max_pic_order_cnt_lsb_minus4``
-
* - __u8
- ``sps_max_dec_pic_buffering_minus1``
-
* - __u8
- ``sps_max_num_reorder_pics``
-
* - __u8
- ``sps_max_latency_increase_plus1``
-
* - __u8
- ``log2_min_luma_coding_block_size_minus3``
-
* - __u8
- ``log2_diff_max_min_luma_coding_block_size``
-
* - __u8
- ``log2_min_luma_transform_block_size_minus2``
-
* - __u8
- ``log2_diff_max_min_luma_transform_block_size``
-
* - __u8
- ``max_transform_hierarchy_depth_inter``
-
* - __u8
- ``max_transform_hierarchy_depth_intra``
-
* - __u8
- ``pcm_sample_bit_depth_luma_minus1``
-
* - __u8
- ``pcm_sample_bit_depth_chroma_minus1``
-
* - __u8
- ``log2_min_pcm_luma_coding_block_size_minus3``
-
* - __u8
- ``log2_diff_max_min_pcm_luma_coding_block_size``
-
* - __u8
- ``num_short_term_ref_pic_sets``
-
* - __u8
- ``num_long_term_ref_pics_sps``
-
* - __u8
- ``chroma_format_idc``
-
* - __u8
- ``sps_max_sub_layers_minus1``
-
* - __u64
- ``flags``
- See :ref:`Sequence Parameter Set Flags <hevc_sps_flags>`
.. raw:: latex
\normalsize
.. _hevc_sps_flags:
``Sequence Parameter Set Flags``
.. raw:: latex
\small
.. cssclass:: longtable
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE``
- 0x00000001
-
* - ``V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED``
- 0x00000002
-
* - ``V4L2_HEVC_SPS_FLAG_AMP_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET``
- 0x00000008
-
* - ``V4L2_HEVC_SPS_FLAG_PCM_ENABLED``
- 0x00000010
-
* - ``V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED``
- 0x00000020
-
* - ``V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT``
- 0x00000040
-
* - ``V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED``
- 0x00000080
-
* - ``V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED``
- 0x00000100
-
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_HEVC_PPS (struct)``
Specifies the Picture Parameter Set fields (as extracted from the
bitstream) for the associated HEVC slice data.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.3.3 "Picture parameter set RBSP
semantics" of the specification.
.. c:type:: v4l2_ctrl_hevc_pps
.. tabularcolumns:: |p{1.2cm}|p{8.6cm}|p{7.5cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_pps
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``num_extra_slice_header_bits``
-
* - __u8
- ``num_ref_idx_l0_default_active_minus1``
- Specifies the inferred value of num_ref_idx_l0_active_minus1
* - __u8
- ``num_ref_idx_l1_default_active_minus1``
- Specifies the inferred value of num_ref_idx_l1_active_minus1
* - __s8
- ``init_qp_minus26``
-
* - __u8
- ``diff_cu_qp_delta_depth``
-
* - __s8
- ``pps_cb_qp_offset``
-
* - __s8
- ``pps_cr_qp_offset``
-
* - __u8
- ``num_tile_columns_minus1``
-
* - __u8
- ``num_tile_rows_minus1``
-
* - __u8
- ``column_width_minus1[20]``
-
* - __u8
- ``row_height_minus1[22]``
-
* - __s8
- ``pps_beta_offset_div2``
-
* - __s8
- ``pps_tc_offset_div2``
-
* - __u8
- ``log2_parallel_merge_level_minus2``
-
* - __u8
- ``padding[4]``
- Applications and drivers must set this to zero.
* - __u64
- ``flags``
- See :ref:`Picture Parameter Set Flags <hevc_pps_flags>`
.. _hevc_pps_flags:
``Picture Parameter Set Flags``
.. raw:: latex
\small
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED``
- 0x00000001
-
* - ``V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT``
- 0x00000002
-
* - ``V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT``
- 0x00000008
-
* - ``V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED``
- 0x00000010
-
* - ``V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED``
- 0x00000020
-
* - ``V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED``
- 0x00000040
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT``
- 0x00000080
-
* - ``V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED``
- 0x00000100
-
* - ``V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED``
- 0x00000200
-
* - ``V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED``
- 0x00000400
-
* - ``V4L2_HEVC_PPS_FLAG_TILES_ENABLED``
- 0x00000800
-
* - ``V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED``
- 0x00001000
-
* - ``V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED``
- 0x00002000
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED``
- 0x00004000
-
* - ``V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED``
- 0x00008000
-
* - ``V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER``
- 0x00010000
-
* - ``V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT``
- 0x00020000
-
* - ``V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT``
- 0x00040000
-
* - ``V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT``
- 0x00080000
- Specifies the presence of deblocking filter control syntax elements in
the PPS
* - ``V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING``
- 0x00100000
- Specifies that tile column boundaries and likewise tile row boundaries
are distributed uniformly across the picture
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (struct)``
Specifies various slice-specific parameters, especially from the NAL unit
header, general slice segment header and weighted prediction parameter
parts of the bitstream.
These bitstream parameters are defined according to :ref:`hevc`.
They are described in section 7.4.7 "General slice segment header
semantics" of the specification.
.. c:type:: v4l2_ctrl_hevc_slice_params
.. raw:: latex
\scriptsize
.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_slice_params
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u32
- ``bit_size``
- Size (in bits) of the current slice data.
* - __u32
- ``data_bit_offset``
- Offset (in bits) to the video data in the current slice data.
* - __u8
- ``nal_unit_type``
-
* - __u8
- ``nuh_temporal_id_plus1``
-
* - __u8
- ``slice_type``
-
(V4L2_HEVC_SLICE_TYPE_I, V4L2_HEVC_SLICE_TYPE_P or
V4L2_HEVC_SLICE_TYPE_B).
* - __u8
- ``colour_plane_id``
-
* - __u16
- ``slice_pic_order_cnt``
-
* - __u8
- ``num_ref_idx_l0_active_minus1``
-
* - __u8
- ``num_ref_idx_l1_active_minus1``
-
* - __u8
- ``collocated_ref_idx``
-
* - __u8
- ``five_minus_max_num_merge_cand``
-
* - __s8
- ``slice_qp_delta``
-
* - __s8
- ``slice_cb_qp_offset``
-
* - __s8
- ``slice_cr_qp_offset``
-
* - __s8
- ``slice_act_y_qp_offset``
-
* - __s8
- ``slice_act_cb_qp_offset``
-
* - __s8
- ``slice_act_cr_qp_offset``
-
* - __s8
- ``slice_beta_offset_div2``
-
* - __s8
- ``slice_tc_offset_div2``
-
* - __u8
- ``pic_struct``
-
* - __u32
- ``slice_segment_addr``
-
* - __u8
- ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The list of L0 reference elements as indices in the DPB.
* - __u8
- ``ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The list of L1 reference elements as indices in the DPB.
* - __u8
- ``padding``
- Applications and drivers must set this to zero.
* - struct :c:type:`v4l2_hevc_pred_weight_table`
- ``pred_weight_table``
- The prediction weight coefficients for inter-picture prediction.
* - __u64
- ``flags``
- See :ref:`Slice Parameters Flags <hevc_slice_params_flags>`
.. raw:: latex
\normalsize
.. _hevc_slice_params_flags:
``Slice Parameters Flags``
.. raw:: latex
\scriptsize
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA``
- 0x00000001
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA``
- 0x00000002
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED``
- 0x00000004
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO``
- 0x00000008
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT``
- 0x00000010
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0``
- 0x00000020
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV``
- 0x00000040
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED``
- 0x00000080
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED``
- 0x00000100
-
* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT``
- 0x00000200
-
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (struct)``
Specifies the HEVC scaling matrix parameters used for the scaling process
for transform coefficients.
These matrix and parameters are defined according to :ref:`hevc`.
They are described in section 7.4.5 "Scaling list data semantics" of
the specification.
.. c:type:: v4l2_ctrl_hevc_scaling_matrix
.. raw:: latex
\scriptsize
.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}|
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``scaling_list_4x4[6][16]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_8x8[6][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_16x16[6][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_32x32[2][64]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_dc_coef_16x16[6]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
* - __u8
- ``scaling_list_dc_coef_32x32[2]``
- Scaling list is used for the scaling process for transform
coefficients. The values on each scaling list are expected
in raster scan order.
.. raw:: latex
\normalsize
.. c:type:: v4l2_hevc_dpb_entry
.. raw:: latex
\small
.. tabularcolumns:: |p{1.0cm}|p{4.2cm}|p{12.1cm}|
.. flat-table:: struct v4l2_hevc_dpb_entry
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u64
- ``timestamp``
- Timestamp of the V4L2 capture buffer to use as reference, used
with B-coded and P-coded frames. The timestamp refers to the
``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the
:c:func:`v4l2_timeval_to_ns()` function to convert the struct
:c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64.
* - __u8
- ``flags``
- Long term flag for the reference frame
(V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE). The flag is set as
described in the ITU HEVC specification chapter "8.3.2 Decoding
process for reference picture set".
* - __u8
- ``field_pic``
- Whether the reference is a field picture or a frame.
* - __u16
- ``pic_order_cnt[2]``
- The picture order count of the reference. Only the first element of the
array is used for frame pictures, while the first element identifies the
top field and the second the bottom field in field-coded pictures.
* - __u8
- ``padding[2]``
- Applications and drivers must set this to zero.
.. raw:: latex
\normalsize
.. c:type:: v4l2_hevc_pred_weight_table
.. raw:: latex
\footnotesize
.. tabularcolumns:: |p{0.8cm}|p{10.6cm}|p{5.9cm}|
.. flat-table:: struct v4l2_hevc_pred_weight_table
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __u8
- ``luma_log2_weight_denom``
-
* - __s8
- ``delta_chroma_log2_weight_denom``
-
* - __s8
- ``delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
-
* - __s8
- ``luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
-
* - __s8
- ``delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
-
* - __s8
- ``chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
-
* - __s8
- ``delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
-
* - __s8
- ``luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
-
* - __s8
- ``delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
-
* - __s8
- ``chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]``
-
* - __u8
- ``padding[6]``
- Applications and drivers must set this to zero.
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (enum)``
Specifies the decoding mode to use. Currently exposes slice-based and
frame-based decoding but new modes might be added later on.
This control is used as a modifier for V4L2_PIX_FMT_HEVC_SLICE
pixel format. Applications that support V4L2_PIX_FMT_HEVC_SLICE
are required to set this control in order to specify the decoding mode
that is expected for the buffer.
Drivers may expose a single or multiple decoding modes, depending
on what they can support.
.. note::
This menu control is not yet part of the public kernel API and
it is expected to change.
.. c:type:: v4l2_mpeg_video_hevc_decode_mode
.. raw:: latex
\small
.. tabularcolumns:: |p{9.4cm}|p{0.6cm}|p{7.3cm}|
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED``
- 0
- Decoding is done at the slice granularity.
The OUTPUT buffer must contain a single slice.
* - ``V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED``
- 1
- Decoding is done at the frame granularity.
The OUTPUT buffer must contain all slices needed to decode the
frame. The OUTPUT buffer must also contain both fields.
.. raw:: latex
\normalsize
``V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (enum)``
Specifies the HEVC slice start code expected for each slice.
This control is used as a modifier for V4L2_PIX_FMT_HEVC_SLICE
pixel format. Applications that support V4L2_PIX_FMT_HEVC_SLICE
are required to set this control in order to specify the start code
that is expected for the buffer.
Drivers may expose a single or multiple start codes, depending
on what they can support.
.. note::
This menu control is not yet part of the public kernel API and
it is expected to change.
.. c:type:: v4l2_mpeg_video_hevc_start_code
.. tabularcolumns:: |p{9.2cm}|p{0.6cm}|p{7.5cm}|
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE``
- 0
- Selecting this value specifies that HEVC slices are passed
to the driver without any start code. The bitstream data should be
according to :ref:`hevc` 7.3.1.1 General NAL unit syntax, hence
contains emulation prevention bytes when required.
* - ``V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B``
- 1
- Selecting this value specifies that HEVC slices are expected
to be prefixed by Annex B start codes. According to :ref:`hevc`
valid start codes can be 3-bytes 0x000001 or 4-bytes 0x00000001.
``V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID (integer)``
Specifies a priority identifier for the NAL unit, which will be applied to
the base layer. By default this value is set to 0 for the base layer,
and the next layer will have the priority ID assigned as 1, 2, 3 and so on.
The video encoder can't decide the priority id to be applied to a layer,
so this has to come from client.
This is applicable to H264 and valid Range is from 0 to 63.
Source Rec. ITU-T H.264 (06/2019); G.7.4.1.1, G.8.8.1.
``V4L2_CID_MPEG_VIDEO_LTR_COUNT (integer)``
Specifies the maximum number of Long Term Reference (LTR) frames at any
given time that the encoder can keep.
This is applicable to the H264 and HEVC encoders.
``V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX (integer)``
After setting this control the frame that will be queued next
will be marked as a Long Term Reference (LTR) frame
and given this LTR index which ranges from 0 to LTR_COUNT-1.
This is applicable to the H264 and HEVC encoders.
Source Rec. ITU-T H.264 (06/2019); Table 7.9
``V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES (bitmask)``
Specifies the Long Term Reference (LTR) frame(s) to be used for
encoding the next frame queued after setting this control.
This provides a bitmask which consists of bits [0, LTR_COUNT-1].
This is applicable to the H264 and HEVC encoders.
``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (struct)``
Specifies various decode parameters, especially the references picture order
count (POC) for all the lists (short, long, before, current, after) and the
number of entries for each of them.
These parameters are defined according to :ref:`hevc`.
They are described in section 8.3 "Slice decoding process" of the
specification.
.. c:type:: v4l2_ctrl_hevc_decode_params
.. cssclass:: longtable
.. flat-table:: struct v4l2_ctrl_hevc_decode_params
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - __s32
- ``pic_order_cnt_val``
- PicOrderCntVal as described in section 8.3.1 "Decoding process
for picture order count" of the specification.
* - __u8
- ``num_active_dpb_entries``
- The number of entries in ``dpb``.
* - struct :c:type:`v4l2_hevc_dpb_entry`
- ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The decoded picture buffer, for meta-data about reference frames.
* - __u8
- ``num_poc_st_curr_before``
- The number of reference pictures in the short-term set that come before
the current frame.
* - __u8
- ``num_poc_st_curr_after``
- The number of reference pictures in the short-term set that come after
the current frame.
* - __u8
- ``num_poc_lt_curr``
- The number of reference pictures in the long-term set.
* - __u8
- ``poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocStCurrBefore as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the short term before references in DPB array.
* - __u8
- ``poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocStCurrAfter as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the short term after references in DPB array.
* - __u8
- ``poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocLtCurr as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the long term references in DPB array.
* - __u64
- ``flags``
- See :ref:`Decode Parameters Flags <hevc_decode_params_flags>`
.. _hevc_decode_params_flags:
``Decode Parameters Flags``
.. cssclass:: longtable
.. flat-table::
:header-rows: 0
:stub-columns: 0
:widths: 1 1 2
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC``
- 0x00000001
-
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC``
- 0x00000002
-
* - ``V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR``
- 0x00000004
-
Documentation/userspace-api/media/v4l/mmap.rst
+1 -1
View File
@@ -232,7 +232,7 @@ In the write loop, when the application runs out of free buffers, it
must wait until an empty buffer can be dequeued and reused.
To enqueue and dequeue a buffer applications use the
:ref:`VIVIOC_QBUF <VIDIOC_QBUF>` and :ref:`VIDIOC_DQBUF <VIDIOC_QBUF>`
:ref:`VIDIOC_QBUF <VIDIOC_QBUF>` and :ref:`VIDIOC_DQBUF <VIDIOC_QBUF>`
ioctl. The status of a buffer being mapped, enqueued, full or empty can
be determined at any time using the :ref:`VIDIOC_QUERYBUF` ioctl. Two
methods exist to suspend execution of the application until one or more
Documentation/userspace-api/media/v4l/pixfmt-compressed.rst
+1 -6
View File
@@ -212,14 +212,9 @@ Compressed Formats
``V4L2_CID_MPEG_VIDEO_HEVC_SPS``,
``V4L2_CID_MPEG_VIDEO_HEVC_PPS``, and
``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS``.
See the :ref:`associated Codec Control IDs <v4l2-mpeg-hevc>`.
See the :ref:`associated Codec Control IDs <v4l2-codec-stateless-hevc>`.
Buffers associated with this pixel format must contain the appropriate
number of macroblocks to decode a full corresponding frame.
.. note::
This format is not yet part of the public kernel API and it
is expected to change.
* .. _V4L2-PIX-FMT-FWHT:
- ``V4L2_PIX_FMT_FWHT``
Documentation/userspace-api/media/v4l/pixfmt-packed-yuv.rst
+20
View File
@@ -220,6 +220,26 @@ the second byte and Y'\ :sub:`7-0` in the third byte.
- Y'\ :sub:`7-0`
- X\ :sub:`7-0`
* .. _V4L2-PIX-FMT-YUVA32:
- ``V4L2_PIX_FMT_YUVA32``
- 'YUVA'
- Y'\ :sub:`7-0`
- Cb\ :sub:`7-0`
- Cr\ :sub:`7-0`
- A\ :sub:`7-0`
* .. _V4L2-PIX-FMT-YUVX32:
- ``V4L2_PIX_FMT_YUVX32``
- 'YUVX'
- Y'\ :sub:`7-0`
- Cb\ :sub:`7-0`
- Cr\ :sub:`7-0`
- X\ :sub:`7-0`
* .. _V4L2-PIX-FMT-YUV24:
- ``V4L2_PIX_FMT_YUV24``
Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
+63
View File
@@ -109,6 +109,20 @@ All components are stored with the same number of bits per component.
- Cb, Cr
- No
- 16x16 tiles
* - V4L2_PIX_FMT_P010
- 'P010'
- 10
- 4:2:0
- Cb, Cr
- Yes
- Linear
* - V4L2_PIX_FMT_P010_4L4
- 'T010'
- 10
- 4:2:0
- Cb, Cr
- Yes
- 4x4 tiles
* - V4L2_PIX_FMT_NV16
- 'NV16'
- 8
@@ -171,6 +185,7 @@ horizontally.
.. _V4L2-PIX-FMT-NV21:
.. _V4L2-PIX-FMT-NV12M:
.. _V4L2-PIX-FMT-NV21M:
.. _V4L2-PIX-FMT-P010:
NV12, NV21, NV12M and NV21M
---------------------------
@@ -519,6 +534,50 @@ number of lines as the luma plane.
- Cb\ :sub:`33`
- Cr\ :sub:`33`
.. _V4L2_PIX_FMT_P010:
.. _V4L2-PIX-FMT-P010-4L4:
P010 and tiled P010
-------------------
P010 is like NV12 with 10 bits per component, expanded to 16 bits.
Data in the 10 high bits, zeros in the 6 low bits, arranged in little endian order.
.. flat-table:: Sample 4x4 P010 Image
:header-rows: 0
:stub-columns: 0
* - start + 0:
- Y'\ :sub:`00`
- Y'\ :sub:`01`
- Y'\ :sub:`02`
- Y'\ :sub:`03`
* - start + 8:
- Y'\ :sub:`10`
- Y'\ :sub:`11`
- Y'\ :sub:`12`
- Y'\ :sub:`13`
* - start + 16:
- Y'\ :sub:`20`
- Y'\ :sub:`21`
- Y'\ :sub:`22`
- Y'\ :sub:`23`
* - start + 24:
- Y'\ :sub:`30`
- Y'\ :sub:`31`
- Y'\ :sub:`32`
- Y'\ :sub:`33`
* - start + 32:
- Cb\ :sub:`00`
- Cr\ :sub:`00`
- Cb\ :sub:`01`
- Cr\ :sub:`01`
* - start + 40:
- Cb\ :sub:`10`
- Cr\ :sub:`10`
- Cb\ :sub:`11`
- Cr\ :sub:`11`
Fully Planar YUV Formats
========================
@@ -538,6 +597,10 @@ relationship between the luma and chroma line padding and stride.
All components are stored with the same number of bits per component.
``V4L2_PIX_FMT_P010_4L4`` stores pixels in 4x4 tiles, and stores tiles linearly
in memory. The line stride must be aligned to multiple of 8 and image height to
a multiple of 4. The layouts of the luma and chroma planes are identical.
.. raw:: latex
\small

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