Ishan Shah
484758e7a6
Adding a driver to handle setup and trigger for IST through the L4T kernel. This driver "hijacks" the current Hotplug entry/exit flow to instead trigger the core to enter the RIST state. Upon failure or success, the core will then be left in the "unplugged" state, to be brought back online at a later time manually. This set of changes is mainly meant for testing RIST in L4T-based systems. This is not intended for production use-cases. TPS-589 Signed-off-by: Ishan Shah <ishah@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Noah Wager <noah.wager@canonical.com> Acked-by: Jacob Martin <jacob.martin@canonical.com> Signed-off-by: Noah Wager <noah.wager@canonical.com>
137 lines
3.2 KiB
C
137 lines
3.2 KiB
C
/*
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* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/arm-smccc.h>
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#include <linux/cpumask.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <uapi/linux/psci.h>
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#include <misc/nv_ist.h>
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/* RIST START SMC */
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/* https://confluence.nvidia.com/display/TFA/Central+Registry+for+SMCs */
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#define NV_IST_FN_RIST_START 0xC200FF0A
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struct ist_smc_vars {
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bool enable;
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u32 tid;
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u32 smc_id;
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};
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static struct ist_smc_vars *cpu_settings;
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static struct dentry *dbgfs_root;
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bool is_ist_enabled(unsigned int cpu)
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{
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return cpu_settings != NULL && cpu_settings[cpu].enable;
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}
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void cpu_enter_ist(unsigned int cpu)
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{
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struct arm_smccc_res res;
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if ((cpu_settings != NULL && cpu_settings[cpu].enable)) {
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pr_debug("CPU %x is entering SMC %x\n", cpu, cpu_settings[cpu].smc_id);
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arm_smccc_smc(cpu_settings[cpu].smc_id,
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cpu_settings[cpu].tid,
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0, 0, 0, 0, 0, 0, &res);
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}
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}
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static int create_ist_debugfs_entries(void)
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{
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char subdir_name[6]; /* cpu + XX + \n */
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struct dentry *subdir;
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int cpu;
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dbgfs_root = debugfs_create_dir("nv_ist", NULL);
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if (!dbgfs_root) {
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return -ENOENT;
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}
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for (cpu = cpumask_first(cpu_possible_mask);
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cpu < nr_cpu_ids;
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cpu = cpumask_next(cpu, cpu_possible_mask)) {
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snprintf(subdir_name, 6, "cpu%d", cpu);
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subdir = debugfs_create_dir(subdir_name, dbgfs_root);
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if (subdir == NULL)
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goto err;
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debugfs_create_bool("enable", 0644,
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subdir, &(cpu_settings[cpu].enable));
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debugfs_create_u32("test_id", 0644,
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subdir, &(cpu_settings[cpu].tid));
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}
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return 0;
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err:
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debugfs_remove_recursive(dbgfs_root);
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return -ENOENT;
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}
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static int tegra_ist_probe(struct platform_device *pdev)
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{
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size_t i;
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int err = 0;
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/* Zero-initialized */
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cpu_settings = devm_kcalloc(&pdev->dev, nr_cpu_ids,
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sizeof(struct ist_smc_vars), GFP_KERNEL);
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/* Setting the PSCI-ID to RIST_START SMC */
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for (i = 0; i < nr_cpu_ids; i++) {
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cpu_settings[i].enable = false;
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cpu_settings[i].tid = 0U;
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cpu_settings[i].smc_id = NV_IST_FN_RIST_START;
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}
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/* Create debugfs */
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err = create_ist_debugfs_entries();
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if (err)
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devm_kfree(&pdev->dev, cpu_settings);
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return err;
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}
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static int tegra_ist_remove(struct platform_device *pdev)
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{
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debugfs_remove_recursive(dbgfs_root);
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return 0;
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}
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static const struct of_device_id tegra_ist_of_match[] = {
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{ .compatible = "nvidia,tegra26x-ist" },
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{ }, /* Terminal */
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};
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static struct platform_driver nv_ist_driver = {
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.probe = tegra_ist_probe,
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.remove = tegra_ist_remove,
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.driver = {
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.name = "nv_ist",
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.of_match_table = tegra_ist_of_match,
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},
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};
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module_platform_driver(nv_ist_driver);
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MODULE_AUTHOR("Ishan Shah <ishah@nvidia.com>");
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MODULE_DESCRIPTION("NV IST Driver");
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MODULE_LICENSE("GPL v2");
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