Alison Schofield
a78297c1ac
BugLink: https://bugs.launchpad.net/bugs/2086138
[ Upstream commit 3b2fedcd75e3991e77c2a8c3ebcab0ea68b2d69d ]
When a device reports a DPA in events like poison, general_media,
and dram, the driver translates that DPA back to an HPA. Presently,
the CXL driver translation only considers the Modulo position and
will report the wrong HPA for XOR configured root decoders.
Add a helper function that restores the XOR'd bits during DPA->HPA
address translation. Plumb a root decoder callback to the new helper
when XOR interleave arithmetic is in use. For Modulo arithmetic, just
let the callback be NULL - as in no extra work required.
Upon completion of a DPA->HPA translation a couple of checks are
performed on the result. One simply confirms that the calculated
HPA is within the address range of the region. That test is useful
for both Modulo and XOR interleave arithmetic decodes.
A second check confirms that the HPA is within an expected chunk
based on the endpoints position in the region and the region
granularity. An XOR decode disrupts the Modulo pattern making the
chunk check useless.
To align the checks with the proper decode, pull the region range
check inline and use the helper to do the chunk check for Modulo
decodes only.
A cxl-test unit test is posted for upstream review here:
https://lore.kernel.org/20240624210644.495563-1-alison.schofield@intel.com/
Fixes: 28a3ae4ff6 ("cxl/trace: Add an HPA to cxl_poison trace events")
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Tested-by: Diego Garcia Rodriguez <diego.garcia.rodriguez@intel.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Link: https://patch.msgid.link/1a1ac880d9f889bd6384e657e810431b9a0a72e5.1719980933.git.alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[koichiroden: applied changes for drivers/cxl/core/region.c onto
drivers/cxl/core/trace.c due to missing commit
86954ff5032d ("cxl/region: Move cxl_trace_hpa() work to the region driver")]
Signed-off-by: Koichiro Den <koichiro.den@canonical.com>
Signed-off-by: Roxana Nicolescu <roxana.nicolescu@canonical.com>
105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
|
|
|
|
#include <cxl.h>
|
|
#include "core.h"
|
|
|
|
#define CREATE_TRACE_POINTS
|
|
#include "trace.h"
|
|
|
|
static bool cxl_is_hpa_in_chunk(u64 hpa, struct cxl_region *cxlr, int pos)
|
|
{
|
|
struct cxl_region_params *p = &cxlr->params;
|
|
int gran = p->interleave_granularity;
|
|
int ways = p->interleave_ways;
|
|
u64 offset;
|
|
|
|
/* Is the hpa in an expected chunk for its pos(-ition) */
|
|
offset = hpa - p->res->start;
|
|
offset = do_div(offset, gran * ways);
|
|
if ((offset >= pos * gran) && (offset < (pos + 1) * gran))
|
|
return true;
|
|
|
|
dev_dbg(&cxlr->dev,
|
|
"Addr trans fail: hpa 0x%llx not in expected chunk\n", hpa);
|
|
|
|
return false;
|
|
}
|
|
|
|
static u64 cxl_dpa_to_hpa(u64 dpa, struct cxl_region *cxlr,
|
|
struct cxl_endpoint_decoder *cxled)
|
|
{
|
|
struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
|
|
u64 dpa_offset, hpa_offset, bits_upper, mask_upper, hpa;
|
|
struct cxl_region_params *p = &cxlr->params;
|
|
int pos = cxled->pos;
|
|
u16 eig = 0;
|
|
u8 eiw = 0;
|
|
|
|
ways_to_eiw(p->interleave_ways, &eiw);
|
|
granularity_to_eig(p->interleave_granularity, &eig);
|
|
|
|
/*
|
|
* The device position in the region interleave set was removed
|
|
* from the offset at HPA->DPA translation. To reconstruct the
|
|
* HPA, place the 'pos' in the offset.
|
|
*
|
|
* The placement of 'pos' in the HPA is determined by interleave
|
|
* ways and granularity and is defined in the CXL Spec 3.0 Section
|
|
* 8.2.4.19.13 Implementation Note: Device Decode Logic
|
|
*/
|
|
|
|
/* Remove the dpa base */
|
|
dpa_offset = dpa - cxl_dpa_resource_start(cxled);
|
|
|
|
mask_upper = GENMASK_ULL(51, eig + 8);
|
|
|
|
if (eiw < 8) {
|
|
hpa_offset = (dpa_offset & mask_upper) << eiw;
|
|
hpa_offset |= pos << (eig + 8);
|
|
} else {
|
|
bits_upper = (dpa_offset & mask_upper) >> (eig + 8);
|
|
bits_upper = bits_upper * 3;
|
|
hpa_offset = ((bits_upper << (eiw - 8)) + pos) << (eig + 8);
|
|
}
|
|
|
|
/* The lower bits remain unchanged */
|
|
hpa_offset |= dpa_offset & GENMASK_ULL(eig + 7, 0);
|
|
|
|
/* Apply the hpa_offset to the region base address */
|
|
hpa = hpa_offset + p->res->start;
|
|
|
|
/* Root decoder translation overrides typical modulo decode */
|
|
if (cxlrd->hpa_to_spa)
|
|
hpa = cxlrd->hpa_to_spa(cxlrd, hpa);
|
|
|
|
if (hpa < p->res->start || hpa > p->res->end) {
|
|
dev_dbg(&cxlr->dev,
|
|
"Addr trans fail: hpa 0x%llx not in region\n", hpa);
|
|
return ULLONG_MAX;
|
|
}
|
|
|
|
/* Simple chunk check, by pos & gran, only applies to modulo decodes */
|
|
if (!cxlrd->hpa_to_spa && (!cxl_is_hpa_in_chunk(hpa, cxlr, pos)))
|
|
return ULLONG_MAX;
|
|
|
|
return hpa;
|
|
}
|
|
|
|
u64 cxl_trace_hpa(struct cxl_region *cxlr, struct cxl_memdev *cxlmd,
|
|
u64 dpa)
|
|
{
|
|
struct cxl_region_params *p = &cxlr->params;
|
|
struct cxl_endpoint_decoder *cxled = NULL;
|
|
|
|
for (int i = 0; i < p->nr_targets; i++) {
|
|
cxled = p->targets[i];
|
|
if (cxlmd == cxled_to_memdev(cxled))
|
|
break;
|
|
}
|
|
if (!cxled || cxlmd != cxled_to_memdev(cxled))
|
|
return ULLONG_MAX;
|
|
|
|
return cxl_dpa_to_hpa(dpa, cxlr, cxled);
|
|
}
|