11 Commits

Author SHA1 Message Date
Mahesh Patil 9f2a4ff622 NVIDIA: SAUCE: net:phy: add new speeds
BugLink: https://bugs.launchpad.net/bugs/2072591

Add speed 2500 and 25000 support in phy

http://nvbugs/4043836

Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Satish Seelamsetti <sseelamsetti@nvidia.com>
Tested-by: Satish Seelamsetti <sseelamsetti@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
2025-07-09 14:46:19 -07:00
Manish Bhardwaj 4bf3f84ca2 NVIDIA: SAUCE: net: phy: fix ubsan warning network layer
BugLink: https://bugs.launchpad.net/bugs/2072591

Using this patch we are fixing ubsan warning
in network driver layer.
[    3.807549] Call trace:
[    3.807550]  dump_backtrace+0x/0x1e0
[    3.807560]  show_stack+0x2c/0x40
[    3.807564]  dump_stack+0xd8/0x138
[    3.807570]  ubsan_epilogue+0xc/0x4c
[    3.807572]  __ubsan_handle_out_of_bounds+0x8c/0xb0
[    3.807578]  swphy_read_reg+0x388/0x590
[    3.807581]  fixed_mdio_read+0xc8/0x110
[    3.807584]  __mdiobus_read+0x40/0x1e0
[    3.807585]  mdiobus_read+0x40/0x60
[    3.807586]  get_phy_device+0x1b4/0x380
[    3.807590]  __fixed_phy_register.part.0+0x94/0x280
[    3.807592]  fixed_phy_register+0x64/0x90
[    3.807594]  of_phy_register_fixed_link+0x124/0x1b0
[    3.80759]  ether_probe+0x108c/0x38e0
[    3.807603]  platform_drv_probe+0x58/0xe0
[    3.807607]  really_probe+0x100/0x4f0
[    3.807608]  driver_probe_device+0xfc/0x180
[    3.807610]  device_driver_attach+0x74/0x80
[    3.807612]  __driver_attach+0xac/0x180
[    3.807614]  bus_for_each_dev+0x80/0xd0
[    3.807617]  driver_attach+0x30/0x40
[    3.807619]  bus_add_driver+0x16c/0x260
[    3.807621]  driver_register+0x64/0x110
[    3.807623]  __platform_driver_register+0x5c/0x70
[    3.807625]  nvethernet_driver_init+0x20/0x28
[    3.807630]  do_oneinitcall+0x50/0x370
[    3.807632]  kernel_init_freeable+0x350/0x3c8
[    3.807635]  kernel_init+0x20/0x128

http://nvbugs/4078213

Signed-off-by: Manish Bhardwaj <mbhardwaj@nvidia.com>
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Abhilash G <abhilashg@nvidia.com>
Reviewed-by: Abhilash G <abhilashg@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
2025-07-09 14:46:09 -07:00
Narayan Reddy ed47711ba2 NVIDIA: SAUCE: net: phy: add 10G, 5G for fixed link
BugLink: https://bugs.launchpad.net/bugs/2072591

Issue: currently there is no support for
10G, 5G fixed link speed

Fix: Add 10G and 5G speed entries for the
fixed link case

http://nvbugs/3978991

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
2025-07-09 14:46:07 -07:00
Russell King 4f39467e52 Update rmk's email address in various drivers
Globally update my email address in six files scattered through the
tree.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-04-21 17:50:09 +01:00
Heiner Kallweit 2441ba4806 net: phy: swphy: emulate register MII_ESTATUS
When the genphy driver binds to a swphy it will call
genphy_read_abilites that will try to read MII_ESTATUS if BMSR_ESTATEN
is set in MII_BMSR. So far this would read the default value 0xffff
and 1000FD and 1000HD are reported as supported just by chance.
Better add explicit support for emulating MII_ESTATUS.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15 11:43:48 -07:00
Heiner Kallweit 726097d6d6 net: phy: improve auto-neg emulation in swphy
Auto-neg emulation currently doesn't set bit BMCR_ANENABLE in BMCR,
add this. Users will ignore speed and duplex settings in BMCR because
we're emulating auto-neg, therefore we can remove related code.
See also following discussion [0].

[0] https://marc.info/?t=155041784900002&r=1&w=2

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-02-24 22:28:15 -08:00
Andrew Lunn a2443fd1a5 net: phy: Convert some PHY and MDIO driver files to SPDX headers
Where the license text and the MODULE_LICENSE() value agree, convert
to using an SPDX header, removing the license text.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-22 20:53:08 -08:00
Russell King 37688e3f53 phy: generate swphy registers on the fly
Generate software phy registers as and when requested, rather than
duplicating the state in fixed_phy.  This allows us to eliminate
the duplicate storage of of the same data, which is only different
in format.

As fixed_phy_update_regs() no longer updates register state, rename
it to fixed_phy_update().

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-06-27 10:40:57 -04:00
Russell King 68888ce075 phy: separate swphy state validation from register generation
Separate out the generation of MII registers from the state validation.
This allows us to simplify the error handing in fixed_phy() by allowing
earlier error detection.

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-06-27 10:40:57 -04:00
Russell King 0629bf17ea phy: convert swphy register generation to tabular form
Convert the swphy register generation to tabular form which allows us
to eliminate multiple switch() statements.  This results in a smaller
object code size, more efficient, and easier to add support for faster
speeds.

Before:

Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         00000164  00000000  00000000  00000034  2**2

   text    data     bss     dec     hex filename
    388       0       0     388     184 swphy.o

After:

Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         000000fc  00000000  00000000  00000034  2**2
  5 .rodata       00000028  00000000  00000000  00000138  2**2

   text    data     bss     dec     hex filename
    324       0       0     324     144 swphy.o

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-06-27 10:40:57 -04:00
Russell King 5ae68b0ce1 phy: move fixed_phy MII register generation to a library
Move the fixed_phy MII register generation to a library to allow other
software phy implementations to use this code.

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-06-27 10:40:57 -04:00