Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits) [ARM] 3559/1: S3C2442: core and serial port [ARM] 3557/1: S3C24XX: centralise and cleanup uart registration [ARM] 3558/1: SMDK24XX: LED platform devices [ARM] 3534/1: add spi support to lubbock platform [ARM] 3554/1: ARM: Fix dyntick locking [ARM] 3553/1: S3C24XX: earlier print of cpu idcode info [ARM] 3552/1: S3C24XX: Move VA of GPIO for low-level debug [ARM] 3551/1: S3C24XX: PM code failes to compile with CONFIG_DCACHE_WRITETHROUGH [ARM] 3550/1: OSIRIS: fix serial port map for 1:1 [ARM] 3548/1: Fix the ARMv6 CPU id in compressed/head.S [ARM] 3335/1: Old-abi Thumb sys_syscall broken [ARM] 3467/1: [3/3] Support for Philips PNX4008 platform: defconfig [ARM] 3466/1: [2/3] Support for Philips PNX4008 platform: chip support [ARM] 3465/1: [1/3] Support for Philips PNX4008 platform: headers [ARM] 3407/1: lpd7x: documetation update [ARM] 3406/1: lpd7x: compilation fix for smc91x [ARM] 3405/1: lpd7a40x: CPLD ssp driver [ARM] 3404/1: lpd7a40x: AMBA CLCD support [ARM] 3403/1: lpd7a40x: updated default configurations [ARM] 3402/1: lpd7a40x: serial driver bug fix ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,20 @@
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/* include/asm-arm/arch-lh7a40x/clocks.h
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*
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* Copyright (C) 2004 Marc Singer
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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#include <linux/config.h>
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#ifndef __ASM_ARCH_CLOCKS_H
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#define __ASM_ARCH_CLOCKS_H
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unsigned int fclkfreq_get (void);
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unsigned int hclkfreq_get (void);
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unsigned int pclkfreq_get (void);
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#endif /* _ASM_ARCH_CLOCKS_H */
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@@ -29,8 +29,7 @@
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#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
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# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */
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/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */
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# define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */
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# define IOBARRIER_VIRT 0xf0000000
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# define IOBARRIER_SIZE PAGE_SIZE
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@@ -53,6 +52,9 @@
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# define CPLD08_PHYS CPLDX_PHYS (0x08)
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# define CPLD08_VIRT CPLDX_VIRT (0x08)
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# define CPLD08_SIZE PAGE_SIZE
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# define CPLD0A_PHYS CPLDX_PHYS (0x0a)
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# define CPLD0A_VIRT CPLDX_VIRT (0x0a)
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# define CPLD0A_SIZE PAGE_SIZE
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# define CPLD0C_PHYS CPLDX_PHYS (0x0c)
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# define CPLD0C_VIRT CPLDX_VIRT (0x0c)
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# define CPLD0C_SIZE PAGE_SIZE
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@@ -84,5 +86,7 @@
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#define XTAL_IN 14745600 /* 14.7456 MHz crystal */
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#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */
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#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
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#define HCLK (99993600)
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//#define HCLK (119808000)
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#endif /* __ASM_ARCH_CONSTANTS_H */
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@@ -1,9 +1,86 @@
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/* include/asm-arm/arch-lh7a40x/dma.h
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*
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* Copyright (C) 2003 Coastal Environmental Systems
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* Copyright (C) 2005 Marc Singer
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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typedef enum {
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DMA_M2M0 = 0,
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DMA_M2M1 = 1,
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DMA_M2P0 = 2, /* Tx */
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DMA_M2P1 = 3, /* Rx */
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DMA_M2P2 = 4, /* Tx */
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DMA_M2P3 = 5, /* Rx */
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DMA_M2P4 = 6, /* Tx - AC97 */
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DMA_M2P5 = 7, /* Rx - AC97 */
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DMA_M2P6 = 8, /* Tx */
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DMA_M2P7 = 9, /* Rx */
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} dma_device_t;
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#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */
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#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
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#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
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#define DMAC_GIR_MMI1 (1<<11)
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#define DMAC_GIR_MMI0 (1<<10)
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#define DMAC_GIR_MPI8 (1<<9)
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#define DMAC_GIR_MPI9 (1<<8)
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#define DMAC_GIR_MPI6 (1<<7)
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#define DMAC_GIR_MPI7 (1<<6)
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#define DMAC_GIR_MPI4 (1<<5)
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#define DMAC_GIR_MPI5 (1<<4)
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#define DMAC_GIR_MPI2 (1<<3)
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#define DMAC_GIR_MPI3 (1<<2)
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#define DMAC_GIR_MPI0 (1<<1)
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#define DMAC_GIR_MPI1 (1<<0)
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#define DMAC_M2P0 0x0000
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#define DMAC_M2P1 0x0040
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#define DMAC_M2P2 0x0080
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#define DMAC_M2P3 0x00c0
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#define DMAC_M2P4 0x0240
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#define DMAC_M2P5 0x0200
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#define DMAC_M2P6 0x02c0
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#define DMAC_M2P7 0x0280
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#define DMAC_M2P8 0x0340
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#define DMAC_M2P9 0x0300
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#define DMAC_M2M0 0x0100
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#define DMAC_M2M1 0x0140
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#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
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#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
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#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
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#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
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#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
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#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
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#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
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#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28)
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#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30)
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#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34)
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#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38)
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#define DMAC_PCONTROL_ENABLE (1<<4)
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#define DMAC_PORT_USB 0
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#define DMAC_PORT_SDMMC 1
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#define DMAC_PORT_AC97_1 2
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#define DMAC_PORT_AC97_2 3
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#define DMAC_PORT_AC97_3 4
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#define DMAC_PORT_UART1 6
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#define DMAC_PORT_UART2 7
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#define DMAC_PORT_UART3 8
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#define DMAC_PSTATUS_CURRSTATE_SHIFT 4
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#define DMAC_PSTATUS_CURRSTATE_MASK 0x3
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#define DMAC_PSTATUS_NEXTBUF (1<<6)
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#define DMAC_PSTATUS_STALLRINT (1<<0)
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#define DMAC_INT_CHE (1<<3)
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#define DMAC_INT_NFB (1<<1)
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#define DMAC_INT_STALL (1<<0)
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@@ -10,11 +10,73 @@
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#include <asm/hardware.h>
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#include <asm/arch/irqs.h>
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# if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
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# error "LH7A400 and LH7A404 are mutually exclusive"
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# endif
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/* In order to allow there to be support for both of the processor
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classes at the same time, we make a hack here that isn't very
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pretty. At startup, the link pointed to with the
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branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
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detected as a lh7a404.
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# if defined (CONFIG_ARCH_LH7A400)
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*** FIXME: we should clean this up so that there is only one
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implementation for each CPU's design.
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*/
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#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
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.macro disable_fiq
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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branch_irq_lh7a400: b 1000f
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@ Implementation of the LH7A404 get_irqnr_and_base.
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mov \irqnr, #0 @ VIC1 irq base
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mov \base, #io_p2v(0x80000000) @ APB registers
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add \base, \base, #0x8000
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ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
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tst \tmp, #VA_VECTORED @ Direct vectored
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bne 1002f
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tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
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ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
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bne 1001f
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add \base, \base, #(0xa000 - 0x8000)
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ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
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tst \tmp, #VA_VECTORED @ Direct vectored
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bne 1002f
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ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
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mov \irqnr, #32 @ VIC2 irq base
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1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
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bcs 1008f @ Bit set; irq found
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add \irqnr, \irqnr, #1
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bne 1001b @ Until no bits
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b 1009f @ Nothing? Hmm.
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1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
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1008: movs \irqstat, #1 @ Force !Z
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str \tmp, [\base, #0x0030] @ Clear vector
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b 1009f
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@ Implementation of the LH7A400 get_irqnr_and_base.
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1000: mov \irqnr, #0
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mov \base, #io_p2v(0x80000000) @ APB registers
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ldr \irqstat, [\base, #0x500] @ PIC INTSR
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1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
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bcs 1008f @ Bit set; irq found
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add \irqnr, \irqnr, #1
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bne 1001b @ Until no bits
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b 1009f @ Nothing? Hmm.
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1008: movs \irqstat, #1 @ Force !Z
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1009:
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.endm
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#elif defined (CONFIG_ARCH_LH7A400)
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.macro disable_fiq
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.endm
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@@ -13,6 +13,8 @@
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <asm/sizes.h> /* Added for the sake of amba-clcd driver */
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#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
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#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
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@@ -53,6 +55,8 @@ typedef struct { volatile u8 offset[4096]; } __regbase8;
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#endif
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#define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s)
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#include "registers.h"
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#endif /* _ASM_ARCH_HARDWARE_H */
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@@ -154,9 +154,10 @@
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#if !defined (IRQ_GPIO0INTR)
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# define IRQ_GPIO0INTR IRQ_GPIO0FIQ
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#endif
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#define IRQ_TICK IRQ_TINTR
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#define IRQ_TICK IRQ_TINTR
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#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */
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#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */
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#define IRQ_USB IRQ_USBINTR /* USB device */
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#ifdef CONFIG_MACH_KEV7A400
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# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */
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@@ -191,6 +192,10 @@
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# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */
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#endif
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#if defined (CONFIG_MACH_LPD7A400)
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# define IRQ_TOUCH IRQ_LPD7A400_TS
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#endif
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#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD)
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#endif
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@@ -18,7 +18,7 @@
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/* Physical register base addresses */
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#define AC97_PHYS (0x80000000) /* AC97 Controller */
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#define AC97C_PHYS (0x80000000) /* AC97 Controller */
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#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
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#define USB_PHYS (0x80000200) /* USB Client */
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#define SCI_PHYS (0x80000300) /* Secure Card Interface */
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@@ -35,6 +35,8 @@
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#define RTC_PHYS (0x80000d00) /* Real-time Clock */
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#define GPIO_PHYS (0x80000e00) /* General Purpose IO */
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#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
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#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */
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#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */
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#define WDT_PHYS (0x80001400) /* Watchdog Timer */
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#define SMC_PHYS (0x80002000) /* Static Memory Controller */
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#define SDRC_PHYS (0x80002400) /* SDRAM Controller */
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@@ -43,6 +45,7 @@
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/* Physical registers of the LH7A404 */
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#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */
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#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
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#define USBH_PHYS (0x80009000) /* USB OHCI host controller */
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#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
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@@ -53,10 +56,32 @@
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/* Clock/State Controller register */
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#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
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#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
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#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
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#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
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#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
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#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
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#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
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#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
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#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
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#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
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#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
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#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
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#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
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#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
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#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
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#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
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#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
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#define CSC_PWRSR_CHIPMAN_SHIFT (24)
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#define CSC_PWRSR_CHIPMAN_MASK (0xff)
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#define CSC_PWRSR_CHIPID_SHIFT (16)
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#define CSC_PWRSR_CHIPID_MASK (0xff)
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#define CSC_USBDRESET_APBRESETREG (1<<1)
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#define CSC_USBDRESET_IORESETREG (1<<0)
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/* Interrupt Controller registers */
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@@ -109,6 +134,13 @@
|
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#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
|
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#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
|
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#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
|
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#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c)
|
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#define GPIO_PADD __REG(GPIO_PHYS + 0x10)
|
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#define GPIO_PAD __REG(GPIO_PHYS + 0x00)
|
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#define GPIO_PCD __REG(GPIO_PHYS + 0x08)
|
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#define GPIO_PCDD __REG(GPIO_PHYS + 0x18)
|
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#define GPIO_PEDD __REG(GPIO_PHYS + 0x24)
|
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#define GPIO_PED __REG(GPIO_PHYS + 0x20)
|
||||
|
||||
|
||||
/* Static Memory Controller registers */
|
||||
@@ -138,20 +170,21 @@
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
|
||||
# define CPLD_CONTROL __REG8(CPLD02_PHYS)
|
||||
# define CPLD_SPI_DATA __REG8(CPLD06_PHYS)
|
||||
# define CPLD_SPI_CONTROL __REG8(CPLD08_PHYS)
|
||||
# define CPLD_SPI_EEPROM __REG8(CPLD0A_PHYS)
|
||||
# define CPLD_INTERRUPTS __REG8(CPLD0C_PHYS) /* IRQ mask/status */
|
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# define CPLD_BOOT_MODE __REG8(CPLD0E_PHYS)
|
||||
# define CPLD_FLASH __REG8(CPLD10_PHYS)
|
||||
# define CPLD_POWER_MGMT __REG8(CPLD12_PHYS)
|
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# define CPLD_REVISION __REG8(CPLD14_PHYS)
|
||||
# define CPLD_GPIO_EXT __REG8(CPLD16_PHYS)
|
||||
# define CPLD_GPIO_DATA __REG8(CPLD18_PHYS)
|
||||
# define CPLD_GPIO_DIR __REG8(CPLD1A_PHYS)
|
||||
#endif
|
||||
|
||||
# define CPLD_CONTROL __REG16(CPLD02_PHYS)
|
||||
# define CPLD_SPI_DATA __REG16(CPLD06_PHYS)
|
||||
# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS)
|
||||
# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS)
|
||||
# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */
|
||||
# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS)
|
||||
# define CPLD_FLASH __REG16(CPLD10_PHYS)
|
||||
# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS)
|
||||
# define CPLD_REVISION __REG16(CPLD14_PHYS)
|
||||
# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS)
|
||||
# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS)
|
||||
# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS)
|
||||
|
||||
#endif
|
||||
|
||||
/* Timer registers */
|
||||
|
||||
@@ -190,4 +223,3 @@
|
||||
|
||||
|
||||
#endif /* _ASM_ARCH_REGISTERS_H */
|
||||
|
||||
|
||||
@@ -0,0 +1,71 @@
|
||||
/* ssp.h
|
||||
$Id$
|
||||
|
||||
written by Marc Singer
|
||||
6 Dec 2004
|
||||
|
||||
Copyright (C) 2004 Marc Singer
|
||||
|
||||
-----------
|
||||
DESCRIPTION
|
||||
-----------
|
||||
|
||||
This SSP header is available throughout the kernel, for this
|
||||
machine/architecture, because drivers that use it may be dispersed.
|
||||
|
||||
This file was cloned from the 7952x implementation. It would be
|
||||
better to share them, but we're taking an easier approach for the
|
||||
time being.
|
||||
|
||||
*/
|
||||
|
||||
#if !defined (__SSP_H__)
|
||||
# define __SSP_H__
|
||||
|
||||
/* ----- Includes */
|
||||
|
||||
/* ----- Types */
|
||||
|
||||
struct ssp_driver {
|
||||
int (*init) (void);
|
||||
void (*exit) (void);
|
||||
void (*acquire) (void);
|
||||
void (*release) (void);
|
||||
int (*configure) (int device, int mode, int speed,
|
||||
int frame_size_write, int frame_size_read);
|
||||
void (*chip_select) (int enable);
|
||||
void (*set_callbacks) (void* handle,
|
||||
irqreturn_t (*callback_tx)(void*),
|
||||
irqreturn_t (*callback_rx)(void*));
|
||||
void (*enable) (void);
|
||||
void (*disable) (void);
|
||||
// int (*save_state) (void*);
|
||||
// void (*restore_state) (void*);
|
||||
int (*read) (void);
|
||||
int (*write) (u16 data);
|
||||
int (*write_read) (u16 data);
|
||||
void (*flush) (void);
|
||||
void (*write_async) (void* pv, size_t cb);
|
||||
size_t (*write_pos) (void);
|
||||
};
|
||||
|
||||
/* These modes are only available on the LH79524 */
|
||||
#define SSP_MODE_SPI (1)
|
||||
#define SSP_MODE_SSI (2)
|
||||
#define SSP_MODE_MICROWIRE (3)
|
||||
#define SSP_MODE_I2S (4)
|
||||
|
||||
/* CPLD SPI devices */
|
||||
#define DEVICE_EEPROM 0 /* Configuration eeprom */
|
||||
#define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */
|
||||
#define DEVICE_CODEC 2 /* Audio codec */
|
||||
#define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */
|
||||
|
||||
/* ----- Globals */
|
||||
|
||||
/* ----- Prototypes */
|
||||
|
||||
//extern struct ssp_driver lh79520_i2s_driver;
|
||||
extern struct ssp_driver lh7a400_cpld_ssp_driver;
|
||||
|
||||
#endif /* __SSP_H__ */
|
||||
@@ -16,7 +16,7 @@
|
||||
#ifndef UART_R_STATUS
|
||||
# define UART_R_STATUS (0x10)
|
||||
#endif
|
||||
#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
|
||||
#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
|
||||
|
||||
/* Access UART with physical addresses before MMU is setup */
|
||||
#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* include/asm-arm/arch-pnx4008/clock.h
|
||||
*
|
||||
* Clock control driver for PNX4008 - header file
|
||||
*
|
||||
* Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#ifndef __PNX4008_CLOCK_H__
|
||||
#define __PNX4008_CLOCK_H__
|
||||
|
||||
struct module;
|
||||
struct clk;
|
||||
|
||||
#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
|
||||
#define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40)
|
||||
#define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44)
|
||||
#define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48)
|
||||
#define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c)
|
||||
#define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50)
|
||||
#define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58)
|
||||
#define USBCTRL_REG (PWRMAN_VA_BASE + 0x64)
|
||||
#define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68)
|
||||
#define MSCTRL_REG (PWRMAN_VA_BASE + 0x80)
|
||||
#define BTCLKCTRL (PWRMAN_VA_BASE + 0x84)
|
||||
#define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90)
|
||||
#define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac)
|
||||
#define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0)
|
||||
#define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4)
|
||||
#define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8)
|
||||
#define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4)
|
||||
#define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8)
|
||||
#define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0)
|
||||
#define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4)
|
||||
#define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8)
|
||||
#define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec)
|
||||
#define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc)
|
||||
|
||||
#define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
|
||||
#define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60)
|
||||
#define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64)
|
||||
#define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68)
|
||||
#define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C)
|
||||
|
||||
#define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
|
||||
|
||||
#define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE)
|
||||
|
||||
#define CLK_RATE_13MHZ 13000
|
||||
#define CLK_RATE_1MHZ 1000
|
||||
#define CLK_RATE_208MHZ 208000
|
||||
#define CLK_RATE_48MHZ 48000
|
||||
#define CLK_RATE_32KHZ 32
|
||||
|
||||
#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,27 @@
|
||||
/* linux/include/asm-arm/arch-pnx4008/debug-macro.S
|
||||
*
|
||||
* Debugging macro include header
|
||||
*
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
.macro addruart,rx
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ MMU enabled?
|
||||
mov \rx, #0x00090000
|
||||
addeq \rx, \rx, #0x40000000
|
||||
addne \rx, \rx, #0xf4000000
|
||||
.endm
|
||||
|
||||
.macro senduart,rd,rx
|
||||
strb \rd, [\rx, #0x0]
|
||||
.endm
|
||||
|
||||
#define UART_SHIFT 2
|
||||
#include <asm/hardware/debug-8250.S>
|
||||
@@ -0,0 +1,162 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-pnx4008/dma.h
|
||||
*
|
||||
* PNX4008 DMA header file
|
||||
*
|
||||
* Author: Vitaly Wool
|
||||
* Copyright: MontaVista Software Inc. (c) 2005
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_DMA_H
|
||||
#define __ASM_ARCH_DMA_H
|
||||
|
||||
#include "platform.h"
|
||||
|
||||
#define MAX_DMA_ADDRESS 0xffffffff
|
||||
|
||||
#define MAX_DMA_CHANNELS 8
|
||||
|
||||
#define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
|
||||
#define DMAC_INT_STAT (DMAC_BASE + 0x0000)
|
||||
#define DMAC_INT_TC_STAT (DMAC_BASE + 0x0004)
|
||||
#define DMAC_INT_TC_CLEAR (DMAC_BASE + 0x0008)
|
||||
#define DMAC_INT_ERR_STAT (DMAC_BASE + 0x000c)
|
||||
#define DMAC_INT_ERR_CLEAR (DMAC_BASE + 0x0010)
|
||||
#define DMAC_SOFT_SREQ (DMAC_BASE + 0x0024)
|
||||
#define DMAC_CONFIG (DMAC_BASE + 0x0030)
|
||||
#define DMAC_Cx_SRC_ADDR(c) (DMAC_BASE + 0x0100 + (c) * 0x20)
|
||||
#define DMAC_Cx_DEST_ADDR(c) (DMAC_BASE + 0x0104 + (c) * 0x20)
|
||||
#define DMAC_Cx_LLI(c) (DMAC_BASE + 0x0108 + (c) * 0x20)
|
||||
#define DMAC_Cx_CONTROL(c) (DMAC_BASE + 0x010c + (c) * 0x20)
|
||||
#define DMAC_Cx_CONFIG(c) (DMAC_BASE + 0x0110 + (c) * 0x20)
|
||||
|
||||
enum {
|
||||
WIDTH_BYTE = 0,
|
||||
WIDTH_HWORD,
|
||||
WIDTH_WORD
|
||||
};
|
||||
|
||||
enum {
|
||||
FC_MEM2MEM_DMA,
|
||||
FC_MEM2PER_DMA,
|
||||
FC_PER2MEM_DMA,
|
||||
FC_PER2PER_DMA,
|
||||
FC_PER2PER_DPER,
|
||||
FC_MEM2PER_PER,
|
||||
FC_PER2MEM_PER,
|
||||
FC_PER2PER_SPER
|
||||
};
|
||||
|
||||
enum {
|
||||
DMA_INT_UNKNOWN = 0,
|
||||
DMA_ERR_INT = 1,
|
||||
DMA_TC_INT = 2,
|
||||
};
|
||||
|
||||
enum {
|
||||
DMA_BUFFER_ALLOCATED = 1,
|
||||
DMA_HAS_LL = 2,
|
||||
};
|
||||
|
||||
enum {
|
||||
PER_CAM_DMA_1 = 0,
|
||||
PER_NDF_FLASH = 1,
|
||||
PER_MBX_SLAVE_FIFO = 2,
|
||||
PER_SPI2_REC_XMIT = 3,
|
||||
PER_MS_SD_RX_XMIT = 4,
|
||||
PER_HS_UART_1_XMIT = 5,
|
||||
PER_HS_UART_1_RX = 6,
|
||||
PER_HS_UART_2_XMIT = 7,
|
||||
PER_HS_UART_2_RX = 8,
|
||||
PER_HS_UART_7_XMIT = 9,
|
||||
PER_HS_UART_7_RX = 10,
|
||||
PER_SPI1_REC_XMIT = 11,
|
||||
PER_MLC_NDF_SREC = 12,
|
||||
PER_CAM_DMA_2 = 13,
|
||||
PER_PRNG_INFIFO = 14,
|
||||
PER_PRNG_OUTFIFO = 15,
|
||||
};
|
||||
|
||||
struct pnx4008_dma_ch_ctrl {
|
||||
int tc_mask;
|
||||
int cacheable;
|
||||
int bufferable;
|
||||
int priv_mode;
|
||||
int di;
|
||||
int si;
|
||||
int dest_ahb1;
|
||||
int src_ahb1;
|
||||
int dwidth;
|
||||
int swidth;
|
||||
int dbsize;
|
||||
int sbsize;
|
||||
int tr_size;
|
||||
};
|
||||
|
||||
struct pnx4008_dma_ch_config {
|
||||
int halt;
|
||||
int active;
|
||||
int lock;
|
||||
int itc;
|
||||
int ie;
|
||||
int flow_cntrl;
|
||||
int dest_per;
|
||||
int src_per;
|
||||
};
|
||||
|
||||
struct pnx4008_dma_ll {
|
||||
unsigned long src_addr;
|
||||
unsigned long dest_addr;
|
||||
u32 next_dma;
|
||||
unsigned long ch_ctrl;
|
||||
struct pnx4008_dma_ll *next;
|
||||
int flags;
|
||||
void *alloc_data;
|
||||
int (*free) (void *);
|
||||
};
|
||||
|
||||
struct pnx4008_dma_config {
|
||||
int is_ll;
|
||||
unsigned long src_addr;
|
||||
unsigned long dest_addr;
|
||||
unsigned long ch_ctrl;
|
||||
unsigned long ch_cfg;
|
||||
struct pnx4008_dma_ll *ll;
|
||||
u32 ll_dma;
|
||||
int flags;
|
||||
void *alloc_data;
|
||||
int (*free) (void *);
|
||||
};
|
||||
|
||||
extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
|
||||
extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
|
||||
extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
|
||||
|
||||
extern int pnx4008_request_channel(char *, int,
|
||||
void (*)(int, int, void *, struct pt_regs *),
|
||||
void *);
|
||||
extern void pnx4008_free_channel(int);
|
||||
extern int pnx4008_config_dma(int, int, int);
|
||||
extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
|
||||
unsigned long *);
|
||||
extern int pnx4008_dma_parse_control(unsigned long,
|
||||
struct pnx4008_dma_ch_ctrl *);
|
||||
extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
|
||||
unsigned long *);
|
||||
extern int pnx4008_dma_parse_config(unsigned long,
|
||||
struct pnx4008_dma_ch_config *);
|
||||
extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
|
||||
extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
|
||||
extern int pnx4008_dma_ch_enable(int);
|
||||
extern int pnx4008_dma_ch_disable(int);
|
||||
extern int pnx4008_dma_ch_enabled(int);
|
||||
extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
|
||||
struct pnx4008_dma_ch_ctrl *);
|
||||
extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
|
||||
struct pnx4008_dma_ch_ctrl *);
|
||||
|
||||
#endif /* _ASM_ARCH_DMA_H */
|
||||
@@ -0,0 +1,121 @@
|
||||
/*
|
||||
* include/asm-arm/arch-pnx4008/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for PNX4008-based platforms
|
||||
*
|
||||
* 2005-2006 (c) MontaVista Software, Inc.
|
||||
* Author: Vitaly Wool <vwool@ru.mvista.com>
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include "platform.h"
|
||||
|
||||
#define IO_BASE 0xF0000000
|
||||
#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
|
||||
|
||||
#define INTRC_MASK 0x00
|
||||
#define INTRC_RAW_STAT 0x04
|
||||
#define INTRC_STAT 0x08
|
||||
#define INTRC_POLAR 0x0C
|
||||
#define INTRC_ACT_TYPE 0x10
|
||||
#define INTRC_TYPE 0x14
|
||||
|
||||
#define SIC1_BASE_INT 32
|
||||
#define SIC2_BASE_INT 64
|
||||
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
/* decode the MIC interrupt numbers */
|
||||
ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
|
||||
ldr \irqstat, [\base, #INTRC_STAT]
|
||||
|
||||
cmp \irqstat,#1<<16
|
||||
movhs \irqnr,#16
|
||||
movlo \irqnr,#0
|
||||
movhs \irqstat,\irqstat,lsr#16
|
||||
cmp \irqstat,#1<<8
|
||||
addhs \irqnr,\irqnr,#8
|
||||
movhs \irqstat,\irqstat,lsr#8
|
||||
cmp \irqstat,#1<<4
|
||||
addhs \irqnr,\irqnr,#4
|
||||
movhs \irqstat,\irqstat,lsr#4
|
||||
cmp \irqstat,#1<<2
|
||||
addhs \irqnr,\irqnr,#2
|
||||
movhs \irqstat,\irqstat,lsr#2
|
||||
cmp \irqstat,#1<<1
|
||||
addhs \irqnr,\irqnr,#1
|
||||
|
||||
/* was there an interrupt ? if not then drop out with EQ status */
|
||||
teq \irqstat,#0
|
||||
beq 1003f
|
||||
|
||||
/* and now check for extended IRQ reasons */
|
||||
cmp \irqnr,#1
|
||||
bls 1003f
|
||||
cmp \irqnr,#30
|
||||
blo 1002f
|
||||
|
||||
/* IRQ 31,30 : High priority cascade IRQ handle */
|
||||
/* read the correct SIC */
|
||||
/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
|
||||
/* set the base IRQ number */
|
||||
ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
|
||||
moveq \irqnr,#SIC1_BASE_INT
|
||||
ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
|
||||
movne \irqnr,#SIC2_BASE_INT
|
||||
ldr \irqstat, [\base, #INTRC_STAT]
|
||||
ldr \tmp, [\base, #INTRC_TYPE]
|
||||
/* and with inverted mask : low priority interrupts */
|
||||
and \irqstat,\irqstat,\tmp
|
||||
b 1004f
|
||||
|
||||
1003:
|
||||
/* IRQ 1,0 : Low priority cascade IRQ handle */
|
||||
/* read the correct SIC */
|
||||
/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
|
||||
/* read the correct SIC */
|
||||
/* set the base IRQ number */
|
||||
ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
|
||||
movne \irqnr,#SIC1_BASE_INT
|
||||
ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
|
||||
moveq \irqnr,#SIC2_BASE_INT
|
||||
ldr \irqstat, [\base, #INTRC_STAT]
|
||||
ldr \tmp, [\base, #INTRC_TYPE]
|
||||
/* and with inverted mask : low priority interrupts */
|
||||
bic \irqstat,\irqstat,\tmp
|
||||
|
||||
1004:
|
||||
|
||||
cmp \irqstat,#1<<16
|
||||
addhs \irqnr,\irqnr,#16
|
||||
movhs \irqstat,\irqstat,lsr#16
|
||||
cmp \irqstat,#1<<8
|
||||
addhs \irqnr,\irqnr,#8
|
||||
movhs \irqstat,\irqstat,lsr#8
|
||||
cmp \irqstat,#1<<4
|
||||
addhs \irqnr,\irqnr,#4
|
||||
movhs \irqstat,\irqstat,lsr#4
|
||||
cmp \irqstat,#1<<2
|
||||
addhs \irqnr,\irqnr,#2
|
||||
movhs \irqstat,\irqstat,lsr#2
|
||||
cmp \irqstat,#1<<1
|
||||
addhs \irqnr,\irqnr,#1
|
||||
|
||||
|
||||
/* is irqstat not zero */
|
||||
|
||||
1002:
|
||||
/* we assert that irqstat is not equal to zero and return ne status if true*/
|
||||
teq \irqstat,#0
|
||||
1003:
|
||||
.endm
|
||||
|
||||
|
||||
.macro irq_prio_table
|
||||
.endm
|
||||
|
||||
|
||||
@@ -0,0 +1,139 @@
|
||||
/*
|
||||
* include/asm-arm/arch-pnx4008/gpio.h
|
||||
*
|
||||
* PNX4008 GPIO driver - header file
|
||||
*
|
||||
* Author: Dmitry Chigirev <source@mvista.com>
|
||||
*
|
||||
* Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
|
||||
* Copyright (c) 2005 Koninklijke Philips Electronics N.V.
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#ifndef _PNX4008_GPIO_H_
|
||||
#define _PNX4008_GPIO_H_
|
||||
|
||||
|
||||
/* Block numbers */
|
||||
#define GPIO_IN (0)
|
||||
#define GPIO_OUT (0x100)
|
||||
#define GPIO_BID (0x200)
|
||||
#define GPIO_RAM (0x300)
|
||||
#define GPIO_MUX (0x400)
|
||||
|
||||
#define GPIO_TYPE_MASK(K) ((K) & 0x700)
|
||||
|
||||
/* INPUT GPIOs */
|
||||
/* GPI */
|
||||
#define GPI_00 (GPIO_IN | 0)
|
||||
#define GPI_01 (GPIO_IN | 1)
|
||||
#define GPI_02 (GPIO_IN | 2)
|
||||
#define GPI_03 (GPIO_IN | 3)
|
||||
#define GPI_04 (GPIO_IN | 4)
|
||||
#define GPI_05 (GPIO_IN | 5)
|
||||
#define GPI_06 (GPIO_IN | 6)
|
||||
#define GPI_07 (GPIO_IN | 7)
|
||||
#define GPI_08 (GPIO_IN | 8)
|
||||
#define GPI_09 (GPIO_IN | 9)
|
||||
#define U1_RX (GPIO_IN | 15)
|
||||
#define U2_HTCS (GPIO_IN | 16)
|
||||
#define U2_RX (GPIO_IN | 17)
|
||||
#define U3_RX (GPIO_IN | 18)
|
||||
#define U4_RX (GPIO_IN | 19)
|
||||
#define U5_RX (GPIO_IN | 20)
|
||||
#define U6_IRRX (GPIO_IN | 21)
|
||||
#define U7_HCTS (GPIO_IN | 22)
|
||||
#define U7_RX (GPIO_IN | 23)
|
||||
/* MISC IN */
|
||||
#define SPI1_DATIN (GPIO_IN | 25)
|
||||
#define DISP_SYNC (GPIO_IN | 26)
|
||||
#define SPI2_DATIN (GPIO_IN | 27)
|
||||
#define GPI_11 (GPIO_IN | 28)
|
||||
|
||||
#define GPIO_IN_MASK 0x1eff83ff
|
||||
|
||||
/* OUTPUT GPIOs */
|
||||
/* GPO */
|
||||
#define GPO_00 (GPIO_OUT | 0)
|
||||
#define GPO_01 (GPIO_OUT | 1)
|
||||
#define GPO_02 (GPIO_OUT | 2)
|
||||
#define GPO_03 (GPIO_OUT | 3)
|
||||
#define GPO_04 (GPIO_OUT | 4)
|
||||
#define GPO_05 (GPIO_OUT | 5)
|
||||
#define GPO_06 (GPIO_OUT | 6)
|
||||
#define GPO_07 (GPIO_OUT | 7)
|
||||
#define GPO_08 (GPIO_OUT | 8)
|
||||
#define GPO_09 (GPIO_OUT | 9)
|
||||
#define GPO_10 (GPIO_OUT | 10)
|
||||
#define GPO_11 (GPIO_OUT | 11)
|
||||
#define GPO_12 (GPIO_OUT | 12)
|
||||
#define GPO_13 (GPIO_OUT | 13)
|
||||
#define GPO_14 (GPIO_OUT | 14)
|
||||
#define GPO_15 (GPIO_OUT | 15)
|
||||
#define GPO_16 (GPIO_OUT | 16)
|
||||
#define GPO_17 (GPIO_OUT | 17)
|
||||
#define GPO_18 (GPIO_OUT | 18)
|
||||
#define GPO_19 (GPIO_OUT | 19)
|
||||
#define GPO_20 (GPIO_OUT | 20)
|
||||
#define GPO_21 (GPIO_OUT | 21)
|
||||
#define GPO_22 (GPIO_OUT | 22)
|
||||
#define GPO_23 (GPIO_OUT | 23)
|
||||
|
||||
#define GPIO_OUT_MASK 0xffffff
|
||||
|
||||
/* BIDIRECTIONAL GPIOs */
|
||||
/* RAM pins */
|
||||
#define RAM_D19 (GPIO_RAM | 0)
|
||||
#define RAM_D20 (GPIO_RAM | 1)
|
||||
#define RAM_D21 (GPIO_RAM | 2)
|
||||
#define RAM_D22 (GPIO_RAM | 3)
|
||||
#define RAM_D23 (GPIO_RAM | 4)
|
||||
#define RAM_D24 (GPIO_RAM | 5)
|
||||
#define RAM_D25 (GPIO_RAM | 6)
|
||||
#define RAM_D26 (GPIO_RAM | 7)
|
||||
#define RAM_D27 (GPIO_RAM | 8)
|
||||
#define RAM_D28 (GPIO_RAM | 9)
|
||||
#define RAM_D29 (GPIO_RAM | 10)
|
||||
#define RAM_D30 (GPIO_RAM | 11)
|
||||
#define RAM_D31 (GPIO_RAM | 12)
|
||||
|
||||
#define GPIO_RAM_MASK 0x1fff
|
||||
|
||||
/* I/O pins */
|
||||
#define GPIO_00 (GPIO_BID | 25)
|
||||
#define GPIO_01 (GPIO_BID | 26)
|
||||
#define GPIO_02 (GPIO_BID | 27)
|
||||
#define GPIO_03 (GPIO_BID | 28)
|
||||
#define GPIO_04 (GPIO_BID | 29)
|
||||
#define GPIO_05 (GPIO_BID | 30)
|
||||
|
||||
#define GPIO_BID_MASK 0x7e000000
|
||||
|
||||
/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
|
||||
#define GPIO_SDRAM_SEL (GPIO_MUX | 3)
|
||||
|
||||
#define GPIO_MUX_MASK 0x8
|
||||
|
||||
/* Extraction/assembly macros */
|
||||
#define GPIO_BIT_MASK(K) ((K) & 0x1F)
|
||||
#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
|
||||
#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
|
||||
#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
|
||||
#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
|
||||
#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
|
||||
#define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
|
||||
|
||||
extern int pnx4008_gpio_register_pin(unsigned short pin);
|
||||
extern int pnx4008_gpio_unregister_pin(unsigned short pin);
|
||||
extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
|
||||
extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
|
||||
extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
|
||||
extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
|
||||
extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
|
||||
extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
|
||||
|
||||
#endif /* _PNX4008_GPIO_H_ */
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-pnx4008/hardware.h
|
||||
*
|
||||
* Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/arch/platform.h>
|
||||
|
||||
/* Start of virtual addresses for IO devices */
|
||||
#define IO_BASE 0xF0000000
|
||||
|
||||
/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
|
||||
#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* include/asm-arm/arch-pnx4008/io.h
|
||||
*
|
||||
* Author: Dmitry Chigirev <chigirev@ru.mvista.com>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#define __io(a) ((void __iomem *)(a))
|
||||
#define __mem_pci(a) (a)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* include/asm-arm/arch-pnx4008/irq.h
|
||||
*
|
||||
* PNX4008 IRQ controller driver - header file
|
||||
* this one is used in entry-arnv.S as well so it cannot contain C code
|
||||
*
|
||||
* Copyright (c) 2005 Philips Semiconductors
|
||||
* Copyright (c) 2005 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#ifndef __PNX4008_IRQ_H__
|
||||
#define __PNX4008_IRQ_H__
|
||||
|
||||
#define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
|
||||
#define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
|
||||
#define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
|
||||
|
||||
/* Manual: Chapter 20, page 195 */
|
||||
|
||||
#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
|
||||
|
||||
#define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
|
||||
#define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
|
||||
#define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
|
||||
#define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
|
||||
#define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
|
||||
#define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
|
||||
|
||||
#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
|
||||
|
||||
#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
|
||||
#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
|
||||
#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
|
||||
#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
|
||||
|
||||
extern void __init pnx4008_init_irq(void);
|
||||
|
||||
#endif /* __PNX4008_IRQ_H__ */
|
||||
@@ -0,0 +1,215 @@
|
||||
/*
|
||||
* include/asm-arm/arch-pnx4008/irqs.h
|
||||
*
|
||||
* PNX4008 IRQ controller driver - header file
|
||||
*
|
||||
* Author: Dmitry Chigirev <source@mvista.com>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#ifndef __PNX4008_IRQS_h__
|
||||
#define __PNX4008_IRQS_h__
|
||||
|
||||
#define NR_IRQS 96
|
||||
|
||||
/*Manual: table 259, page 199*/
|
||||
|
||||
/*SUB2 Interrupt Routing (SIC2)*/
|
||||
|
||||
#define SIC2_BASE_INT 64
|
||||
|
||||
#define CLK_SWITCH_ARM_INT 95 /*manual: Clkswitch ARM */
|
||||
#define CLK_SWITCH_DSP_INT 94 /*manual: ClkSwitch DSP */
|
||||
#define CLK_SWITCH_AUD_INT 93 /*manual: Clkswitch AUD */
|
||||
#define GPI_06_INT 92
|
||||
#define GPI_05_INT 91
|
||||
#define GPI_04_INT 90
|
||||
#define GPI_03_INT 89
|
||||
#define GPI_02_INT 88
|
||||
#define GPI_01_INT 87
|
||||
#define GPI_00_INT 86
|
||||
#define BT_CLKREQ_INT 85
|
||||
#define SPI1_DATIN_INT 84
|
||||
#define U5_RX_INT 83
|
||||
#define SDIO_INT_N 82
|
||||
#define CAM_HS_INT 81
|
||||
#define CAM_VS_INT 80
|
||||
#define GPI_07_INT 79
|
||||
#define DISP_SYNC_INT 78
|
||||
#define DSP_INT8 77
|
||||
#define U7_HCTS_INT 76
|
||||
#define GPI_10_INT 75
|
||||
#define GPI_09_INT 74
|
||||
#define GPI_08_INT 73
|
||||
#define DSP_INT7 72
|
||||
#define U2_HCTS_INT 71
|
||||
#define SPI2_DATIN_INT 70
|
||||
#define GPIO_05_INT 69
|
||||
#define GPIO_04_INT 68
|
||||
#define GPIO_03_INT 67
|
||||
#define GPIO_02_INT 66
|
||||
#define GPIO_01_INT 65
|
||||
#define GPIO_00_INT 64
|
||||
|
||||
/*Manual: table 258, page 198*/
|
||||
|
||||
/*SUB1 Interrupt Routing (SIC1)*/
|
||||
|
||||
#define SIC1_BASE_INT 32
|
||||
|
||||
#define USB_I2C_INT 63
|
||||
#define USB_DEV_HP_INT 62
|
||||
#define USB_DEV_LP_INT 61
|
||||
#define USB_DEV_DMA_INT 60
|
||||
#define USB_HOST_INT 59
|
||||
#define USB_OTG_ATX_INT_N 58
|
||||
#define USB_OTG_TIMER_INT 57
|
||||
#define SW_INT 56
|
||||
#define SPI1_INT 55
|
||||
#define KEY_IRQ 54
|
||||
#define DSP_M_INT 53
|
||||
#define RTC_INT 52
|
||||
#define I2C_1_INT 51
|
||||
#define I2C_2_INT 50
|
||||
#define PLL1_LOCK_INT 49
|
||||
#define PLL2_LOCK_INT 48
|
||||
#define PLL3_LOCK_INT 47
|
||||
#define PLL4_LOCK_INT 46
|
||||
#define PLL5_LOCK_INT 45
|
||||
#define SPI2_INT 44
|
||||
#define DSP_INT1 43
|
||||
#define DSP_INT2 42
|
||||
#define DSP_TDM_INT2 41
|
||||
#define TS_AUX_INT 40
|
||||
#define TS_IRQ 39
|
||||
#define TS_P_INT 38
|
||||
#define UOUT1_TO_PAD_INT 37
|
||||
#define GPI_11_INT 36
|
||||
#define DSP_INT4 35
|
||||
#define JTAG_COMM_RX_INT 34
|
||||
#define JTAG_COMM_TX_INT 33
|
||||
#define DSP_INT3 32
|
||||
|
||||
/*Manual: table 257, page 197*/
|
||||
|
||||
/*MAIN Interrupt Routing*/
|
||||
|
||||
#define MAIN_BASE_INT 0
|
||||
|
||||
#define SUB2_FIQ_N 31 /*active low */
|
||||
#define SUB1_FIQ_N 30 /*active low */
|
||||
#define JPEG_INT 29
|
||||
#define DMA_INT 28
|
||||
#define MSTIMER_INT 27
|
||||
#define IIR1_INT 26
|
||||
#define IIR2_INT 25
|
||||
#define IIR7_INT 24
|
||||
#define DSP_TDM_INT0 23
|
||||
#define DSP_TDM_INT1 22
|
||||
#define DSP_P_INT 21
|
||||
#define DSP_INT0 20
|
||||
#define DUM_INT 19
|
||||
#define UOUT0_TO_PAD_INT 18
|
||||
#define MP4_ENC_INT 17
|
||||
#define MP4_DEC_INT 16
|
||||
#define SD0_INT 15
|
||||
#define MBX_INT 14
|
||||
#define SD1_INT 13
|
||||
#define MS_INT_N 12
|
||||
#define FLASH_INT 11 /*NAND*/
|
||||
#define IIR6_INT 10
|
||||
#define IIR5_INT 9
|
||||
#define IIR4_INT 8
|
||||
#define IIR3_INT 7
|
||||
#define WATCH_INT 6
|
||||
#define HSTIMER_INT 5
|
||||
#define ARCH_TIMER_IRQ HSTIMER_INT
|
||||
#define CAM_INT 4
|
||||
#define PRNG_INT 3
|
||||
#define CRYPTO_INT 2
|
||||
#define SUB2_IRQ_N 1 /*active low */
|
||||
#define SUB1_IRQ_N 0 /*active low */
|
||||
|
||||
#define PNX4008_IRQ_TYPES \
|
||||
{ /*IRQ #'s: */ \
|
||||
IRQT_LOW, IRQT_LOW, IRQT_LOW, IRQT_HIGH, /* 0, 1, 2, 3 */ \
|
||||
IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 4, 5, 6, 7 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 8, 9,10,11 */ \
|
||||
IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 12,13,14,15 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 16,17,18,19 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 20,21,22,23 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 24,25,26,27 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 28,29,30,31 */ \
|
||||
IRQT_HIGH, IRQT_LOW, IRQT_HIGH, IRQT_HIGH, /* 32,33,34,35 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_FALLING, IRQT_HIGH, /* 36,37,38,39 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 40,41,42,43 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 44,45,46,47 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 48,49,50,51 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 52,53,54,55 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_HIGH, /* 56,57,58,59 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 60,61,62,63 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 64,65,66,67 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 68,69,70,71 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 72,73,74,75 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 76,77,78,79 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 80,81,82,83 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 84,85,86,87 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 88,89,90,91 */ \
|
||||
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 92,93,94,95 */ \
|
||||
}
|
||||
|
||||
/* Start Enable Pin Interrupts - table 58 page 66 */
|
||||
|
||||
#define SE_PIN_BASE_INT 32
|
||||
|
||||
#define SE_U7_RX_INT 63
|
||||
#define SE_U7_HCTS_INT 62
|
||||
#define SE_BT_CLKREQ_INT 61
|
||||
#define SE_U6_IRRX_INT 60
|
||||
/*59 unused*/
|
||||
#define SE_U5_RX_INT 58
|
||||
#define SE_GPI_11_INT 57
|
||||
#define SE_U3_RX_INT 56
|
||||
#define SE_U2_HCTS_INT 55
|
||||
#define SE_U2_RX_INT 54
|
||||
#define SE_U1_RX_INT 53
|
||||
#define SE_DISP_SYNC_INT 52
|
||||
/*51 unused*/
|
||||
#define SE_SDIO_INT_N 50
|
||||
#define SE_MSDIO_START_INT 49
|
||||
#define SE_GPI_06_INT 48
|
||||
#define SE_GPI_05_INT 47
|
||||
#define SE_GPI_04_INT 46
|
||||
#define SE_GPI_03_INT 45
|
||||
#define SE_GPI_02_INT 44
|
||||
#define SE_GPI_01_INT 43
|
||||
#define SE_GPI_00_INT 42
|
||||
#define SE_SYSCLKEN_PIN_INT 41
|
||||
#define SE_SPI1_DATAIN_INT 40
|
||||
#define SE_GPI_07_INT 39
|
||||
#define SE_SPI2_DATAIN_INT 38
|
||||
#define SE_GPI_10_INT 37
|
||||
#define SE_GPI_09_INT 36
|
||||
#define SE_GPI_08_INT 35
|
||||
/*34-32 unused*/
|
||||
|
||||
/* Start Enable Internal Interrupts - table 57 page 65 */
|
||||
|
||||
#define SE_INT_BASE_INT 0
|
||||
|
||||
#define SE_TS_IRQ 31
|
||||
#define SE_TS_P_INT 30
|
||||
#define SE_TS_AUX_INT 29
|
||||
/*27-28 unused*/
|
||||
#define SE_USB_AHB_NEED_CLK_INT 26
|
||||
#define SE_MSTIMER_INT 25
|
||||
#define SE_RTC_INT 24
|
||||
#define SE_USB_NEED_CLK_INT 23
|
||||
#define SE_USB_INT 22
|
||||
#define SE_USB_I2C_INT 21
|
||||
#define SE_USB_OTG_TIMER_INT 20
|
||||
|
||||
#endif /* __PNX4008_IRQS_h__ */
|
||||
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-pnx4008/memory.h
|
||||
*
|
||||
* Copyright (c) 2005 Philips Semiconductors
|
||||
* Copyright (c) 2005 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
/*
|
||||
* Physical DRAM offset.
|
||||
*/
|
||||
#define PHYS_OFFSET (0x80000000)
|
||||
|
||||
#define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
|
||||
#define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-pnx4008/param.h
|
||||
*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#define HZ 100
|
||||
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* include/asm-arm/arch-pnx4008/platfrom.h
|
||||
*
|
||||
* PNX4008 Base addresses - header file
|
||||
*
|
||||
* Author: Dmitry Chigirev <source@mvista.com>
|
||||
*
|
||||
* Based on reference code received from Philips:
|
||||
* Copyright (C) 2003 Philips Semiconductors
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __ASM_ARCH_PLATFORM_H__
|
||||
#define __ASM_ARCH_PLATFORM_H__
|
||||
|
||||
#define PNX4008_IRAM_BASE 0x08000000
|
||||
#define PNX4008_IRAM_SIZE 0x00010000
|
||||
#define PNX4008_YUV_SLAVE_BASE 0x10000000
|
||||
#define PNX4008_DUM_SLAVE_BASE 0x18000000
|
||||
#define PNX4008_NDF_FLASH_BASE 0x20020000
|
||||
#define PNX4008_SPI1_BASE 0x20088000
|
||||
#define PNX4008_SPI2_BASE 0x20090000
|
||||
#define PNX4008_SD_CONFIG_BASE 0x20098000
|
||||
#define PNX4008_FLASH_DATA 0x200B0000
|
||||
#define PNX4008_MLC_FLASH_BASE 0x200B8000
|
||||
#define PNX4008_JPEG_CONFIG_BASE 0x300A0000
|
||||
#define PNX4008_DMA_CONFIG_BASE 0x31000000
|
||||
#define PNX4008_USB_CONFIG_BASE 0x31020000
|
||||
#define PNX4008_SDRAM_CFG_BASE 0x31080000
|
||||
#define PNX4008_AHB2FAB_BASE 0x40000000
|
||||
#define PNX4008_PWRMAN_BASE 0x40004000
|
||||
#define PNX4008_INTCTRLMIC_BASE 0x40008000
|
||||
#define PNX4008_INTCTRLSIC1_BASE 0x4000C000
|
||||
#define PNX4008_INTCTRLSIC2_BASE 0x40010000
|
||||
#define PNX4008_HSUART1_BASE 0x40014000
|
||||
#define PNX4008_HSUART2_BASE 0x40018000
|
||||
#define PNX4008_HSUART7_BASE 0x4001C000
|
||||
#define PNX4008_RTC_BASE 0x40024000
|
||||
#define PNX4008_PIO_BASE 0x40028000
|
||||
#define PNX4008_MSTIMER_BASE 0x40034000
|
||||
#define PNX4008_HSTIMER_BASE 0x40038000
|
||||
#define PNX4008_WDOG_BASE 0x4003C000
|
||||
#define PNX4008_DEBUG_BASE 0x40040000
|
||||
#define PNX4008_TOUCH1_BASE 0x40048000
|
||||
#define PNX4008_KEYSCAN_BASE 0x40050000
|
||||
#define PNX4008_UARTCTRL_BASE 0x40054000
|
||||
#define PNX4008_PWM_BASE 0x4005C000
|
||||
#define PNX4008_UART3_BASE 0x40080000
|
||||
#define PNX4008_UART4_BASE 0x40088000
|
||||
#define PNX4008_UART5_BASE 0x40090000
|
||||
#define PNX4008_UART6_BASE 0x40098000
|
||||
#define PNX4008_I2C1_BASE 0x400A0000
|
||||
#define PNX4008_I2C2_BASE 0x400A8000
|
||||
#define PNX4008_MAGICGATE_BASE 0x400B0000
|
||||
#define PNX4008_DUMCONF_BASE 0x400B8000
|
||||
#define PNX4008_DUM_MAINCFG_BASE 0x400BC000
|
||||
#define PNX4008_DSP_BASE 0x400C0000
|
||||
#define PNX4008_PROFCOUNTER_BASE 0x400C8000
|
||||
#define PNX4008_CRYPTO_BASE 0x400D0000
|
||||
#define PNX4008_CAMIFCONF_BASE 0x400D8000
|
||||
#define PNX4008_YUV2RGB_BASE 0x400E0000
|
||||
#define PNX4008_AUDIOCONFIG_BASE 0x400E8000
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* include/asm-arm/arch-pnx4008/pm.h
|
||||
*
|
||||
* PNX4008 Power Management Routiness - header file
|
||||
*
|
||||
* Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_PNX4008_PM_H
|
||||
#define __ASM_ARCH_PNX4008_PM_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include "irq.h"
|
||||
#include "irqs.h"
|
||||
#include "clock.h"
|
||||
|
||||
extern void pnx4008_pm_idle(void);
|
||||
extern void pnx4008_pm_suspend(void);
|
||||
extern unsigned int pnx4008_cpu_suspend_sz;
|
||||
extern void pnx4008_cpu_suspend(void);
|
||||
extern unsigned int pnx4008_cpu_standby_sz;
|
||||
extern void pnx4008_cpu_standby(void);
|
||||
|
||||
extern int pnx4008_startup_pll(struct clk *);
|
||||
extern int pnx4008_shutdown_pll(struct clk *);
|
||||
|
||||
static inline void start_int_umask(u8 irq)
|
||||
{
|
||||
__raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
|
||||
START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
|
||||
}
|
||||
|
||||
static inline void start_int_mask(u8 irq)
|
||||
{
|
||||
__raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
|
||||
~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
|
||||
}
|
||||
|
||||
static inline void start_int_ack(u8 irq)
|
||||
{
|
||||
__raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
|
||||
}
|
||||
|
||||
static inline void start_int_set_falling_edge(u8 irq)
|
||||
{
|
||||
__raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
|
||||
~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
|
||||
}
|
||||
|
||||
static inline void start_int_set_rising_edge(u8 irq)
|
||||
{
|
||||
__raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
|
||||
START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
|
||||
}
|
||||
|
||||
#endif /* ASSEMBLER */
|
||||
#endif /* __ASM_ARCH_PNX4008_PM_H */
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-pnx4008/system.h
|
||||
*
|
||||
* Copyright (C) 2003 Philips Semiconductors
|
||||
* Copyright (C) 2005 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/platform.h>
|
||||
|
||||
static void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
cpu_reset(0);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* include/asm-arm/arch-pnx4008/timex.h
|
||||
*
|
||||
* PNX4008 timers header file
|
||||
*
|
||||
* Author: Dmitry Chigirev <source@mvista.com>
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#ifndef __PNX4008_TIMEX_H
|
||||
#define __PNX4008_TIMEX_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define CLOCK_TICK_RATE 1000000
|
||||
|
||||
#define TICKS2USECS(x) (x)
|
||||
|
||||
/* MilliSecond Timer - Chapter 21 Page 202 */
|
||||
|
||||
#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
|
||||
#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
|
||||
#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
|
||||
#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
|
||||
#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
|
||||
#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
|
||||
|
||||
/* High Speed Timer - Chpater 22, Page 205 */
|
||||
|
||||
#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
|
||||
#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
|
||||
#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
|
||||
#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
|
||||
#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
|
||||
#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
|
||||
#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
|
||||
#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
|
||||
#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
|
||||
#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
|
||||
#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
|
||||
#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
|
||||
|
||||
/* IMPORTANT: both timers are UPCOUNTING */
|
||||
|
||||
/* xSTIM_MCTRL bit definitions */
|
||||
#define MR0_INT 1
|
||||
#define RESET_COUNT0 (1<<1)
|
||||
#define STOP_COUNT0 (1<<2)
|
||||
#define MR1_INT (1<<3)
|
||||
#define RESET_COUNT1 (1<<4)
|
||||
#define STOP_COUNT1 (1<<5)
|
||||
#define MR2_INT (1<<6)
|
||||
#define RESET_COUNT2 (1<<7)
|
||||
#define STOP_COUNT2 (1<<8)
|
||||
|
||||
/* xSTIM_CTRL bit definitions */
|
||||
#define COUNT_ENAB 1
|
||||
#define RESET_COUNT (1<<1)
|
||||
#define DEBUG_EN (1<<2)
|
||||
|
||||
/* xSTIM_INT bit definitions */
|
||||
#define MATCH0_INT 1
|
||||
#define MATCH1_INT (1<<1)
|
||||
#define MATCH2_INT (1<<2)
|
||||
#define RTC_TICK0 (1<<4)
|
||||
#define RTC_TICK1 (1<<5)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-pnx4008/uncompress.h
|
||||
*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
* Copyright (C) 2006 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#define UART5_BASE 0x40090000
|
||||
|
||||
#define UART5_DR (*(volatile unsigned char *) (UART5_BASE))
|
||||
#define UART5_FR (*(volatile unsigned char *) (UART5_BASE + 18))
|
||||
|
||||
static __inline__ void putc(char c)
|
||||
{
|
||||
while (UART5_FR & (1 << 5))
|
||||
barrier();
|
||||
|
||||
UART5_DR = c;
|
||||
}
|
||||
|
||||
/*
|
||||
* This does not append a newline
|
||||
*/
|
||||
static inline void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup()
|
||||
#define arch_decomp_wdog()
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* include/asm-arm/arch-pnx4008/vmalloc.h
|
||||
*
|
||||
* Author: Vitaly Wool <source@mvista.com>
|
||||
*
|
||||
* 2006 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Just any arbitrary offset to the start of the vmalloc VM area: the
|
||||
* current 8MB value just means that there will be a 8MB "hole" after the
|
||||
* physical memory until the kernel virtual memory starts. That means that
|
||||
* any out-of-bounds memory accesses will hopefully be caught.
|
||||
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
|
||||
* area for the same reason. ;)
|
||||
*/
|
||||
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
|
||||
@@ -126,9 +126,18 @@
|
||||
#define S3C24XX_SZ_IIS SZ_1M
|
||||
|
||||
/* GPIO ports */
|
||||
#define S3C24XX_VA_GPIO S3C2410_ADDR(0x00E00000)
|
||||
|
||||
/* the calculation for the VA of this must ensure that
|
||||
* it is the same distance apart from the UART in the
|
||||
* phsyical address space, as the initial mapping for the IO
|
||||
* is done as a 1:1 maping. This puts it (currently) at
|
||||
* 0xF6800000, which is not in the way of any current mapping
|
||||
* by the base system.
|
||||
*/
|
||||
|
||||
#define S3C2400_PA_GPIO (0x15600000)
|
||||
#define S3C2410_PA_GPIO (0x56000000)
|
||||
#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
|
||||
#define S3C24XX_SZ_GPIO SZ_1M
|
||||
|
||||
/* RTC */
|
||||
|
||||
@@ -114,7 +114,7 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
|
||||
|
||||
/* extra registers */
|
||||
#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
|
||||
@@ -136,7 +136,9 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
|
||||
#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
|
||||
#define S3C2440_CAMDIVN_DVSEN (1<<12)
|
||||
|
||||
#endif /* CONFIG_CPU_S3C2440 */
|
||||
#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5)
|
||||
|
||||
#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
|
||||
|
||||
|
||||
#endif /* __ASM_ARM_REGS_CLOCK */
|
||||
|
||||
@@ -450,12 +450,14 @@
|
||||
#define S3C2410_GPD0_OUTP (0x01 << 0)
|
||||
#define S3C2410_GPD0_VD8 (0x02 << 0)
|
||||
#define S3C2400_GPD0_VFRAME (0x02 << 0)
|
||||
#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
|
||||
|
||||
#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
|
||||
#define S3C2410_GPD1_INP (0x00 << 2)
|
||||
#define S3C2410_GPD1_OUTP (0x01 << 2)
|
||||
#define S3C2410_GPD1_VD9 (0x02 << 2)
|
||||
#define S3C2400_GPD1_VM (0x02 << 2)
|
||||
#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
|
||||
|
||||
#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
|
||||
#define S3C2410_GPD2_INP (0x00 << 4)
|
||||
@@ -858,6 +860,7 @@
|
||||
#define S3C2410_GPG12_OUTP (0x01 << 24)
|
||||
#define S3C2410_GPG12_EINT20 (0x02 << 24)
|
||||
#define S3C2410_GPG12_XMON (0x03 << 24)
|
||||
#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
|
||||
|
||||
#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
|
||||
#define S3C2410_GPG13_INP (0x00 << 26)
|
||||
@@ -943,6 +946,7 @@
|
||||
#define S3C2410_GPH9_INP (0x00 << 18)
|
||||
#define S3C2410_GPH9_OUTP (0x01 << 18)
|
||||
#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
|
||||
#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
|
||||
|
||||
#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
|
||||
#define S3C2410_GPH10_INP (0x00 << 20)
|
||||
@@ -1051,6 +1055,7 @@
|
||||
#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
|
||||
#define S3C2410_GSTATUS1_2410 (0x32410000)
|
||||
#define S3C2410_GSTATUS1_2440 (0x32440000)
|
||||
#define S3C2410_GSTATUS1_2442 (0x32440aaa)
|
||||
|
||||
#define S3C2410_GSTATUS2_WTRESET (1<<2)
|
||||
#define S3C2410_GSTATUS2_OFFRESET (1<<1)
|
||||
|
||||
@@ -82,7 +82,8 @@ static void putc(int ch)
|
||||
while (1) {
|
||||
level = uart_rd(S3C2410_UFSTAT);
|
||||
|
||||
if (cpuid == S3C2410_GSTATUS1_2440) {
|
||||
if (cpuid == S3C2410_GSTATUS1_2440 ||
|
||||
cpuid == S3C2410_GSTATUS1_2442) {
|
||||
level &= S3C2440_UFSTAT_TXMASK;
|
||||
level >>= S3C2440_UFSTAT_TXSHIFT;
|
||||
} else {
|
||||
@@ -130,7 +131,7 @@ static void arch_decomp_wdog_start(void)
|
||||
{
|
||||
__raw_writel(WDOG_COUNT, S3C2410_WTDAT);
|
||||
__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
|
||||
__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
|
||||
__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
@@ -50,6 +50,7 @@ struct sys_timer {
|
||||
#define DYN_TICK_ENABLED (1 << 1)
|
||||
|
||||
struct dyn_tick_timer {
|
||||
spinlock_t lock;
|
||||
unsigned int state; /* Current state */
|
||||
int (*enable)(void); /* Enables dynamic tick */
|
||||
int (*disable)(void); /* Disables dynamic tick */
|
||||
|
||||
Reference in New Issue
Block a user